MITEL SP8401KGMPES

SP8401
Very Low Phase Noise 300MHz ÷10/11
Supersedes February 1992 edition
DS3230 - 3.1 April 1994
The SP8401 is a very low phase noise variable modulus
divider. Special circuit techniques have been used to reduce
the phase noise considerably below that produced by standard
dividers. The modulus control input is CMOS or TTL
compatible.
The SP8401 is packaged in a 28 pin plastic SO package to
be compatible with the SP8400 and SP8402 devices.
N/C
N/C
N/C
VCC +5V
GND
CLOCK INPUT
CLOCK INPUT
CLOCK INPUT
CLOCK INPUT
GND
FEATURES
■ Very low Phase Noise (Typically -160dBc/Hz at 1kHz
offset)
■ Supply Voltage 5V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Output Current
Storage Temperature Range
Maximum Clock Input Voltage
6.5V
20mA
-55°C to +125°C
2.5V p-p
VCC +5V
VCC +5V
N/C
MODULUS CONTROL
1
2
3
4
28
27
26
25
5
6
7
8
24
23
22
21
9
10
11
12
20
19
18
17
13
14
16
15
N/C
N/C
N/C
N/C
N/C
N/C
N/C
OUTPUT
OUTPUT
N/C
VCC +5V
N/C
N/C
N/C
MP28
Fig.1 Pin connections - top view
ORDERING INFORMATION
SP8401 KG MPES(Commercial Grade)
0
–10
–20
–30
–40
(f) (dBc/Hz) –3dB
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
1
10
100
1k
Frequency (Hz)
Fig.2 Typical single sideband phase noise measured at 300MHz
10k
100k
SP8400
ELECTRICAL CHARACTERISTICS
Guaranteed over: Supply voltage VCC = +4.75V to +5.25V Temperature Tamb = -10°C to +75°C
Tested at +4.75V and +5.25V at Tamb = +25°C
Characteristic
Value
Pin
4, 11, 12, 18
20, 21
Supply current
Output voltage swing
Input sensitivity 50MHz to 300MHz
7, 8
Modulus Control Inputs
Logic high voltage
Low low voltage
Input current
Set up time ts
Release time tr
14
14
14
14
14
Units
Min.
Typ. Max.
50
340
57
440
64
mA
mV
140
(-4)
mV
dBm
2.2
V
0.8
180
µA
ns
ns
4
4
Conditions
Output loaded with 300R See Fig.5
p-p @ 330MHz input ÷ 11 mode
Output loaded with 300R
RMS Sine wave into 50 Ohms
(dBm equivalent) See Fig.3
÷ 10 mode
÷ 11 mode
Modulus control input voltage 5V
400
VIN mVRMS
355mV
300
OPERATING WINDOW
200
140mV
100
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
Fig.3 Typical input sensitivity
CLOCK INPUT
MODULUS
CONTROL
INPUT
ts
tr
6
5
5
OUTPUT
Fig.4 Timing diagram
2
300
350
SP8400
VCC
1nF
1
28
2
27
3
26
4
25
5
24
6
23
7
8
50R
RF
SIGNAL
GENERATOR
TTL/CMOS
MODULUS
CONTROL
22
SP8401
220nF OUTPUT
21
9
20
10
19
11
18
12
17
13
16
14
15
50R
1nF
10nF
1nF
2x330R
10nF
Fig.4 Test circuit
3
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