MITEL SP8852EKGHCAR

SP8852E
2·7GHz Parallel Load Professional Synthesiser
Preliminary Information
FEATURES
■ 2·7 GHz Operating Frequency
■ Single 5V Supply
■ Low Power Consumption <1·3W
■ High Comparison Frequency : 20MHz
■ High Gain Phase Detector : 1mA/rad
■ Zero ‘Dead Band’ Phase Detector
■ Wide Range of RF and Reference Division Ratios
■ Programming by Dual Word Data Transfer
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Operating temperature
Storage temperature
Prescaler and reference input voltage
Data inputs
Junction temperature
1 44
B4
B3
B2
B1
B0
0V (PRESCALER)
RF INPUT
RF INPUT
VCC (PRESCALER)
VEE
LOCK DETECT
SP8852E
C-LOCK DETECT
RSET
CHARGE PUMP OUTPUT
CHARGE PUMP REF
NC
NC
FPD*
FREF*
VCC
REF OSC CAPACITOR
REF IN/CRYSTAL
The SP8852E is one of a family of parallel load synthesisers
containing all the elements apart from the loop amplifier to
fabricate a PLL synthesis loop. Other parts in the series are
the SP8854E which has hard wired reference counter programming and requires only a single 16-bit programming
word, and the SP8855E which is fully programmable using
hard wired links or switches.
The SP8852E is programmed using a 16-bit parallel data
bus. Data can be stored in one of two internal buffers, selected
by a single address bit on the input interface. In order to fully
program the device, two 16-bit words are required, one to
select the RF division ratio (A and M counters) and phase
detector gain, and one to set the 10-bit reference divider
count, phase detector state and sense. Once the reference
divide ratio has been set, frequency changes can be made by
a single 16-bit data load entry to the RF divider chain.
DS4237 - 2.0 June 1998
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
Supersedes January 1996 version, DS4237 - 1.2
ORDERING INFORMATION
SP8852E KG HCAR Non-standard temperature range,
255°C to 1100°C, standard product screening
SP8852E IG HCAR Industrial temperature range,
240°C to 185°C, standard product screening
HC44
*FPD and FREF outputs are reversed by the phase
detector sense bit in the F1/F2 programming word, bit
12. The above diagram is correct when bit 12 is high.
Fig. 1 Pin connections - top view
THERMAL DATA
20·3V to 16V
255°C to1100°C
265°C to 1150°C
2·5Vp-p
VCC 10·3V
VEE 20·3V
1175°C
STROBE
ADDRESS
NC
NC
NC
NC
NC
NC
NC
NC
NC
uJC = 5°C/W
uJA = 53°C/W
ESD PROTECTION
1000V, human body model
SP8852E
VCC
PRESCALER
RF INPUT
RF INPUT
MODULUS
CONTROL
15
13
3-BIT
A COUNTER
48/9
14
FPD
11-BIT
M COUNTER
14
0V
PRESCALER
B0
STROBE
ADDRESS
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B2
B3
B13 B14
RF BUFFER
38
20
11
21
10
17
9
PHASE
DETECTOR
8
7
6
18
25
LOAD
5
4
19
24
CHARGE PUMP OUTPUT
CHARGE PUMP REFERENCE
LOCK DETECT OUTPUT
RSET
C-LOCK DETECT
FPD*
FREF*
REFERENCE BUFFER
INPUT
INTERFACE
B0
B9
B10
B12
3
2
10-BIT REFERENCE
DIVIDER
1
FREF
44
43
42
*FREF and FPD outputs are reversed
by the phase detector sense bit, bit 12
in the programming word. The pin
allocations shown are correct when
bit 12 is high.
41
40
28
REFERENCE
CRYSTAL
27
REFERENCE
CAPACITOR
Fig. 2 Block diagram
2
B15
LOAD
39
26
16
VCC
VEE
SP8852E
Description
Pin
1-11, 40-44
These are the inputs to the 16-bit data bus. When pin 38 is high the data goes to the buffers for
the A counter, M counter and phase detector gain. When pin 38 is low the data goes to the buffers
for the reference counter and the phase detector state (see Table 4). Open circuit = 1 (high) on
these pins. Data is transparent from pins to the selected buffers when pin 39 (STROBE) is high
and frozen in buffers when pin 39 is low.
13 (RF INPUT)
Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into
pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC
biased.
14 (RF INPUT)
17 (LOCK DETECT INPUT)
A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give
an external indication of phase lock.
18 (C-LOCK DETECT)
A capacitor connected to this point determines the lock detect integrator time constant and can
be used to vary the sensitivity of the phase lock indicator.
19 (RSET)
An external resistor from pin 19 to VCC sets the charge pump output current.
20 (CHARGE PUMP OUTPUT)
The phase detector output is a single ended charge pump sourcing or sinking current to the
inverting input of an external loop filter. The direction is controlled by bit 12 of the reference word.
For bit 12 = 1 and FPD or RF phase leads Ref phase pin 20 will sink current (see Table 3).
21 (CHARGE PUMP REF)
Connected to the non-inverting input of the loop filter to set the optimum DC bias.
22
Not Connected.
23
Not connected.
24
FPD if pin 23 is high
FREF if pin 23 is low
RF divider output pulses. FPD = RF input frequency/(M.N1A). Pulse width = 8 RF input cycles
(1 cycle of the divide by 8 prescaler output).
25
FPD if pin 23 is low
FREF if pin 23 is high
Reference divider output pulses. FREF = reference input frequency/R. Pulse width = high period
of Ref input.
27 (Ref. oscillator capacitor)
Leave open circuit if an external reference is used. See Fig. 5 for typical connection for use as
an onboard crystal oscillator.
28 (REF IN/XTAL)
This pin is the input buffer amplifier for an external reference signal. This amplifier provides the
active element if an onboard crystal oscillator is used.
29-37
Not connected.
38 (ADDRESS)
Controls which buffer the data on the input bus goes to. Pin 38 high sends data to the RF divider
group of functions. Pin 38 low sends data to the Ref divider group of functions (see Fig. 6). Open
circuit = high.
39 (STROBE)
When pin 39 is high the A, M, and R counters are held in the reset state and the charge pump
output is disabled. The data on the input bus is loaded into the buffers selected by the ADDRESS
input state (pin 38) when pin 39 goes low. When pin 39 is low the data is fixed in the buffers, the
buffers are loaded into the counter and control register, all the counters are active, and the
charge pump is enabled. Open circuit = high.
Table 1 Pin descriptions
3
SP8852E
ELECTRICAL CHARACTERISTICS
The Electrical Characteristics are guaranteed over the following range of operating conditions unless otherwise stated
TAMB = 2 55°C to 1100°C (KG parts), 2 40°C to 185°C (IG parts); VCC = 4·75V to 5·25V
Value
Characteristic
Pin
Min.
Max.
180
240
mA
dBm
Supply current
18, 26
RF input sensitivity
13,14
25
17
13,14, 24
56
16383
Reference division ratio
28, 25
1
1023
Comparison frequency
28, 24, 25
RF division ratio
Reference input frequency
28
10
Reference input voltage
28
0
Units
Typ.
16
50
MHz
100
MHz
110
dBm
Conditions
100MHz to 2·7GHz. See note 3.
Ref division ratio >2. See note 1
FREF/FPD output voltage high
24, 25
20·8
V
WRT VCC, 2·2kΩ to 0V
FREF/FPD output voltage low
24, 25
21·4
V
WRT VCC, 2·2kΩ to 0V
17
300
500
mV
IOUT = 3mA
61·4
61·5
61·7
mA
VPIN20 = VPIN21, IPIN19 = 1·6mA,
62·0
62·3
62·5
mA
63·4
63·8
64·1
mA
65·4
66·1
66·5
mA
LOCK DETECT output voltage
CHARGE PUMP current
19, 20, 21
multiplication factor = 1
VPIN20 = VPIN21, IPIN19 = 1·6mA,
multiplication factor = 1·5
VPIN20 = VPIN21, IPIN19 = 1·6mA,
multiplication factor = 2·5
VPIN20 = VPIN21, IPIN19 = 1·6mA,
multiplication factor = 4·0
Input bus logic level high
1-11, 38-44
Input bus logic level low
1-11, 38-44
Input bus current source
1-11, 38-44 2200
Input bus current sink
1-11, 38-44
Up/down current matching
CHARGE PUMP REFERENCE voltage
V
3·5
1
V
µA
VIN = 0V
10
µA
VIN = VCC
20
65
%
VPIN20 = VPIN21, IPIN19 = 1·6mA
21
VCC20·5
V
IPIN19 = 1·6mA, current
multiplication factor = 1·0
V
VCC21·6
IPIN19 = 1·6mA, current
multiplication factor = 4·0
2
mA
RSET current
19
RSET voltage
19
1·6
V
IPIN19 = 1·6mA
C-LOCK DETECT current
18
110
µA
VPIN18 = 4·7V
0·5
Note 2
STROBE pulse width
50
ns
Note 3
Data setup time
100
ns
Note 3
NOTES
1. Lower frequencies may be used provided that slew rates are maintained.
2. Pin 19 current3multiplication factor must be less than 5mA if charge pump accuracy is to be maintained.
3. Guranteed but not tested.
4
SP8852E
120
RF INPUT TO PIN 13 (dBm)
TYPICAL OVERLOAD
110
17
GUARANTEED
OPERATING WINDOW
0
25
210
220
TYPICAL SENSITIVITY
230
100MHz
1GHz
2GHz 2·7GHz
10GHz
FREQUENCY
Fig. 3 Input sensitivity
j1
j 0.5
j2
ZO = 50Ω
j 0.2
j5
0.2
0
0.5
1
2
5
50MHz
1·1GHz
2·5GHz
2j 5
2j 0.2
2j 2
2j 0.5
2j 1
Fig. 4 RF input impedance
5
SP8852E
ADDRESS
STROBE
CONTROL
MICRO
15V
1k
7
6
5
4
3
1n
1 44 43 42 41 40
39
8
38
9
37
10
36
11
35
12
15V
2
34
SP8852E
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
1n
SP8852E
1n
1n
100p
REF IN
27 28
2·2k
FREF
LOOP FILTER
*
*
33p
100p
*
1µ
130V
10MHZ
FPD
15V
10n
−
Application using
crystal reference
VCO
OP27
ETC
+
DEPEND
* VALUES
ON APPLICATION
Fig. 5 Typical application diagram
DESCRIPTION
Prescaler and AM counter The programmable divider
chain is of A and M counter construction and therefore
contains a dual modulus front end prescaler, an A counter
which controls the dual modulus ratio and an M counter which
performs the bulk multi-modulus division. A programmable
divider of this construction has a division ratio of MN1A and
a minimum integer steppable division ratio of N(N21), where
N is the prescaler value.
Data Entry and Storage
Data is loaded from the 16-bit bus into one of the internal
buffers by applying a positive pulse to the STROBE input. The
input bus can be driven from TTL or CMOS logic levels. When
6
STROBE is low, the inputs are isolated and the data can be
changed without affecting the programmed state.
The data is loaded into the RF buffer when the address
input is high and into the reference buffer when low. When the
STROBE input is taken high, the A and M and reference
counters are reset and the input data is applied to the internal
storage register. When STROBE is again taken low, the data
on the input bus is stored in the selected register and the
counters released. The STROBE input is level triggered so
that if the data is changed whilst the input is high, the final
value before STROBE goes low will be stored.
In order to prevent disturbances on the VCO control voltage
when frequency changes are made, the STROBE input disables
SP8852E
the charge pump outputs when high. During this period the
VCO control voltage will be maintained by the loop filter
components around the loop amplifier, but due to the combined effects of the amplifier input current and charge pump
leakage a gradual change will occur. In order to reduce the
change, the duration of the strobe pulse should be minimised.
Selection of a loop amplifier with low input current will reduce
the VCO voltage droop during the strobe pulse and result in
minimum reference sidebands from the synthesiser.
Output for RF phase lag
Sense bit (bit 12)
Pin 20
1
Current source
0
Current sink
The SP8852E has a digital phase/frequency comparator
driving a charge pump with programmable current output.
The charge pump current level at the minimum gain setting is
approximately equal to the current fed into the RSET input, pin
19, and can be increased by programming the bus according
to Table 2 by up to 4 times.
Table 3
The FPD and FREF signals to the phase detector are
available on pins 24 and 25 and may be used to monitor the
frequency input to the phase detector or used in conjunction
with an external phase detector. These outputs may be
programmed by bits 10 and 11 of word 0 according to Table 4.
State 3, where the outputs are disabled by the lock detect
circuit, is useful where the user wishes to use an external
phase detector. The internal phase/frequency detector may
be used to pull the loop into lock and an automatic switch-over
to the external phase detector made. When the FPD and FREF
outputs are to be used at high frequencies, an external pull
down resistor of minimum value 330Ω may be connected to
ground to reduce the fall time of the output pulse.
Bit 15 Bit 14
Bit 11 Bit 10
Reference Input
The reference source can be either driven from an external
sine or square wave source of up to 100MHz or a crystal can
be connected as shown in Fig. 5.
Phase Comparator and Charge Pump
Current multiplication factor
Phase detector state
0
0
1·0
0
0
Enabled, FPD and FREF off
0
1
1·5
0
1
Enabled, FPD and FREF on
1
0
2·5
1
0
Disabled by lock detect, FPD and FREF on
1
1
4·0
1
1
Disabled, FPD and FREF on
Table 2
Pin 19 current =
Table 4
The charge pump connections to the loop amplifier consist
of the charge pump output and the charge pump reference.
The matching of the charge pump up and down currents will
only be maintained if the charge pump output is held at a
voltage equal to the charge pump reference using an
operational amplifier to produce a virtual earth condition at pin
20. The lock detect circuit can drive an LED to give visual
indication of phase lock or provide an indication to the control
system if a pullup resistor is used in place of the LED. A small
capacitor connected form the C-LOCK DETECTOR pin to
ground may be used to delay lock detect indication and
remove glitches produced by momentary phase coincidence
during lock up.
VCC21·6V
RSET
Phase detector gain =
IPIN19 (mA)3multiplication factor
mA/rad
2p
To allow for control direction changes introduced by the
design of the PLL, bit 12 on the input bus address 0 can be
programmed to reverse the sense of the phase detector by
transposing the FPD and FREF connections. In order that any
external phase detector will also be reversed by this programming bit, the FPD and FREF outputs are also interchanged by
bit 12 as shown in Table 3.
PIN 40
BIT 15
PIN 11
BIT 0



ADDRESS
NOT USED
PHASE
DETECTOR
SENSE
CONTROL
(SEE TABLE 3)
28
27
26
25
24
23
22
21
20


















29
0
PHASE
DETECTOR
STATE
CONTROL
(SEE TABLE 4)
10-BIT REFERENCE COUNTER
Fig. 6a Reference word bit allocation
PIN 40
BIT 15
PIN 11
BIT 0
213 212 211 210 29
27
26
25
24
23
22
21
20






ADDRESS
28















1
PHASE
DETECTOR
GAIN
CONTROL
(SEE TABLE 2)
M COUNTER
3-BIT
A COUNTER
Fig. 6b RF division ratio bit allocation
Fig. 6 Programming data format
7
SP8852E
VCC
VCC
40k
40k
5k
4k
5k
325
325
INPUT
500
500
13
RF INPUT
14
RF INPUT
50µA
3mA
3k
0V
0V
Fig. 7b RF inputs
Fig. 7a 16-bit input bus, strobe and address
VCC
C-LOCK DETECT
(HIGH WHEN LOCKED)
2·5k
18
2·5k
VCC
3k
3k
LOCK DETECT OUTPUT
(LOW WHEN LOCKED)
VREF
4·7V
20µA
3k
17
3k
400µA
100µA
100
100
1k
1k
0V
0V
Fig. 7d Lock detect output
Fig. 7c Lock detect decouple
VCC
RSET
450
19
450
VCC
f UP
CHARGE PUMP
CURRENT SOURCES
83
f UP
VCC
83
20
OUTPUT
21
REFERENCE
f DN
f DN
130
0V
2mA
0V
Fig. 7e RSET pin
Fig. 7f Charge pump circuit
Fig 7 Interface circuit diagrams
8
SP8852E
VCC
VCC
296
296
40k
3k
3k
40k
296
28
24, 25 FPD, FREF
OUTPUTS
CRYSTAL
CAPACITOR
27
60k
60k
50µA
50µA
3·3mA
0V
0V
Fig. 7g FPD and FREF outputs
100µA
100µA
100µA
Fig. 7h Reference oscillator
Fig. 7 Interface circuit diagrams (continued)
APPLICATIONS
RF Layout
Lock Detect Circuit
The SP8852E can operate with input frequencies up to
2·7GHz but to obtain optimum performance, good RF layout
practices should be used. A suitable layout technique is to use
double sided printed circuit board with through plated holes.
Wherever possible the top surface on which the SP8852E is
mounted should be left as a continuous sheet of copper to
form a low impedance ground plane. The ground pins 12 and
16 should be connected directly to the ground plane.
Pins such as VCC and the unused RF input should be
decoupled with chip capacitors mounted as close to the
device pin as possible, with a direct connection to the ground
plane; suitable values are 10nF for the power supplies and
<1nF for the RF input pin (a lower value should be used
sufficient to give good decoupling at the RF frequency of
operation). A larger decoupling capacitor mounted as close
as possible to pin 26 should be used to prevent modulation of
VCC by the charge pump pulses. The RSET resistor should also
be mounted close to the RSET pin to prevent noise pickup. The
capacitor connected from the charge pump output should be
a chip component with short connections to the SP8852E. All
signals such as the programming inputs, RF IN, REFERENCE
IN and the connections to the op-amp are best taken through
the pc board adjacent to the SP8852D with through plated
holes allowing connections to remote points without
fragmenting the ground plane.
The input pins are designed to be compatible with TTL or
CMOS logic with a switching threshold set at about 2·4V by
three forward biased base-emitter diodes. The inputs will be
taken high by an internal pull up resistor if left open circuit but
for best noise immunity it is better to connect unused inputs
directly to VCC or ground.
The lock detect circuit uses the up and down correction
pulses from the phase detector to determine whether the loop
is in or out of lock. When the loop is locked, both up and down
pulses are very narrow compared to the reference frequency,
but the pulse width in the out of lock condition continuously
varies, depending on the phase difference between the outputs
of the reference and RF counters. The logical AND of the up
and down pulses is used to switch a 20mA current sink to pin
18 and a 50kΩ resistor provides a load to VCC. The circuit is
shown in Fig. 7c.
When lock is established, the narrow pulses from the
phase detector ensure that the current source is off for the
majority of the time and so pin 18 will be pulled high by the
50kΩ resistor. A voltage comparator with a switching threshold
at about 4·7V monitors the voltage at pin 18 and switches pin
17 low when pin 18 is more positive than the 4·7V threshold.
When the loop is unlocked, the frequency difference at the
counter outputs will produce a cyclic change in pulse width
from the phase detector outputs with a frequency equal to the
difference at the reference and RF counter outputs. A small
capacitor connected to pin 18 prevents the indication of false
phase lock conditions at pin 17 for momentary phase
coincidence. Because of the variable width pulse nature of the
signal at pin 18 the calculation of a suitable capacitor value is
complex, but if an indication with a delay amounting to several
times the expected lock up time is acceptable, the delay will
be approximately equal to the time constant of the capacitor
on pin 18 and the internal 50kΩ resistor. If a faster indication
is required, comparable with the loop lock up time, the
capacitor will need to be 2 to 3 times smaller than the time
constant calculation suggests. The time to respond to an out
of lock condition is 2 to 3 times less than that required to
indicate lock.
RF Inputs
Charge Pump Circuit
The prescaler has a differential input amplifier to improve
input sensitivity. Generally the input drive will be single ended
and the RF signal should be AC coupled to either of the inputs
using a chip capacitor.The remaining input should be decoupled
to ground, again using a chip capacitor. The inputs can be driven
differentially but the input circuit should not provide a DC path
between inputs or to ground.
The charge pump circuit converts the variable width up and
down pulses from the phase detector into adjustable current
pulses which can be directly connected to the loop amplifier.
The magnitude of the current and therefore the phase detector gain can be modified when new frequency data is entered
to compensate for change in the VCO gain characteristic over
Programming Bus
9
SP8852E
its frequency band. The charge pump pulse current is determined
by the current fed into pin 19 and is approximately equal to pin
19 current when the programmed multiplication ratio is 1. The
circuit diagram Fig. 7e shows the internal components on pin 19
which mirror the input current into the charge pump. The voltage
at pin 19 will be approximately 1·6V above ground due to two VBE
drops in the current mirror. This voltage will exhibit a negative
temperature coefficient, causing the charge pump current to
change with chip temperature by up to 10% over the full military
temperature range if the current programming resistor is
connected to VCC as shown in the application diagram, Fig. 5. In
critical applications where this change in charge pump current
would be too large the resistor to pin 19 could be increased in
value and connected to a higher supply to reduce the effect of VBE
variation on the current level. A suitable resistor connected to a
30V supply would reduce the variation in pin 19 current due to
temperature to less than 1·5%. Alternatively a stable current
source could be used to set pin 19 current.
The charge pump output on pin 20 will only produce
symmetrical up and down currents if the voltage is equal to that
on the voltage reference pin 21. In order to ensure that this
voltage relationship is maintained, an operational amplifier must
be used as shown in the typical application Fig. 5. Using this
configuration pin 20 voltage will be forced to be equal to that on
pin 21 since the operational amplifier differential input voltage will
be no more than a few millivolts (the input offset voltage of the
amplifier).
When the synthesiser is first switched on or when a frequency
outside the VCO range is programmed, the amplifier output will
limit, allowing pin 20 voltage to differ from that on pin 21. As soon
as an achievable frequency value is programmed and the
amplifier output starts to slew the correct voltage relationship
between pin 20 and 21 will be restored. Because of the importance
of voltage equality between the charge pump reference and
output pins, a resistor should never be connected in series with
the operational amplifier inverting input and pin 20, as is the case
with a phase detector giving voltage outputs. Any current drawn
from the charge pump reference pin should be limited to the few
microamps input current of a typical operational amplifier. A
resistor between the charge pump reference and the noninverting input could be added to provide isolation but the value
should not be so high that more than a few millivolts drop are
produced by the amplifier input current.
When selecting a suitable amplifier for the loop filter, a
number of parameters are important; input offset voltage in
most designs is only a few millivolts and an offset of 5mV will
produce a mismatch in the up and down currents of about 4%
with the charge pump multiplication factor set at 1. The
mismatch in up and down currents caused by input offset
voltage will be reduced in proportion to the charge pump
multiplication factor in use.
If the linearity of the phase detector about the normal phase
locked operating point is critical, the input offset voltage of most
amplifiers can be adjusted to near zero by means of a
potentiometer. The charge pump reference voltage on pin 21 is
about 1·3V below the positive supply and will change with
temperature and with the programmed charge pump multiplication
factor. In many cases it is convenient to operate the amplifier with
the negative power supply pin connected to 0V as this removes
the need for an additional power supply. The amplifier selected
must have a common mode range to within 3·4V (minimum
charge pump reference voltage) of the negative supply pin to
operate correctly without a negative supply. Most popular
amplifiers can be operated from a 30V positive supply to give a
wide VCO voltage drive range and have adequate common
10
mode range to operate with inputs at 13·4V with respect to the
negative supply.
Input bias and offset current levels to most operational
amplifiers are unlikely to be high enough to significantly affect the
accuracy of the charge pump circuit currents but the bias current
can be important in reducing reference side bands and local
oscillator drift during frequency changes.
When the loop is locked, the charge pump produces only very
narrow pulses of sufficient width to make up for any charge lost
from the loop filter components during the reference cycle. The
charge lost will be due to leakage from the charge pump output
pin and to the amplifier input bias current, the latter usually being
more significant. The result of the lost charge is a sawtooth ripple
on the VCO control line which frequency modulates the phase
locked oscillator at the reference frequency and its harmonics. A
similar effect will occur whenever the strobe input is taken high
during a programming sequence. In this case the charge pump
is disabled when the strobe input is high and any leakage current
will cause the oscillator to drift off frequency. To reduce this
effect, the duration of the strobe pulse should be minimised.
FPD and FREF Outputs
These outputs provide access to the outputs from the RF and
reference dividers and are provided for monitoring purposes
during product development or test, and for connection of an
external phase detector if required. The output circuit is of ECL
type, the circuit diagram being shown in Fig. 7g. The outputs can
be enabled or disabled under software control by the address 0
control word but are best left in the disabled state when not
required as the fast edge speeds on the output can increase the
level of reference sidebands on the synthesised oscillator.
The emitter follower outputs have no internal pulldown resistor to save current and if the outputs are required an external
pulldown resistor should be fitted. The value should be kept as
high as possible to reduce supply current, about 2·2kΩ being
suitable for monitoring with a high impedance oscilloscope probe
or for driving an AC-coupled 50Ω load. A minimum value for the
pulldown resistor is 330Ω.
When the FPD and FREF outputs are disabled the output level
will be at the logic low level of about 3·5V so that the additional
supply current due to the load resistors will be present even when
the outputs are disabled.
Reference Input
The reference input circuit functions as an input amplifier or
crystal oscillator. When an external reference signal is used this
is simply AC-coupled to pin 28, the base of the input emitter
follower. When a low phase noise synthesiser is required the
reference signal is critical since any noise present here will be
multiplied by the loop. To obtain the lowest possible phase noise
from the SP8852E it is best to use the highest possible reference
input frequency and to divide this down internally to obtain the
required frequency at the phase detector. The amplitude of the
reference input is also important, and a level close to the
maximum will give the lowest noise.
When the use of a low reference input frequency say 4 to
10MHz is essential some advantage may be gained by using a
limiting amplifier such as a CMOS gate to square up the
reference input. In cases where a suitable reference signal is not
available, it may be more convenient to use the input buffer as a
crystal oscillator in this case the emitter follower input transistor
is connected as a Colpitts oscillator with the crystal connected
from the base to ground and with the feedback necessary for
oscillation provided by a capacitor tap at the emitter. The
arrangement is shown inset in Fig. 5.
SP8852E
From equation (3):
C2
1
2tan 45°1
cos 45°
t3 =
100kHz32p
C1
R2
FROM
CHARGE PUMP
FROM
CHARGE PUMP
REFERENCE
−
+
From equation (2):
Generally, the third order filter configuration shown in Fig. 8
gives better results than the more commonly used second order
because the reference sidebands are reduced. Three equations
are required to determine values for the three constants, where
t1 = C1R1
t2 = R2 (C11C2)
t3 = C2R2
KfK0 11vn2 t22 
vn2N 11vn2 t32 
1
2
1
∴t2 = 3·84431026
Using these values in equation (1):
13102332p310MHz/V
1
2tan F0 1
cos F0
vn
…(1)
=
Since the phase detector used is linear over a range of 2p
radians, the phase detector gain is given by:
mA/radian
These values can now be substituted in equation (1) to obtain
a value for C1 and in equations (2) and (3) to determine values
for C2 and R2.
Example
Calculate values for a loop with the following parameters:
1000MHz
10MHz
1000MHz/100MHz = 100
2p310MHz/V
45°
6·3mA
The phase detector gain factor Kf = 6·3/2p = 1mA/radian
1
2
3[A]
11vn2 t22 
11vn2 t32 
11(100kHz32p)23(3·84431026)2
11(100kHz32p)23(65931029)2
1
2
t1 = 62832 212  6·833 
1·1714 
39·48310
…(3)
where
Kf is the phase detector gain factor in mA/radian
K0 is the VCO gain factor in radians/seconds/V
N is the division ratio from VCO to reference frequency
vn is the natural loop frequency
F0 is the phase margin, normally set to 45°
Phase comparator current setting
Kf =
2p
1003(100kHz32p)2
where A =
…(2)
vn2t32
Frequency to be synthesised
Reference frequency
Division ratio
K0 VCO gain factor
F0 phase margin
Phase comparator current
(100kHz32p)2365931029
t1 =
The equations are:
t3 =
1
t2 =
Loop Filter Design
t2 =
628319
∴t3 = 65931029
Fig. 8 Third order loop filter circuit diagram
t1 =
0·4142
=
TO VCO
= 1·593102932·415
∴t1 = 3·8431029
Now, t1 = C1 ∴ C1 = 3·84nF
t2 = R2 (C11C2)
t2 = C2R2
Substituting for C2:
t2 = R2 C11t3 

or, R2=
R2 
t22t3
C1
3·84431026265931029
0·015331026
∴R2 = 829·4Ω
=
t3 = C2R2 = t3
R2
=
65931029
829·4
∴C2 = 0·794nF
11
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