NJ88C24 Frequency Synthesiser with non-resettable counters DS2438 - 2.3 The NJ88C24 is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable ‘M’ counter, 7-bit programmable ‘A’ counter and the necessary control and latch circuitry for accepting and latching the input data. Data is presented serially under external control from a suitable microprocessor. Although 28 bits of data are initially required to program all counters, subsequent updating can be abbreviated to 17 bits, when only the ‘A’ and‘M’ counters require changing. The NJ88C24 is intended to be used in conjunction with a two-modulus prescaler such as the SP8710 or SP8705 series to produce a universal binary coded synthesiser for up to 1100MHz operation. PDA 1 16 CH PDB 2 15 RB LD 3 14 MC FIN 4 13 CAP NJ88C24 VSS 5 12 VDD 6 11 OSC IN 7 10 OSC OUT 8 9 18 17 16 15 NJ88C24 14 13 12 11 10 DG16, DP16 FEATURES ■ Low Power Consumption ■ ■ ■ ■ 1 2 3 4 5 6 7 8 9 PDA PDB NC ENABLE LD FIN CLOCK VSS DATA VDD NC NC OSC IN CH RB MC CAP ENABLE CLOCK DATA NC OSC OUT MP18 Fig.1 Pin connections - top view (not to scale) High Performance Sample and Hold Phase Detector ABSOLUTE MAXIMUM RATINGS Serial Input with Fast Update Feature 20·5V to 7V Supply voltage, VDD2VSS: Input voltage Open drain output, LD pin: All other pins: Storage temperature: >20MHz Input Frequency Fast Lock-up Time ORDERING INFORMATION 7V VSS20·3V to VDD10·3V 255°C to 1125°C (DP and MP packages) 265°C to 1150°C (DG package) NJ88C24 MA DG Ceramic DIL Package NJ88C24 MA DP Plastic DIL Package NJ88C24 MA MP Miniature Plastic DIL Package RB 15 (17) OSC IN OSC OUT 7 (9) REFERENCE COUNTER (11BITS) fr 42 8 (10) CAP CH 17 (15) 16 (18) SAMPLE/HOLD 1 (1) PDA PHASE DETECTOR LATCH 6 LATCH 7 LATCH 8 10 (12) DATA 12 (14) ENABLE CLOCK FIN VDD 11 (13) 4 (5) ‘R’ REGISTER fV ‘M’ REGISTER ‘A’ REGISTER LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 ‘M’ COUNTER (10 BITS) ‘A’ COUNTER (7 BITS) 2 (2) PDB 3 (4) LOCK DETECT (LD) VSS 6 (7) CONTROL LOGIC VSS FREQUENCY/ PHASE DETECTOR 5 (6) Fig.2 Block diagram 14 (16) MODULUS CONTROL OUTPUT (MC) NJ88C24 ELECTRICAL CHARACTERISTICS AT VDD = 5V Test conditions unless otherwise stated: VDD–VSS=5V ±0·5V. Temperature range = –40°C to +85°C DC Characteristics Value Characteristic Units Typ. Supply current Modulus Control Output (MC) High level Low level Lock Detect Output (LD) Low level Open drain pull-up voltage PDB Output High level Low level 3-state leakage current Conditions Max. 5·5 1.5 mA mA fosc, fFIN = 10MHz fosc, fFIN = 1MHz 0·4 V V ISOURCE = 1mA ISINK = 1mA 0·4 7·0 V V ISINK = 4mA 0·4 ±0·1 V V µA ISOURCE = 5mA ISINK = 5mA 4·6 4·6 Min. 0 to 5V square wave AC Characteristics Value Characteristic Units FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propagation delay, clock to modulus control MC Programming Inputs Clock high time, tCH Clock low time, tCL Enable set-up time, tES Enable hold time, tEH Data set-up time, tDS Data hold time, tDH Clock rise and fall times High level threshold Low level threshold Hysteresis Phase Detector Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Programming capacitor, CAP Output resistance, PDA Typ. 200 20 30 0·5 0·5 0·2 0·2 0·2 0·2 Conditions Max. 50 tCH 0·2 VDD20·8 0·8 1·0 500 5 1 1 5 mV RMS 10MHz AC-coupled sinewave MHz Input squarewave VDD to VSS, 25°C. ns See note 2 µs µs µs µs µs µs µs V V V ns kΩ nF nF kΩ Min. All timing periods are referenced to the negative transition of the clock waveform See note 1 See note 1 See note 1 See note 3 NOTES 1. Data, Clock and Enable inputs are high impedance Schmitt buffers without pull-up resistors; they are therefore not TTL compatible. 2. All counters have outputs directly synchronous with their respective clock rising edges. 3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs. 4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the signal/osc. frequency inputs. 2 NJ88C24 PIN DESCRIPTIONS Pin no. Name Description 1 PDA Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Voltage increases as fv (the output from the ‘M’ counter) phase lead increases; voltage decreases as fr (the output from the reference counter) phase lead increases. Output is linear over only a narrow phase window, determined by gain (programmed by RB). In a type 2 loop, this pin is at (VDD2VSS)/2 when the system is in lock. 2 2 PDB Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal. fv. fr or fv leading: positive pulses with respect to the bias point VBIAS fv , fr or fr leading: negative pulses with respect to the bias point VBIAS fv = fr and phase error within PDA window: high impedance. – 3 NC Not connected. 3 4 LD An open-drain lock detect output at low level when phase error is within PDA window (in lock); high impedance at all other times. 4 5 FIN The input to the main counters. It is normally driven from a prescaler, which may be AC-coupled or, when a full logic swing is available, may be DC-coupled. 5 6 VSS Negative supply (ground). 6 7 VDD Positive supply (normally 5V) – 8 NC Not connected. DG,DP MP 1 7, 8 9,10 OSC IN/ These pins form an on-chip reference oscillator when a series resonant crystal is connected across OSC OUT them. Capacitors of appropriate value are also required between each end of the crystal and ground to provide the necessary additional phase shift. The addition of a 220Ω resistor between OSC OUT and the crystal will improve stability. An external reference signal may, alternatively, be applied to OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled. The program range of the reference counter is 3 to 2047 , with the total division ratio being twice the programmed number. 9 – NC 10 12 DATA Information on this input is transferred to the internal data latches during the appropriate data read time slot. DATA is high for a ‘1’ and low for a ‘0’. There are three data words which control the NJ88C24; MSB is first in the order: ‘A’ (7 bits), ‘M’ (10 bits), ‘R’ (11 bits). 11 13 CLOCK Data is clocked on the negative transition of the CLOCK waveform. If less than 28 negative clock transitions have been received when the ENABLE line goes low (i.e., only ‘M’ and ‘A’ will have been clocked in), then the ‘R’ counter latch will remain unchanged and only ‘M’ and ‘A’ will be transferred from the input shift register to the counter latches. This will protect the ‘R’ counter from being corrupted by any glitches on the clock line after only ‘M’ and ‘A’ have been loaded If 28 negative transitions have been counted, then the ‘R’ counter will be loaded with the new data. 12 14 ENABLE When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is transferred from the input shift register to the counter latches on the negative transition of the ENABLE input and both inputs to the phase detector are synchronised to each other. 13 15 CAP This pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and allows further programming of the device. (This capacitor is connected from CAP to VSS). 14 16 MC Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset. This gives a total division ratio of MP1A, where P and P11 represent the dual-modulus prescaler values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a division ratio up to and including 4128/129. The programming range of the ‘M’ counter is 8-1023 and, for correct operation, M>A. Where every possible channel is required, the minimum total division ratio N should be: N>P 22P, where N = MP1A. 15 17 RB An external sample and hold phase comparator gain programming resistor should be connected between this pin and VSS. 16 18 CH An external hold capacitor should be connected between this pin and VSS. Not connected. 3 NJ88C24 8 2·0 VDD = 5V FIN = LOW FREQUENCY 0V TO 5V SQUARE WAVE 7 1·5 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) VDD = 5V OSC IN, FIN = 0V TO 5V SQUARE WAVE OSC IN 1·0 FIN 6 5 4 3 10MHz 2 0·5 TOTAL SUPPLY CURRENT IS THE SUM OF THAT DUE TO FIN AND OSC IN 1 2 3 4 5 6 7 INPUT FREQUENCY (MHz) 8 1MHz 1 9 0·2 10 Fig. 3 Typical supply current v. input frequency 0·4 0·6 0·8 1·0 1·2 INPUT LEVEL (V RMS) 1·4 1·6 Fig. 4 Typical supply current v. input level, OSC IN PROGRAMMING Reference Divider Chain The comparison frequency depends upon the crystal oscillator frequency and the division ratio of th ‘R’ counter, which can be programmed in the range 3 to 2047, and a fixed divide by two stage. fosc R= 23fcomp where fosc = oscillator frequency, fcomp = comparison frequency, R = ‘R’ counter ratio For example, where the crystal frequency = 10MHz and a channel spacing comparison frequency of 12·5kHz is required, R= 107 = 400 2312·53103 Thus, the ‘R’ register would be programmed to 400 expressed in binary. The total division ratio would then be 23400 = 800 since the total division ratio of the ‘R’ counter plus the 42 stage is from 6 to 4094 in steps of 2. VCO Divider Chain The synthesised frequency of the voltage controlled oscillator (VCO) will depend on the division ratios of the ‘M’ and ‘A’ counters, the ratio of the external two-modulus prescaler (P/P11)and the comparison frequency . The division ratio N = MP1A, where M is the ratio of the ‘M’ counter in the range 8 to 1023 and A is the ratio of the ‘A’ counter in the range 0 to 127. N = fVCO fcomp For example, if the desired VCO frequency = 275MHz, the comparison frequency is 12·5kHz and a two-modulus prescaler of 464/65 is being used, then 6 N = 275310 = 223103 12·53103 Now, N = MP1A, which can be rearranged as N/P = M1A/P. In our example we have P = 64, therefore A 223103 = M1 64 64 such that M = 343 and A /64 = 0·75. Now, M is programmed to the integer part = 343 and A is programmed to the fractional part364 i.e., A = 0·75364 = 48. NB The minimum ratio N that can be used is P 22P (=4032 in our example) for all contiguous channels to be available. To check: N = 343364148 = 22000, which is the required division ratio and is greater than 4032 ( = P 22P ). When re-programming, the counters are changed only at the zero state. There is no reset to zero , which means that the synthesiser loop lock-up time will be variable. When only small changes in frequency are required, the non-resettable synthesiser should achieve the shortest loop lock-up times. tCL tCH CLOCK ENABLE Note that M>A and tEH tES tEH tDS tDH DATA Fig. 5 Timing diagram showing timing periods required for correct operation 4 tES NJ88C24 1 2 3 4 5 (15)26 (16)27 (17)28 CLOCK ENABLE DATA A6 A5 A4 A3 A2 (M2)R2 (M1)R1 (M0)R0 Fig.6 Timing diagram showing programming details PHASE COMPARATORS Noise output from a synthesiser loop is related to loop gain: KPD KVCO N where KPD is the phase detector constant (volts/rad), KVCO is the VCO constant (rad/sec/volt) and N is the overall loop division ratio. When N is large and the loop gain is low, noise may be reduced by employing a phase comparator with a high gain. The sample and hold phase comparator in the NJ88C24 has a high gain and uses a double sampling technique to reduce spurious outputs to a low level. A standard digital phase/frequency detector driving a threestate output,PDB, provides a ‘coarse’ error signal to enable fast switching between channels. The PDB output is active until the phase error is within the sample and hold phase detector window, when PDB becomes high impedance. Phase-lock is indicated at this point by a low level on LD. The sample and hold phase detector provides a ‘fine’ error signal to give further phase adjustment and to hold the loop in lock. An internally generated ramp, controlled by the digital output from both the reference and main divider chains, is sampled at the reference frequency to give the ‘fine’ error signal, PDA. When in phase lock, this output would be typically at (VDD2VSS)/2 and any offset from this would be proportional to phase error. The relationship between this offset and the phase error is the phase comparator gain, KPDA, which is programmable with an external resistor, RB, and a capacitor, CAP. An internal 50pF capacitor is used in the sample and hold comparator. CRYSTAL OSCILLATOR When using the internal oscillator, the stability may be enhanced at high frequencies by the inclusion of a resistor between the OSC OUT pin and the other components. A value of between 150Ω and 270Ω is advised, depending on the crystal series resistance. PROGRAMMING/POWER UP Data and signal input pins should not have input applied to them prior to the application of VDD, as otherwise latch-up may occur. 5 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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