MITSUMI MM1068

MITSUMI
No-adjustment Sync Separator MM1068
No-adjustment Sync Separator
Monolithic IC MM1068
Outline
This IC is a no-adjustment sync IC designed for use in VCR, TV and other video equipment. A ceramic
resonator is used in the oscillation circuit for stable operation.
Features
1. Sync separator with AFC
2. Ceramic resonator means no adjustment required
3. High precision due to use of PLL format
4. Ceramic resonator can be selected for use in either PAL or NTSC
5. Power supply voltage VCC=5V
Package
SIP-10A (MM1068XS)
Applications
1. TV
2. VCR
3. Other video equipment
Block Diagram
No-adjustment Sync Separator MM1068
MITSUMI
Pin Description
Pin no. Pin name
Internal equivalent circuit diagram Pin no. Pin name
1
GND
6
VCC
2
OSC OUT
7
VIDEO IN
3
OSC IN1
8
H.SYNC
4
OSC IN2
9
V.INT
5
LPF
10
V.SYNC
Absolute Maximum Ratings
Internal equivalent circuit diagram
(Ta=25°C)
Item
Symbol
Ratings
Units
Storage temperature
TSTG
-40~+125
°C
Operating temperature
TOPR
-20~+75
°C
Power supply voltage
VCC max.
7
V
Allowable loss
Pd
500
mW
No-adjustment Sync Separator MM1068
MITSUMI
(Except where noted otherwise, Ta=25°C, VCC=5.0V, X=CSB503F2,
R=390 [OHM], C=3300pF, SW1=ON, SW2=OFF)
Electrical Characteristics
Measurement
Item
Symbol
Operating power supply voltage
VCC
VCC
Consumption current
Id
Id
Free-running frequency NTSC
fO1
TP1
fCAP1
TP1
fO2
TP1
fCAP2
TP1
LPF pin DC level
VLPF
TP4
Sync separation level
VSEPA
VIN
SW1 : OFF, VIN : staircase wave 1VP-P
H. sync pulse width
tW1
TP1
VIN : signal 1, 15.734kHz
H. sync delay time
Td 1
TP1
H. sync output voltage L
VL1
TP1
H. sync output voltage H
VH1
TP1
V. sync pulse width
tW3
TP3
V. sync delay time
td3
TP3
V. sync output voltage L
VL3
TP3
V. sync output voltage H
VH3
TP3
V. sync switching voltage L
VTHL3
TP2
V. sync switching voltage H VTHH3
TP2
Horizontal sync signal
acquisition range NTSC
Free-running frequency PAL
Horizontal sync signal
acquisition range PAL
Measurement conditions
circuit
Min. Typ. Max. Units
4.7
5.0
5.3
8.0
11.5 mA
15.534 15.734 15.934 kHz
VIN : signal 1
*1 *2
300
X=CSB500F40, R=200OHM,
500
Hz
15.425 15.625 15.825 kHz
C=4700pF
X=CSB500F40, R=200OHM,
300
500
0.9
1.4
1.9
V
*4
20
50
80
mV
*5
V : signal 1, 15.734kHz
*5
V : signal 1, 15.734kHz
*5
V : signal 1, 15.734kHz
*5
V : staircase wave 1V
*6
V : staircase wave 1V
*6
V : staircase wave 1V
*6
V : staircase wave 1V
*6
TP2 : DC voltage 5V Low
*7
TP2 : DC voltage 0V High
*7
3.9
4.2
4.5
uS
0.7
1.2
1.7
uS
0.2
0.4
V
C=4700pF, VIN : signal 1
*1 *3
SW2 : ON
IN
IN
IN
4.8
5.0
Hz
V
IN
P-P
150
190
230
uS
IN
P-P
8.0
10.0 12.0
uS
IN
P-P
0.2
V
IN
P-P
0.4
4.8
5.0
V
1.5
1.8
2.1
V
2.3
2.6
2.9
V
Notes:
1 Signal 1 : Pulse signal with 0.3V amplitude and pulse width 4.7µS
*
Signal 1 waveform
4.7uS
Measuring horizontal sync signal pull-in range for NTSC
*2 With
TP1 waveform not synchronized to signal 1, adjust signal 1 frequency toward 15.734kHz.
The
measurement value is the smaller of the synchronized frequency and the difference from 15.734.
*3 Measuring horizontal sync signal pull-in range for PAL
With TP1 waveform not synchronized to signal 1, adjust signal 1 frequency toward 15.625kHz. The
measurement value is the smaller of the synchronized frequency and the difference from 15.625.
*4 Measuring sync separation level
V
Gradually lower staircase wave signal sync tip level, and measure sync tip level when Pin 9 waveform
starts to change.
No-adjustment Sync Separator MM1068
MITSUMI
*5 H. SYNC measurement
Signal 1
tw1
V H1
TP1 waveform
VL1
td1
*6 V. SYNC measurement
Input video signal
(Horizontal sync signal portion)
VH3
tw3
TP3 waveform
VL3
td3
*7 V. SYNC switching voltage measurement
Gradually change the DC voltage impressed on TP2, and measure TP2 voltage when TP3 output switches.
Measuring Circuit
Note : 1
*
NTSC
PAL
X
CSB503F2
CSB500F40
R
390Ω
220Ω
C
3300pF
4700pF
No-adjustment Sync Separator MM1068
MITSUMI
Application Circuits
There is a momentary phase lag in the H. SYNC output vertical feedback interval. When using this IC for OSD
timing, characters at the top of the screen may bend due to IC deviation. If this happens, change the
resistance between Pins 13 and 14 as shown, and the bending will improve by several H from the top edge of
the screen.
Application Circuit 1
Application Circuit 2
*
Note 1 : 1. 1
NTSC
PAL
X
CSB503F2
CSB500F40
R1
1.5kΩ
1.8kΩ
R2
390Ω
C1
220pF
C2
3300pF
2. Resistors R1 and R2 should have precision of ±1%.
3. Capacitors C1 and C2 should have precision of
±5% and temperature characteristic of CH class.
Note 2 :
1. 2 Input signal sync tip must be less than
1V for application circuit 1 Pin 7
external circuit.
2. The above 1. does not apply for
application circuit 2 Pin 7 external circuit.
Pin 1 is clamped at approximately 2.5V.
*