DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT µPC1862 BURST LOCK CLOCK GENERATOR The µPC1862 is an LSI incorporating a PLL circuit to generate nfSC clocks (fSC: color subcarrier frequency), ideal for the processing of digital video signals as in extended definition television (EDTV) systems. FEATURES • VCO is incorporated. • Horizontal and vertical sync separation circuits are incorporated (with output pins). • Horizontal and vertical sync output pulses (TTL level) • ACC amplifier and killer detector circuits are incorporated. • 1/4 and 1/8 (1/2 × 1/4) frequency dividers are incorporated. • fSC phase control circuits is incorporated. • Applicable to both NTSC and PAL systems. • Possible to input burst gate pulse from external ORDERING INFORMATION Part number Package µPC1862GS 36-pin plastic shrink SOP (300 mil) The information in this document is subject to change without notice. Document No. S11431EJ3V0DS00 (3rd edition) Date Published December 1997 N CP(K) Printed in Japan The mark shows major revised points. © 1991, 1996 µPC1862 BLOCK DIAGRAM SSI VSSI CSO 36 35 H sync SEP HDO HDF 34 SGND HSOF2 AFCF BGPE CPO VSO HSOF1 HSOF3 SVCC NHSO FIO N/P HKO 33 32 31 30 29 H DET V sync SEP 28 27 26 32fH VCO 25 24 23 22 21 20 19 15 16 17 18 AFC H count down LPF ACC DET Phase shift ACC AMP 1 2 SCO 3 4 TINT CVCC1 Color Killer DET 5 6 ACCF CIN f 2 V count down 7 CKF CKO APC 8 9 f 4 nfSC VCO 10 11 12 13 14 APCF SCOF1 SCOF3 CVCC3 DIVS COUT CGND SCOF2 CVCC2 VCOO ESCI Remark AFC : Automatic Frequency Control ACC : Automatic Color saturation level Control APC : Automatic Phase Control Selecting divide ratio by DIVS pin DIVS Divide ratio N/P pin TV transmission H 1/8 H PAL Open EXT IN with pin 18 L NTSC L 1/4 In PAL, only correspond 4fSC (DIVS = L). 2 Selecting TV transmission by N/P pin µPC1862 System Block Diagram Application to Process of Digital Video Signal Gate array, etc Analog video input A/D converter µPC659A Processing of digital video D/A converter µPC665 (1ch.) µPC664 (2ch.) µPC662 (3ch.) Analog video output Clock generator µ PC1862 3 µPC1862 PIN CONFIGURATION (Top View) 36-pin plastic shrink SOP (300 mil) 4 SCO 1 36 SSI CVCC1 2 35 CSO TINT 3 34 VSSI CIN 4 33 HDF ACCF 5 32 HDO CKO 6 31 HKO CKF 7 30 SGND COUT 8 29 HSOF1 APCF 9 28 HSOF2 CGND 10 27 HSOF3 SCOF1 11 26 AFCF SCOF2 12 25 SVCC SCOF3 13 24 BGPE CVCC2 14 23 NHSO CVCC3 15 22 CPO VCOO 16 21 FIO DIVS 17 20 VSO ESCI 18 19 N/P µPC1862 ACCF : Chroma ACC Filter AFCF : Horizontal Sync AFC Filter APCF : Chroma APC Filter BGPE : Burst Gate Pulse from External CGND : Chroma GND CIN : Chroma Input CKF : Color Killer Filter CKO : Color Killer Output COUT : Chroma Output CPO : Clamp Pulse Output CSO : Composite Sync Output CVCC1-CVCC3 : Chroma VCC DIVS : Divider Setting Input ESCI : External Subcarrier Input FIO : Field ID Output HDF : Horizontal Sync Detect Filter HDO : Horizontal Sync Detect Output HKO : Horizontal Sync Killer Output HSOF1-HSOF3 : 32fH VCO Filter NHSO : Negative Horizontal Sync Output N/P : NTSC/PAL Mode Select SCO : Subcarrier Output SCOF1-SCOF3 : fSC VCO Filter SGND : Sync GND SSI : Horizontal Sync Separation Input SVCC : Sync VCC TINT : Tint Control VCOO : VCO Output VSO : Vertical Sync Output VSSI : Vertical Sync Separation Input 5 µPC1862 PIN FUNCTIONS (1/12) Pin No. 1 Symbol SCO Pin Name Equivalent Circuit Sub Carrier Output Function CVCC3 (pin 15) Burst locked sub carrier output 5 kΩ 1 400 µ A DC voltage of a standard 2 CVCC1 Chroma VCC1 3 TINT Tint Control 2.9 V Power supply for chroma signal processing circuit (pin 1 to pin 18) This power supply must be isolated from the power supply for sync processing circuit use. CVCC3 (pin 15) Tint control input (DC voltage) This pin adjusts the tint of sub carrier output (SCO pin). 3.3 V 5 kΩ 100 µ A 15 kΩ 3 Internal bias voltage of a standard 6 2.5 V µPC1862 (2/12) Pin No. 4 Symbol CIN Pin Name Equivalent Circuit Chroma Signal Input Function CVCC1 (pin 2) Chroma signal input 5 kΩ 4.0 V 10 kΩ 100 µ A 200 µ A 4 Internal bias voltage of a standard 5 ACCF Chroma ACC Filter 3.2 V CVCC3 (pin 15) 2 kΩ Pin for connecting filter of ACC (Automatic Color Control) detector 200 Ω 2 kΩ 5 DC voltage of a standardNote 6 CKO Color Killer Output CVCC3 (pin 15) 1 kΩ 1.0 V Color Killer Detection output When Killer (without burst) signal: Low level output When color signal: High level output 6 Note Chroma burst amplitude from pin 4: 150 mVp-p 7 µPC1862 (3/12) Pin No. 7 Symbol CKF Pin Name Equivalent Circuit Function CVCC3 (pin 15) Chroma Killer Filter 1 kΩ Pin for connecting filter of Color killter detector 3.6 V 2 kΩ 500 Ω 14 kΩ 1 kΩ 7 DC voltage of a standardNote 8 COUT Chroma Signal Output 2.2 V CVCC3 (pin 15) For APC circuit 5 kΩ 8 400 µ A DC voltage of a standard Note 8 Chroma burst amplitude from pin 4: 150 mVp-p 2.4 V Automatic color controlled chroma output µPC1862 (4/12) Pin No. 9 Symbol APCF Pin Name Equivalent Circuit Function APC Filter 1 kΩ Pin for connecting filter of APC (Automatic Phase Control) detector 12 kΩ 5 kΩ 60 kΩ 65 kΩ 1.8 V 1 kΩ 4.5 kΩ 9 DC voltage of a standardNote 10 CGND Chroma GND 11 SCOF1 nfSC VCO Filter (1) 2.7 V Ground for chroma signal processing circuit (pin 1 to pin 18) CVCC2 (pin 14) Pin for connecting filter of nfSC VCO 500 Ω 11 200 µ A Bias voltage of a standard Note 3.0 V Chroma burst amplitude from pin 4: 150 mVp-p 9 µPC1862 (5/12) Pin No. 12 Symbol SCOF2 Pin Name Equivalent Circuit Function nfSC VCO Filter (2) Pin for connecting filter of nfSC CVCC2 (pin 14) VCO 1 kΩ 3.8 V 20 kΩ 1 kΩ 200 µ A 200 µ A 12 Internal bias voltage of a standard 13 SCOF3 nfSC VCO Filter (3) 3.0 V CVCC2 (pin 14) Pin for connecting filter of nfSC VCO 13 200 µ A 1 mA DC voltage of a standard 2.9 V 14 CVCC2 Chroma VCC 2 Power supply for chroma signal processing circuit (pin 1 to pin 18) This power supply must be isolated from the power supply for sync processing circuit use. 15 CVCC3 Chroma VCC 3 Power supply for chroma signal processing circuit (pin 1 to pin 18) This power supply must be isolated from the power supply for sync processing circuit use. 10 µPC1862 (6/12) Pin No. 16 Symbol VCOO Pin Name Equivalent Circuit Function CVCC2 (pin 14) VCO Output Burst locked VCO output 5 kΩ 16 400 µ A DC voltage of a standard 17 DIVS Dividing ratio selection 100 µ A 100 µ A 2.8 V Divider ratio selection input CVCC3 (pin 15) When 1/4: Low level input 25 kΩ 10 kΩ When 1/8: High level input When external dividing: Middle level input 25 kΩ 16 kΩ 16 kΩ 16 kΩ 16 kΩ 17 18 ESCI External subcarrier Input (External Divide) 100 µ A CVCC3 (pin 15) 25 kΩ External subcarrier input. When no use (pin 17 is not middle level): Low level input 2.5 V 5 kΩ 18 22 kΩ 11 µPC1862 (7/12) Pin No. 19 Symbol N/P Pin Name Equivalent Circuit Function CVCC3 (pin 15) NTSC/PAL selection 100 µ A 5 kΩ NTSC/PAL system selection input When NTSC system: Low level input When PAL system: High level input 2.0 V 19 16 kΩ 20 VSO Vertical Sync Output SVCC (pin 25) 1 kΩ Negative polarity vertical sync output 40 kΩ 20 21 FIO SVCC (pin 25) Field ID Output 1 kΩ 40 kΩ Odd/Even field ID output When Odd ID: Low level output When Even ID: High level output When a input is non-standard signal, this pin outputs an indefiniteness. 21 22 CPO SVCC (pin 25) Clamp Pulse Output 1 kΩ 40 kΩ 22 12 Pedestal Clamp pulse (burst gate pulse) output µPC1862 (8/12) Pin No. 23 Symbol NHSO Pin Name Equivalent Circuit Negative Horizontal Sync Output Function SVCC (pin 25) 1 kΩ Negative polarity horizontal sync output 40 kΩ 23 24 BGPE SVCC (pin 25) Burst Gate Pulse from External 24 2.5 kΩ 5 kΩ 8 kΩ 5 kΩ 7 kΩ BGP 25 SVCC Sync VCC Burst gate pulse input In inside burst gate pulse generation mode: Low level fix In external burst gate pulse input mode: When Non-burst period: Middle level input When burst period: High level input Power supply for sync signal processing circuit (pin 19 to pin 36) This power supply must be isolated from the power supply for chroma processing circuit use. 13 µPC1862 (9/12) Pin No. 26 Symbol AFCF Pin Name Equivalent Circuit AFC Filter 200 Ω Function SVCC (pin 25) 3.2 V Pin for connecting filter of horizontal AFC (Automatic Frequency Control) detector 3 kΩ 300 Ω 30 kΩ 100 µ A 1 kΩ 26 DC voltage of a standardNote 27 HSOF3 3.2 V 32fH VCO Filter (3) Pin for connecting filter of 32fH VCO SVCC (pin 25) 27 1 mA DC voltage of a standard 28 HSOF2 2.4V 32fH VCO Filter (2) Pin for connecting filter of 32fH VCO SVCC (pin 25) 4.6 V 3.3 kΩ 100 µ A 28 Internal bias voltage of a standard Note 14 When only 0.3 Vp-p sync signal is input to pin 36 3.8 V µPC1862 (10/12) Pin No. 29 Symbol HSOF1 Pin Name Equivalent Circuit Function 32fH VCO Filter (1) Pin for connecting filter of 32fH VCO 29 Bias voltage of a standard 3.8 V 30 SGND Sync GND Ground for sync processing circuit (pin 19 to pin 36) 31 HKO Horizontal Killer Output Horizontal killer output (Open Corrector) When No sync: High impedance output When sync: Low level output 31 24 kΩ 32 HDO Horizontal Sync Detection Output SVCC (pin 25) Horizontal sync detection signal output When No sync: High level output When sync: Low level output 1 kΩ 32 15 µPC1862 (11/12) Pin No. 33 Symbol HDF Pin Name Equivalent Circuit Horizontal Sync Detection Filter Function SVCC (pin 25) Pin for connecting filter of Horizontal sync detector 1 kΩ 10 kΩ H gate pulse 33 Bias voltage of a standardNote 34 VSSI Vertical Sync Separator Input 16 kΩ 4.1 V Vertical sync separation input pin SVCC (pin 25) 5 kΩ 20 kΩ 100 Ω 1 kΩ 30 kΩ 34 35 CSO Composite Sync Separator Output SVCC (pin 25) 1 kΩ 35 Note 16 When only 0.3 Vp-p sync signal is input to pin 36 Negative polarity composite sync output µPC1862 (12/12) Pin No. 36 Symbol SSI Pin Name Equivalent Circuit Horizontal Sync Separator Input SVCC (pin 25) 5 kΩ Function Horizontal sync separation input pin 16 kΩ 20 kΩ 100 Ω 1 kΩ 30 kΩ 36 17 µPC1862 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise specified) Parameter Symbol Ratings Unit Supply voltage VCC 7 V Input signal voltage (Chroma signal) ei4 3 Vp-p Input signal voltage (H sync separation) ei36 3 Vp-p Input signal voltage (V sync separation) ei34 3 Vp-p Input signal voltage (EXT) ei18 VCC Vp-p Tint control signal voltage ec3 VCC V Output current IO –7 mA Permissible package power dissipation (when mounted on PCB) PD 570 (TA = 75°C) mW Operating ambient temperature TA –10 to +75 °C Storage temperature Tstg –40 to +125 °C Caution Expose to Absolute Maximum Rating for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. RECOMMENDED OPERATING CONDITIONS Parameter Symbol MIN. TYP. MAX. Unit Supply voltage VCC 4.5 5.0 5.5 V Input signal voltage (Chroma signal) ei4 150 mVp-p Input signal voltage (H sync separation) ei36 1.0 Vp-p Input signal voltage (V sync separation) ei34 1.0 Vp-p Input signal voltage (EXT IN HIGH voltage) eiH18 Input signal voltage (EXT IN LOW voltage) eiL18 Divider selector voltage 1 (1/8) V17 (8) Divider selector voltage 2 (1/4) V17 (4) Tint control voltage V19P NTSC/PAL select voltage (NTSC) V19N V 0.8 4.8 V V 0.2 V3 NTSC/PAL select voltage (PAL) 18 2.0 2.5 V V 4.5 V 0.5 V µPC1862 ELECTRICAL CHARACTERISTICS (at TA = 25±3 °C, RH ≤ 70 %, VCC = 5 V, unless otherwise specified) Chroma section Parameter Symbol Condition MIN. TYP. MAX. Unit 17 21 25 mA Supply current of chroma section ICC (C) VCC (C) = 5 V No current on pin 2, 14 and 15 ACC amplitude characteristic 1 ACC1 Fluctuation of chroma output level at +6 dB change of chroma input burst signal (0 dB = 150 mVp-p) –2.0 0 +2.0 dB ACC amplitude characteristic 2 ACC2 Fluctuation of chroma output level at –20 dB change of chroma input burst signal (0 dB = 150 mVp-p) –5.0 –1.0 +1.0 dB Color killer set point eKS Input level at killer ON with chroma input burst sig. (0 dB = 150 mVp-p) being attenuated –45 –39 –33 dB Color residual of color killer eKR Residual level of chroma output in Killer ON state when chroma input burst signal of 150 mVp-p is input - - 15 mVp-p Chroma output level ECOUT Chroma output level when chroma input burst signal of 150 mVp-p is input 1.1 1.3 1.5 Vp-p Color killer output ECKOH (1) High level of color killer output at color killer OFF IOH = –400 µA 2.7 3.5 - V Color killer output High level (2) ECKOH (2) High level of color killer output at color killer OFF IOH = –20 µA 3.5 4.0 - V Color killer output Low level ECKOL Low level of color killer output at color killer ON IOL = +2 mA - 0.2 0.4 V APC lock-in range fP Frequency pulled by APC with chroma input burst frequency changed (fSC conversion) ±400 ±600 - Hz VCO control sensitivity βP Rate of variation of frequency when APC filter pin is changed from –0.025 V to +0.025 V (fSC conversion) 8.0 10.0 12.0 Hz/mV Phase variable range θCONT Amount of phase shift when voltage of phase control pin is set at 2.5 V + 1 V ±40 ±55 - deg VCO output level eVCOO VCO output level when chroma input burst signal of 150 mVp-p is input 1.0 1.3 1.6 Vp-p fSC output level eSCO fSCO output level when chroma input burst signal of 150 mVp-p is input 210 300 390 mVp-p Divider select voltage VDIVSL 1/4 freq. division if VDIVS < VDIVSL - - 0.5 V 4.5 - - V 1.7 2.0 2.3 V High level (1) EXT IN with VDIVS : OPEN VDIVSH NTSC/PAL select voltage VN/PT 1/8 freq. division if VDIVSH < VDIVS fV = 60 Hz if VN/P < VN/PT fV = 50 Hz if VN/PT < VN/P 19 µPC1862 Sync section Parameter Symbol Condition MIN. TYP. MAX. Unit Supply current of Sync section ICC (1) VCC (1) = 5 V No current on pin 25 12 15 18 mA DC level of H sync separation input VSSI Voltage of pin 36 when connected to GND via 10 kΩ resistor 1.9 2.2 2.5 V DC level of V sync separation input VVSSI Voltage of pin 34 when connected to GND via 10 kΩ resistor 1.9 2.2 2.5 V Sync separation output High level (1) ECSOH1 High level of sync separation output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –400 µA 2.7 3.8 - V Sync separation output High level (2) ECSOH2 High level of sync separation output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –20 µA 3.5 4.3 - V Sync separation output Low level ECSOL Low level of sync separation output when only 0.3 Vp-p sync signal is input to pin 36 IOL = +2 mA - 0.1 0.4 V HD output ENHSOH1 High level of synchronized HD output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –400 µA 2.7 3.8 - V HD output High level (2) ENHSOH2 High level of synchronized HD output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –20 µA 3.5 4.3 - V HD output Low level ENHSOL High level of synchronized HD output when only 0.3 Vp-p sync signal is input to pin 36 IOL = +2 mA - 0.1 0.4 V VD output EVSOH1 High level of synchronized VD output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –400 µA 2.7 3.8 - V VD output High level (2) EVSOH2 High level of synchronized VD output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –20µA 3.5 4.3 - V VD output Low level EVSOL High level of synchronized VD output when only 0.3 Vp-p sync signal is input to pin 36 IOL = +2 mA - 0.1 0.4 V Clamp output High level (1) ECPOH1 High level of synchronized Clamp output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –400 µA 2.7 3.8 - V Clamp output High level (2) ECPOH2 High level of synchronized Clamp output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –20 µA 3.5 4.3 - V Clamp output Low level ECPOL High level of synchronized Clamp output when only 0.3 Vp-p sync signal is input to pin 36 IOL= +2 mA - 0.1 0.4 V High level (1) High level (1) 20 µPC1862 Parameter Symbol Condition MIN. TYP. MAX. Unit Field ident. output High level (1) EFIOH1 High level of synchronized Field ident. output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –400 µA 2.7 3.8 - V Field ident. output High level (2) EFIOH2 High level of synchronized Field ident. output when only 0.3 Vp-p sync signal is input to pin 36 IOH = –20 µA 3.5 4.3 - V Field idnet. output Low level EFIOL High level of synchronized Field ident. output when only 0.3 Vp-p sync signal is input to pin 36 IOL = +2 mA - 0.1 0.4 V H detection output High level (1) EFIOH1 High level of asynchronized H detect output without H sync input IOH = –400 µA 2.7 3.8 - V H detection output High level (2) EFIOH2 High level of asynchronized H detect output without H sync input IOH = –20 µA 3.5 4.3 - V H detection output Low level EFIOL High level of synchronized H detect output when only 0.3 Vp-p sync signal is input to pin 36 IOL= +2 mA - 0.1 0.4 V H sync lock-in range fHP Frequency range that can be pulled when only 0.3 Vp-p sync signal is input to pin 36 and H sync frequency is varied (fSC conversion) ±400 ±500 - Hz Horizontal VCO control βH Rate of variation of frequency when APC filter pin is changed form 3.0 V to 3.4 V without H sync input (fSC conversion) –1.6 –1.3 –0.9 Hz/mV Horizontal VCO free-run frequency fHO Frequency difference of HD output from fH when H sync input is not applied –100 –25 +50 Hz Pulse width of HD output PWNHSO Pulse width of synchronized HD output when only 0.3 Vp-p sync signal is input to pin 36 3.8 4.0 4.2 µs Pulse width of VD output PWVSO1 Pulse width of synchronized VD output when only 0.3 Vp-p sync signal is input to pin 36 ODD - 6.0 - HNote EVEN - 5.5 - HNote 3.4 3.6 3.8 µs sensitivity PWVSO2 Pulse width of Clamp output PWCPO Pulse width of synchronized Clamp output when only 0.3 Vp-p sync signal is input to pin 36 Oscillation start voltage of horizontal VCO VST Output voltage at HD when VCC is gradually increased from 0 V without H sync input - - 4.2 V H killer output Low level EHKOL Low level of synchronized H killer output when only 0.3 Vp-p sync signal is input to pin 36 Change value of Chroma output - - 0.4 V Burst gate input Threshold level 1 VBGPE1 Burst gate pulse input voltage when Clamp voltage begins Low level is gradually increased from 0 V without signal input 1.6 1.9 2.0 V Note H: Horizontal scanning period 21 µPC1862 Parameter Symbol Condition MIN. TYP. MAX. Unit Burst gate input Threshold level 2 VBGPE2 Burst gate pulse input voltage when Clamp voltage begins High level is gradually increased from VBGPE1 without signal input 3.8 4.0 4.2 V Vertical free-running frequency 1 fV1 (50) Frequency ratio of HD output to VD output H sync input: No signal Pin 33 input: VCC V sync input: VCC - fH/352 - Hz - fH/288 - Hz fV1 (60) Vertical free-running fV2 (50) Same as fV1 with the following exception - fH/288 - Hz frequency 2 fV2 (60) V sync input: GND - fH/240 - Hz Vertical free-running fV3 (50) Same as fV1 with the following exception - fH/368 - Hz frequency 3 fV3 (60) Pin 33 input: GND - fH/296 - Hz Vertical free-running frequency 4 fV4 (50) Same as fV1 with the following exception Pin 33 input: GND V sync input: GND - fH/272 - Hz - fH/232 - Hz 22 fV4 (60) µPC1862 TIMING CHARTS (Horizontal Period) 1 µs Burst Signal Comp Video Input Comp Sync Output (CSO) This delay is fixed by the application of pin 36. HD Output (NHSO) 4 µs 4 µs CLAMP Output (CPO) This rising edge is cut by Comp Sync Output. 23 24 TIMING CHARTS (Vertical Period) <Odd Field> Comp Video Input HD Output (NHSO) CLAMP Output (CPO) VD Output (VSO) 6 HNote 0.5 HNote FIELD Output (FIO) <Even Field> Comp Video Input HD Output (NHSO) CLAMP Output (CPO) VD Output (VSO) 5.5 HNote 0.5 HNote FIELD Output (FIO) H: Horizontal scanning period µPC1862 Note µPC1862 CAUTION AT DESIGNING Resonators NEC evaluates µPC1862 using resonators which are shown below in design and development process. If the different product is used as a resonator, electrical specification value described in this document is not assured. And when connecting resonator to external circuit, there is need to consider temperature specification, voltage fluctuation and product variation. In this case, normal operation is not assured in the application circuit including the different product. Use the resonators which are shown below when you design circuit. 32 fH VCO resonator X1 X1 (PAL) : in application example circuit : CSB500F2 (MURATA) (NTSC) : CSB503F2 (MURATA) nfSC VCO resonator X2 X2 : HC-49/U (KINSEKI, µPC1860 adoption) Reference data of 4fSC, 8fSC VCO resonator (KINSEKI) Item NTSC for 4fSC Name Frequency Overtone Order NTSC for 8fSC PAL for 4fSC HC-49/U 14.31818 MHz 28.63636 MHz 17.34475 MHz Fundamental (AT cut) Fundamental (BT cut) Fundamental (AT cut) Operating Temperature –10 to +70°C Frequency Permitted Tolerance (25±5°C) ±30 × 10–6 ±50 × 10–6 ±30 × 10–6 Frequency Temperature ±30 × 10–6 ±100 × 10–6 ±30 × 10–6 Specification (to 25°C) 50 Ω or less Equivalent Serial Resistance Parallel Capacitance 3rd harmonic standard 7.0 pF or less 3rd harmonic frequency is over 3fO (42.95454 MHz) + 7.5 kHz – 3rd harmonic frequency is over 3fO (53.203425 MHz) + 7.5 kHz 25 µPC1862 Recommended pattern The µ PC1862 generates system clock for synchronous signal processing and clock generate processing. If the supply voltage, line placement and routing are not set appropriately that the µPC1862 cannot generate correct system clock. Though the recommended pattern is not shows in this document, note points shown below at designing. 26 1. For synchronous section and chroma section, each power supply must be isolated. 2. Lines to pin 9 to pin 13 should be as thick and short as possible. 3. Connect resonator as near IC as possible. Don’t put GND line between resonator pins for parasitism capacitance. APPLICATION CIRCUIT 5V X1:CSB503F2(Murata) 1 kΩ Comp video IN 39 kΩ 10 µ F + 75 Ω Burst gate input ‘H’: In the period of burst ‘M’: Out the period of burst ‘L’: Internal Comp sync OUT 2SA1175 4.7 µ F or equivalent 100 kΩ 11 kΩ 4.7 µF 100 kΩ + 220 Ω + 220 Ω 1000 pF 36 35 H DET OUT 1500 pF 270 Ω X1 220 pF 0.01 µF 1.5 kΩ 2.2 kΩ 8.2 2.7 kΩ kΩ 4.7 µF 5V VD NTSC/PAL + 100 kΩ 34 33 32 31 30 29 28 27 26 25 SGND 24 23 22 21 20 19 14 15 16 17 18 SVCC 32fH VCO H DET V sync SEP H sync SEP HD Clamp output Field ID output 0.015 µ F AFC H count down LPF ACC DET Phase shift ACC AMP f 4 f 2 V count down BPF 47 pF Color killer DET 68 pF 15 µH CGND 1 0.01 µ F 2 3 5V 0.01 µ F 680 Ω + 7 6 0.47 µF 0.01 µF 8 + 1 MΩ 5V 0.1 µF 9 11 12 510 Ω 4.7 kΩ + 4.7 Chroma µ F OUT 10 13 68 pF 100 Ω 5V X2 0.022 µ F C2 C1 X2:HC-49/U(KINSEKI) External subcarrier input 2.2 kΩ VCO OUT ‘H’ …1/8 ‘M’ …EXT ‘L’ …1/4 27 X2 8 fSC 4 fSC NTSC C1 18 pF No connect (N/P =‘L’) C2 22 pF 10 pF PAL C1 12 pF – (N/P =‘H’) C2 18 pF – Cannot correspond 8fSC of PAL. Divider ratio select input µPC1862 2SC2785 or equivalent Tint cont. 5 Color killer OUT 5V Chroma IN 10 kΩ fSC OUT 4 0.1 µF 2.2 kΩ 680 Ω 10 kΩ nfSC VCO APC µPC1862 Care Point for Planning of Application Circuit Processing of VCC pin 1. Please isolate Chroma. VCC from Sync. VCC as follows. If you have external processing block of digital signal, don’t directly supply of the block’s VDD. 5V 0.01 µF 47 µF 30 25 SVCC SGND Sync (Pin 19 to pin 36) µPC1862 Chroma (Pin 1 to pin 18) VDD Processing IC of digital signal, etc CVCC1 2 GND 0.01 µF 2. CGND 10 47 µF CVCC2 14 CVCC3 15 0.01 µF Application of no using Chroma pin If you don’t use Chroma pin but use Sync pin on µPC1862, you process pin 1 to pin 18 as follows. µ PC1862 5V 0.01 µF SCO CVCC1 TINT 1 2 3 CIN ACCF CKO CKF COUT APCF CGND SCOF1 SCOF2 SCOF3 CVCC2 CVCC3 VCOO DIVS ESCI 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 47 µ F 0.01 µF 3. Application of no using Sync pin If you don’t use Sync pin but use Chroma pin on µPC1862, you process pin 19 to pin 36 as follows. In this case, you need to input a pin 24 with burst gate pulse from external. In this application, you can’t use output of pin 20 to pin 23. Video signal input Comp Sync Output 5V 5V 0V 3.3 kΩ Open 36 SSI 35 34 33 32 31 30 2.2 kΩ 29 28 27 3.3 kΩ 25 24 23 22 CSO VSSI HDF HDO HKO SGND HSOF1 HSOF2 HSOF3 AFCF SVCC BGPE NHSO CPO µ PC1862 28 26 Burst Gate Input Open (Don’t use) 21 20 19 FIO VSO N/P µPC1862 PACKAGE DRAWING 36 PIN PLASTIC SHRINK SOP (300 mil) 19 1 detail of lead end 5°±5° 36 18 A H J E K F G I C D L B N M M P36GM-80-300B-3 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 15.54 MAX. 0.612 MAX. B 0.97 MAX. 0.039 MAX. C 0.8 (T.P.) 0.031 (T.P.) D +0.10 0.35 –0.05 0.014+0.004 –0.003 E 0.125 ± 0.075 0.005 ± 0.003 F 1.8 MAX. 0.071 MAX. G 1.55 0.061 H 7.7 ± 0.3 0.303 ± 0.012 I 5.6 0.220 J 1.1 0.043 K 0.20 +0.10 –0.05 0.008+0.004 –0.002 L 0.6 ± 0.2 0.024 –0.009 M 0.10 0.004 N 0.10 0.004 +0.008 29 µPC1862 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Surface Mount Device µPC1862GS: 36-pin plastic shrink SOP (300 mil) Process Conditions Symbol Infrared ray reflow Peak temperature: 235 °C or below (Package surface temperature), Reflow time: 30 seconds or less (at 210 °C or higher), Maximum number of reflow processes: 2 times. IR35-00-2 VPS Peak temperature: 215 °C or below (Package surface temperature), Reflow time: 40 seconds or less (at 200 °C or higher), VP15-00-2 Maximum number of reflow processes: 2 times. Wave Soldering Solder temperature: 260 °C or below, Flow time: 10 seconds or less, Maximum number of flow process: 1 time, Pre-heating temperature: 120 °C or below (Package surface temperature). Partial heating method Pin temperature: 300 °C or below, Heat time: 3 seconds or less (Per each side of the device). WS60-00-1 – Caution Apply only one kind of soldering condition to a device, except for “Partial heating method”, or the device will be damaged by heat stress. 30 µPC1862 [MEMO] 31 µPC1862 [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5