System Reset (with built-in watchdog timer) MM1096 MITSUMI Electrical Characteristics (DC) Item Consumption current MM1096A MM1096B MM1096A Detection voltage MM1096B MM1096A MM1096B Detection voltage temperature coefficient Hysteresis voltage MM1096A MM1096B CK input threshold CK input current Output voltage MM1096A (High) MM1096B Output voltage (Low) R output sync current CT charge current Minimum operating power --------------------------------------------------- supply voltage to ensure RESET (Except where noted otherwise, MM1096A : VCC=3.6V, Ta=25°C, MM1096B : VCC=5.0V) Symbol Measurement conditions ICC During watchdog timer operation VSL VSH Min. Typ. Max. Units 195 3.15 3.25 3.35 VS=OPEN, VCC µA V 4.15 4.30 4.45 %/°C ±0.01 25 50 100 50 100 150 0.8 1.2 2 0 1 -12 -6 -2 I RESET =1µA 3.0 3.4 VS=OPEN 4.0 4.5 VSH-VSL, VCC IIH A : VCK=3.6V, B : VCK=5.0V IIL VCK=0V ---------------------------------------------------- VOL1 130 4.05 4.20 4.35 VTH VOH 150 3.10 3.20 3.30 VS=OPEN, VCC VS/ T VHYS 100 0.2 0.4 ---------------------------------------------------- 0.3 0.5 VOL2 I RESET =1.0mA, VS=0V IOL V RESET =1.0V, VS=0V ---------------------------------------------------- 1 V µA V ---------------------------------------------------- I RESET =0.5mA, VS=0V mV 2 V mA ICT1 VTC=1.0V during watchdog timer operation -0.28 -0.48 -0.96 µA ICT2 VTC=1.0V during power ON reset operation -1.60 -2.40 -4.80 µA ---------------------------------------------------- VCCL V RESET =0.4V ---------------------------------------------------- I RESET =0.1mA 0.8 1.0 V System Reset (with built-in watchdog timer) MM1096 MITSUMI Electrical Characteristics (DC) Item VCC input pulse width Symbol MM1096A Measurement conditions VCC TPI MM1096B VCC CK input pulse width TCKW CK input cycle TCK Watchdog timer monitoring time 1 (Except where noted otherwise, MM1096A : VCC=3.6V, Ta=25°C, MM1096B : VCC=5.0V) (Except where noted otherwise, resistance unit is Ω) 3.6V Min. Typ. Max. Units 8 2.8V µs 5.0V 8 4.0V CK or 3 µs 20 µs TWD CT=0.02µF 25 50 75 ms TWR CT=0.02µF 1 2 3 ms 5 10 15 ms 2 10 µs 2.0 4.0 µs 0.2 1.0 µs * Reset time for watchdog timer 2 * Reset hold time for TPR power supply rise 3 * Output delay time from VCC 4 * Output rise time 5 * Output fall time 5 * TPD tR tF CT=0.02µF, VCC -------------------------------------------------------------------------- RESET pin, RL=10k, CL=20pF -------------------------------------------------------------------------- RESET pin, RL=10k, CL=20pF -------------------------------------------------------------------------- RESET pin, RL=10k, CL=20pF Notes: 1 Monitoring time is the time from the last pulse (negative edge) of the timer clear clock pulse until reset pulse output. In other words, reset output is output if a clock pulse is not input during this time. 2 Reset time means reset pulse width. However, this does not apply to power ON reset. 3 Reset hold time is the time from when VCC exceeds detection voltage (VSH) during power ON reset until reset release (RESET output high). 4 Output delay time is the time from when power supply voltage drops below detection voltage (VSL) until reset (RESET output low). 5 Voltage range when measuring output rise and fall is 10~90%. 6 Watchdog timer monitoring time (TWD), watchdog timer reset time (TWR) and reset hold time (TPR) during power supply rise can be changed by varying CT capacitance. The times are expressed by the following formulae. * * * * ----------------------------------------------- ----------------------------------------------- * * . TPR (ms) =. 500 CT (µF) . TWD (ms) =. 2500 CT (µF) . TWR (ms) =. 100 CT (µF) Example : When CT=0.02µF . TPR =. 10ms TWD .=. 50ms TWR .=. 2ms System Reset (with built-in watchdog timer) MM1096 MITSUMI Measuring Circuits Measuring Circuit 1 (DC) Measuring Circuit 1 Item Consumption current Detection voltage CK input threshold CK input current Output voltage (High) Measuring Circuit 2 (AC) SW & Power Supply Table ----------------------------------------------- Symbol SW1 SW2 SW3 SW4 SW5 SW6 VCC VCK VCT I RESET ICC OFF OFF OFF ON ON A 3.6V 3.6V 0V VM, IM ICC VSL OFF OFF ON ON ON A 3.6V 3V 0V 2V VO1, CRT1 VSH OFF OFF ON ON ON A 3V 3.6V 0V 2V VO1, CRT1 VTH OFF OFF OFF ON ON A 3.6V 0V 3V 1V ICK, VCK IIH OFF OFF OFF ON ON A 3.6V 3.6V 0V ICK IIL OFF OFF OFF ON ON A 3.6V 0V 0V VOH ON OFF ON ON ON A 3.6V 3.6V 2V -1µA V O1 ICK VOL1 ON ON ON ON ON A 3.6V 3.6V 2V 0.5mA V O1 VOL2 ON ON ON ON ON A 3.6V 3.6V 2V 1.0mA V O1 Output sink current IOL1 OFF ON ON ON ON B 3.6V 3.6V 2V IO1 CT charge current 1 ITC1 OFF OFF OFF ON OFF A 3.6V 1V ITC CT charge current 2 ITC2 OFF OFF OFF ON OFF A 3.6V IV ITC VCCL ON OFF ON ON ON A 0V 2V 0V VO1, VCC Output voltage (Low) Minimum operating power ------------------------------------------------------ supply voltage to ensure RESET Measuring Circuit 2 Item 0V Symbol SW1 SW2 VCCA 3.6V T1 VCC VCK T2 1.4V T3 CRT1 CK input pulse width TCKW A B - 3.6V TCK A B - 3.6V TWD A A - 3.6V - 3.6V TWR A A - 3.6V - 3.6V TPR B A A - 3.6V - 3.6V TPD C A - - 0V CRT1 Output rise time TR A A - 3.6V - 3.6V CRT1 Output fall time TF A A - 3.6V - 3.6V CRT1 monitoring time Reset time for watchdog timer Reset hold time for power supply rise Output delay time from VCC 3.6V 0V 0V 1.4V - CRT B 2.8V - VCKA C Watchdog timer VO=1V SW & Power Supply Table VCC input pulse width TP1 CK input cycle Notes T2 or 0V T2 1.4V 0V T2 T3 - CRT2 CRT1 CRT2 CRT1 CRT2 CRT1 CRT2 CRT1 CRT2 CRT1 CRT2 Notes T1=8µs T2=3µs T3=20µs System Reset (with built-in watchdog timer) MM1096 MITSUMI Block Diagram MM1096A MM1096B RA RB ~ - 305k ~ - 350k ~ - 195k ~ - 150k Note 1: CP=0.1µF approx. Note 2: C > = 1000pF Note 3: The watchdog timer can be stopped by connecting the RCT pin to GND. Then it functions as a voltage detection circuit.) Timing Chart VCC VSH VSL 0.8V CK TCK TC TWD TPR RESET 1 2 3 4 5 5 TPR TWR 6 7 8 9 10 11 12 System Reset (with built-in watchdog timer) MM1096 MITSUMI Description of Operation ------------------------------------------------- 1. RESET goes low when VCC rises to approximately 0.8V. Approximately 1µA (VCC=0.8V) of pull up current is output from RESET . . 2. Capacitor CT charging starts when VCC rises to VSH (MM1096A =. 3.25V, MM1096B =. 4.3V). Output is in reset state at this time. 3. Output reset is released (RESET goes high) after a certain time (TPR), from when CT starts charging until discharge (the time from when CT voltage reaches a certain threshold value 1 (.=. 1.4V) until CT voltage . drops to a certain threshold value 2 ( =. 0.2V). Reset hold time : TPR is as follows. TPR (ms) .=. 500 CT (µF) CT charging starts again after reset release, and watchdog timer operation begins. Clock input to the CK pin during CT charging will cause mis-operation. 4. If a clock is input (negative edge trigger) to the CK pin during CT charging, C switches from charging to discharge. 5. Discharge switches to charging when CT voltage drops to a certain threshold value (.=. 0.2V). Steps 4 and 5 are repeated while a normal clock is input from the logic system. 6. Output goes to reset state (RESET goes low) when the clock ceases and CT voltage reaches reset ON threshold value (.=. 1.4V). The formula for CT charging time (TWD : watchdog timer monitoring time) until reset is output is as follows. . TWD (ms) =. 2500 CT (µF) 7. Watchdog timer reset time TWR is the discharge time until CT voltage drops to reset OFF threshold value . ( =. 0.2V). The formula is as follows. TWR (ms) .=. 100 CT (µF) After reset OFF threshold value is reached, output reset is released and CT starts charging. Thereafter, steps 4 and 5 are repeated if a normal clock is input, and when the clock ceases, 6 and 7 are repeated. 8. Reset is output when VCC drops to VSL (MM1096A .=. 3.2V, MM1096B .=. 4.2V). CT is charged simultaneously. 9. CT charging starts when VCC rises to VSH. When VCC drops momentarily, CT charging begins after the charge is first discharged, if the time from VCC dropping below VSL until it rises to VSH is longer than the Vcc input pulse width standard value TPI. 10.Output reset is released after VCC goes above VSH and after TPR, and the watchdog timer starts. Thereafter, 8~10 are repeated when VCC goes below VSL. 11.When power is OFF, reset is output if VCC goes below VSL. 12.When VCC drops to 0V, reset output is held until VCC reaches 0.8V. ------------------------------------------------- ----------------------------------------------- -----------------------------------------------