INTEGRATED CIRCUITS NE56604-42 System reset with built-in Watchdog timer Product data Supersedes data of 2001 Aug 22 2003 Oct 15 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 GENERAL DESCRIPTION The NE56604-42 is designed to generate a reset signal at a threshold voltage of 4.2 V for a variety of microprocessor and logic systems. Accurate reset signals are generated during momentary power interruptions, or whenever power supply voltages sag to intolerable levels. The NE56604-42 has a built-in Watchdog Timer to monitor the microprocessor and ensure it is operating properly. Any abnormal system operations due to microprocessor malfunctions are terminated by a system reset generated by the Watchdog. The NE56604-42 has a Watchdog monitoring time of 100 ms (typical). The NE56604-42 is offered in the SO8 surface mount package (SOP005). FEATURES • Both positive and negative logic reset output signals are available • Accurate threshold detection • Internal power-on reset delay • Internal Watchdog timer programmable with external resistor • Watchdog monitoring time of 100 ms (typical) • Reset assertion with VCC down to 0.8 VDC (typical) • Few external components required. APPLICATIONS • Microcomputer systems • Logic systems. SIMPLIFIED SYSTEM DIAGRAM VCC RCT 6 RCT 5 R VS NE56604-42 LOGIC SYSTEM 8 7 RESET GENERATOR 2 R RESET RESET RESET RESET VREF PROGRAMMABLE WATCHDOG TIMER C 4 GND 3 CLK CLK GND 1 CT SL01281 Figure 1. Simplified system diagram. 2003 Oct 15 2 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 ORDERING INFORMATION PACKAGE TYPE NUMBER NE56604-42D NAME DESCRIPTION SO8 plastic small outline package; 8 leads; body width 3.9 mm Part number marking TEMPERATURE RANGE SOP005 –20 to +70 °C PIN CONFIGURATION TOP VIEW CT 1 8 RESET RESET 2 7 VS CLK 3 6 RCT GND 4 5 VCC SO8 5 6 7 The package is marked with a four letter code in the first line to the right of the logo. The first three letters designate the product. The fourth letter, represented by ‘x’, is a date tracking code. The remaining two or three lines of characters are internal manufacturing codes. 8 VERSION SL01280 4 3 2 1 Figure 2. Pin configuration. Part number Marking NE56604-42 AA D x PIN DESCRIPTION PIN SYMBOL DESCRIPTION 1 CT tWDM, tWDR, tPR adjustment pin. tWDM, tWDR, tPR times are dependent on the value of external CT capacitor used. See Figure 20 (Timing Diagram) for definition of tWDM, tWDR, tPR times. 2 RESET Reset HIGH output pin. 3 CLK Clock input pin from logic system for Watchdog timer. 4 GND Circuit ground. 5 VCC Power supply pin for circuit. 6 RCT Watchdog timer control and program pin. Serves to ENABLE the Watchdog function when connected to pull-up resistor (RCT) to VCC, and DISABLE the Watchdog when connected to ground. Used in conjunction with CT pin to program tWDM time. 7 VS Detection threshold adjustment pin. The detection threshold can be increased by connecting this pin to VCC with a pull-up resistor. The detection threshold can be decreased by connecting this pin to ground with a pull-down resistor. 8 RESET Reset LOW output pin. 2003 Oct 15 3 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 MAXIMUM RATINGS SYMBOL PARAMETER MIN. MAX. UNIT VCC Power supply voltage –0.3 10 V VVS VS pin voltage –0.3 10 V VCLK CLK pin voltage –0.3 10 V VOH RESET and RESET pin voltage –0.3 10 V Toper Operating temperature –20 70 °C Tstg Storage temperature –40 125 °C P Power dissipation – 250 mW DC ELECTRICAL CHARACTERISTICS Characteristics measured with VCC = 5.0 V, and Tamb = 25 °C, unless otherwise specified. See Figure 26 (Test circuit 1) for test configuration used for DC parameters. SYMBOL PARAMETER ICC Supply current during Watchdog timer operation VSL Reset detection threshold VSH CONDITIONS MIN. TYP. MAX. UNIT – 0.7 1.0 mA VS = open; VCC = falling 4.05 4.20 4.35 V VS = open; VCC = rising 4.15 4.30 4.45 V –20 °C ≤ Tamb ≤ 70 °C – ±0.01 – %/°C Vhys = VSH (rising VCC) – VSL (falling VCC) 50 100 150 mV 0.8 1.2 2.0 V ∆VS/∆Tamb Temperature coefficient of reset threshold Vhys Threshold hysteresis VTH CLK input threshold IIH CLK input current, HIGH-level VCLK = 5.0 V – 0 1.0 µA IIL CLK input current, LOW-level VCLK = 0 V –20 –10 –3.0 µA VOH1 Output voltage, HIGH-level IRESET = –5.0 µA; VS = open 4.5 4.8 – V IRESET current = –5.0 mA; VS = 0 V 4.5 4.8 – V VOH2 VOL1 IRESET = 3.0 mA; VS = 0 V – 0.2 0.4 V VOL2 IRESET = 10 mA; VS = 0 V – 0.3 0.5 V VOL3 IRESET = 0.5 mA; VS = open – 0.2 0.4 V VOL4 IRESET = 1.0 mA; VS = open – 0.3 0.5 V VRESET = 1.0 V; VS = 0 V 10 16 – mA VRESET = 1.0 V; VS = open 1.0 2.0 – mA VCT = 1.0 V; RCT = open during Watchdog operation –0.8 –1.2 –2.4 µA VCT = 1.0 V; during power-on reset operation –0.8 –1.2 –2.4 µA VRESET = 0.4 V; IRESET = 0.2 mA – 0.8 1.0 V VRESET = VCC – 0.1 V; 1 MΩ resistor (pin 2 to GND) – 0.8 1.0 V IOL1 Output voltage, LOW-level Output sink current IOL2 ICT1 CT charge current (Note 1) ICT2 VCCL1 VCCL2 Supply voltage to assert reset operation NOTE: 1. ICT source current is determined by the value of the RCT pull-up resistor to VCC. 2003 Oct 15 4 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 AC ELECTRICAL CHARACTERISTICS Characteristics measured with VCC = 5.0 V, and Tamb = 25 °C, unless otherwise specified. See Figure 27 (Test circuit 2) for test configuration used for AC parameters. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 4.0 V ≤ negative-going VCC pulse ≤ 5.0 V 8.0 – – µs tP1 Minimum power supply pulse width for detection tCLKW Clock input pulse width 3.0 – – µs tCLK Clock input cycle 20 – – µs tWDM Watchdog monitoring time (Notes 1, 6) CT = 0.1 µF; RCT = open 50 100 150 ms tWDR Watchdog reset time (Notes 2, 6) CT = 0.1 µF 1.0 2.0 3.0 ms tPR Power-on reset delay time (Notes 3, 6) VCC = rising from 0 V; CT = 0.1 µF 50 100 150 ms tPD1 Reset propagation delay time (Note 4) RESET: RL1 = 2.2 kΩ; CL1 = 100 pF – 2.0 10 µs RESET: RL2 = 10 kΩ; CL2 = 20 pF – 3.0 10 µs RESET: RL1 = 2.2 kΩ; CL1 = 100 pF – 1.0 1.5 µs RESET: RL2 = 10 kΩ; CL2 = 20 pF – 1.0 1.5 µs RESET: RL1 = 2.2 kΩ; CL1 = 100 pF – 0.1 0.5 µs RESET: RL2 = 10 kΩ; CL2 = 20 pF – 0.5 1.0 µs tPD2 tR1 Reset rise time (Note 5) tR2 tF1 Reset fall time (Note 5) tF2 NOTES: 1. ‘Watchdog monitoring time’ is the duration from the last pulse (negative-going edge) of the timer clear clock pulse until reset output pulse occurs (see Figure 20). A reset signal is output if a clock pulse is not input during this time. Watchdog monitoring time can be modified by changing the value of the RCT pull-up resistor. Monitoring time adjustments are shown in Figure 25. 2. ‘Watchdog reset time’ is the reset pulse width (see Figure 20). 3. ‘Power-on reset delay time’ is the duration measured from the time VCC exceeds the upper detection threshold (VSH) and power-on reset release is experienced (RESET output HIGH; RESET output LOW). 4. ‘Reset response time’ is the duration from when the supply voltage sags below the lower detection threshold (VSL) and reset occurs (RESET output LOW, RESET output HIGH). 5. Reset rise and fall times are measured at 10% and 90% output levels. 6. Watchdog monitoring time (tWDM), Watchdog reset time (tWDR), and power-on reset delay time (tPR) during power-on can be modified by varying the CT capacitance. The times can be approximated by applying the following formula. The recommended range for CT is 0.001 µF to 10 µF. Formula 1. Calculation for approximate tPR, tWDM, and tWDR values: tPR (ms) ≈ 1000 × CT (µF) tWDM (ms) ≈ 1000 × CT (µF) tWDR (ms) ≈ 20 × CT (µF) Example: When CT = 0.1 µF and RCT = open: tPR ≈ 100 ms tWDM ≈ 100 ms tWDR ≈ 2.0 ms 2003 Oct 15 5 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 TYPICAL PERFORMANCE CURVES 6.0 Tamb = 35 °C RESET PULL-UP R = 10 kΩ 1 .2 VRST, RESET OUTPUT VOLTAGE (V) I CC POWER SUPPLY CURRENT (mA) 1 .4 WITHOUT CLOCK SIGNALS TO WATCHDOG 1.0 0.8 0.6 WITH CLOCK SIGNALS TO WATCHDOG 0.4 0.2 0 5.0 Tamb = –25 °C, 25 °C, 75 °C 4.0 3.0 2.0 VSL VSH VOL 1.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VCC, POWER SUPPLY VOLTAGE (V) VCC, POWER SUPPLY VOLTAGE (V) SL01303 SL01304 Figure 3. Power supply current vs. voltage. Figure 4. RESET output voltage vs. supply voltage. 4.5 RESET PULL-UP R = 2.2 kΩ VSL , V SH , DETECTION THRESHOLD (V) VRST , RESET OUTPUT VOLTAGE (V) 6.0 5.0 4.0 3.0 VSL VSH 2.0 Tamb = –25 °C Tamb = 25 °C 1.0 VOL Tamb = 75 °C 0 0 1.0 2.0 3.0 4.0 5.0 VCC = RISING (VSH) VCC = FALLING (VSL) 4.4 VSH 4.3 VSL 4.2 4.1 4.0 –40 6.0 –20 0 VCC POWER SUPPLY VOLTAGE (V) 20 40 60 80 SL01302 SL01301 Figure 5. RESET output voltage vs. supply voltage. Figure 6. Detection threshold vs. temperature. 600 VCC = 5.0 V RESET PULL-UP R = 10 kΩ VOL , RESET OUTPUT SATURATION (mV) VOL , RESET OUTPUT SATURATION (mV) 600 500 400 Tamb = 75 °C 300 100 Tamb, AMBIENT TEMPERATURE (°C) 200 100 Tamb = –25 °C Tamb = 25 °C VCC = 5.0 V RESET PULL-UP R = 2.2 kΩ 500 400 Tamb = 75 °C 300 Tamb = 25 °C Tamb = –25 °C 200 100 0 0 –0.2 0 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 0 –1.8 IOL, RESET OUTPUT SINK CURRENT (mA) –2 –4 –6 –8 –10 –12 –14 –16 SL01300 SL01299 Figure 7. RESET saturation vs. sink current. 2003 Oct 15 –18 IOL, RESET OUTPUT SINK CURRENT (mA) Figure 8. RESET saturation vs. sink current. 6 Philips Semiconductors Product data System reset with built-in Watchdog timer 5.0 VCC = 5.0 V Tamb = 25 °C VOM, RESET HIGH LEVEL OUTPUT (V) VOM, RESET HIGH LEVEL OUTPUT (V) 5.2 NE56604-42 5.0 4.8 4.6 4.4 4.2 4.8 VCC = 5.0 V Tamb = 25 °C 4.6 4.4 4.2 4.0 3.8 4.0 3.6 0 –2 –4 –6 –8 –10 –12 –14 –16 0 –18 IOM, RESET HIGH OUTPUT LEAKAGE CURRENT (µA) –2.0 –4.0 –6.0 –8.0 –10 –12 –14 IOM, RESET HIGH OUTPUT LEAKAGE CURRENT (µA) SL01298 SL01297 Figure 9. RESET HIGH-level voltage vs. current. Figure 10. RESET HIGH-level voltage vs. current. 140 VCC = 5.0 V CT = 0.1 µF RCT = Open t WDM , WATCHDOG MONITORING (ms) t PR , POWER-ON RESET HOLD (ms) 140 120 100 80 VCC = 5.0 V CT = 0.1 µF RCT = Open 120 100 80 60 60 –40 –20 0 20 40 60 80 100 –40 –20 Tamb, AMBIENT TEMPERATURE (5C) 0 20 40 60 80 100 Tamb, AMBIENT TEMPERATURE (5C) SL01296 SL01295 Figure 11. Power–on reset hold time vs. temperature. Figure 12. Watchdog monitoring time vs. temperature. 100 3.0 t WDM , WATCHDOG MONITORING (ms) VCC = 5.0 V CT = 0.1 µF t WDR , WATCHDOG RESET (ms) –16 2.5 2.0 1.5 1.0 –40 –20 0 20 40 60 80 10 RCT = 100 kΩ 1 –40 100 –20 0 20 40 60 80 100 Tamb, AMBIENT TEMPERATURE (°C) Tamb, AMBIENT TEMPERATURE (°C) SL01294 SL01308 Figure 13. Watchdog reset time vs. temperature. 2003 Oct 15 RCT = 5 MΩ VCC = 5.0V CT = 0.1 µF Figure 14. Watchdog monitoring time vs. temperature. 7 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 102 VCC = 5.0 V Tamb = 25 °C VCC = 5.0 V Tamb = 25 °C t WDR , WATCHDOG RESET (ms) t PR , POWER-ON RESET HOLD (ms) 104 103 102 10 1.0 10–3 10–2 10–1 1.0 10 1.0 10–1 10–2 10–3 10 10–2 CT, CAPACITANCE (µF) 10–1 1.0 10 CT, CAPACITANCE (µF) SL01290 SL01291 Figure 15. Power-on reset hold time vs. CT. Figure 16. Watchdog reset time vs. CT. 105 VCC = 5.0 V Tamb = 25 °C t WDM , WATCHDOG MONITORING (ms) t WDM, WATCHDOG MONITORING (ms) 104 103 102 10 1.0 10–3 10–2 10–1 104 103 102 10 10 RCT = OPEN RCT = 2.2 MΩ RCT = 1.0 MΩ RCT = 470 kΩ 1.0 10–1 RCT = 200 kΩ 10–2 1.0 VCC = 5.0 V Tamb = 25 °C 10–3 10–2 10–1 1.0 SL01309 SL01307 Figure 17. Watchdog reset time vs. CT. 2003 Oct 15 10 CT, CAPACITANCE (µF) CT, CAPACITANCE (µF) Figure 18. Watchdog monitoring time vs. CT. 8 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 The Watchdog timer requires a pulse input. Normally this signal comes from the system microprocessor’s clock. For operation, an external resistor (RCT) must be connected from Pin 6 to VCC and an external capacitor (CT) from Pin 1 to ground. Normally a 0.1 µF capacitor is used for CT. The external RCT resistor and CT capacitor establish the required minimum frequency of Watchdog input signal for the device to not output a reset signal. The RCT resistor establishes, in part, the rate of charge of the CT capacitor. In the absence of a Watchdog input pulse, the CT capacitor charges to the 0.2 volt threshold of the internal comparator, causing a reset signal to be output. If microprocessor clock signals are received within the required interval, no Watchdog reset signal will be output. The Watchdog function can be disabled by grounding Pin 6 without affecting the undervoltage detection function. TECHNICAL DESCRIPTION General discussion The NE56604-42 combines a Watchdog timer and an undervoltage reset function in a single SO8 surface mount package. This provides a space-saving solution for maintaining proper operation of typical 5.0 volt microprocessor-based logic systems. Either function, or both, can force the microprocessor into a reset. While the Watchdog monitors the microprocessor operation, the undervoltage reset monitors the supply voltage to the microprocessor. If the microprocessor clock signal ceases or becomes erratic, the NE56604-42 outputs a reset signal to the microprocessor. If the microprocessor supply voltage sags to 4.2 volts or less, the NE56604-42 outputs a reset signal for the duration of the supply voltage deficiency. The undervoltage reset signal allows the microprocessor to shut down in an orderly manner to avoid system corruption. In addition to a single reset output, the NE56604-42 has complementary RESET and RESET outputs for system use. The undervoltage detection threshold incorporates hysteresis to prevent generating erratic resets. Although the temperature coefficient of detection threshold is specified over a temperature of –20 °C to +70 °C, the device will support operation in excess of this temperature range. See the supporting curves for performance over the full temperature range of –40 °C to +85 °C. Some degradation in performance will be experienced at the temperature extremes and the system designer should take this into account. VCC RCT 6 RCT 5 R 47 kΩ 0.1 V R R 58 kΩ 12 µA 54 kΩ S Q 7 1.2 µA R R R R 26 kΩ C S Q R 3 R R S Q PULSE GENERATOR R 0.2 V 1 CT 4 GND 2 8 RESET RESET SL01310 Figure 19. Functional diagram. 2003 Oct 15 9 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 Timing diagram E–F: Immediately before ‘E’, falling VCC causes the RESET signal to sag. CLK signals are still being received, CT is within normal operating range, and reset signals are not output. VCC continues to sag until the VSL undervoltage threshold is reached. At that time, reset signals are generated (RESET goes LOW; RESET goes HIGH). The timing diagram shown in Figure 20 depicts the operation of the device. Letters indicate events on the TIME axis. A: At start-up ‘A’, the VCC and RESET voltages begin to rise. Also the RESET voltage initially rises, but then abruptly returns to a LOW state. This is due to VCC reaching the level (RESET 0.8 V) that activates the internal bias circuitry, asserting RESET. At ‘E’, VCC starts to rise, and the RESET voltage rises with VCC. However, CT voltage does not start to ramp up until ‘F’, when VCC reaches the VSH upper threshold. B: Just before ‘B’, the CT voltage starts to ramp up. This is caused by, and coincident to, VCC reaching the threshold level of VSH. At this level the device is in full operation. The RESET output continues to rise as VCC rises above VSH. This is normal. G: The reset outputs are released at ‘G’ when CT reaches the upper threshold level again. After ‘G’, normal CLK signals are received, but at a lower frequency than those following event ‘C’. The frequency is above the minimum frequency required to keep the device from outputting reset signals. C: At ‘C’, VCC is above the undervoltage detect threshold, and CT has ramped up to its upper detect level. At this point, the device removes the hold on the resets. RESET goes HIGH while RESET goes LOW. Also, an internal ramp discharge transistor activates, discharging CT. G–H: At ‘H’, VCC is normal, CLK signals are being received, and no reset signals are output. At event ‘H’, the VCC starts falling, causing RESET to also fall. In a microprocessor-based system these events remove the reset from the microprocessor, allowing it to function normally. The system must send clock signals to the Watchdog Timer often enough to prevent CT from ramping up to the CT threshold, to prevent reset signals from being generated. Each clock signal discharges CT. J: At event ‘J’, VCC sags to the point where the VSL undervoltage threshold point is reached, and at that level reset signals are output (RESET to a LOW state, and RESET to a HIGH state). As the VCC voltage falls lower, the RESET voltage falls lower. C–D: Midway between ‘C’ and ‘D’, the CLK signals cease allowing the CT voltage to ramp up to its RESET threshold at ‘D’. At this time, reset signals are generated (RESET goes LOW; RESET goes HIGH). The device attempts to come out of reset as the CT voltage is discharged and finally does come out of reset when CLK signals are re-established after two attempts of CT. K: At event ‘K’, the VCC voltage has deteriorated to a level where normal internal circuit bias is no longer able to maintain a RESET, and as a result may exhibit a slight rise to something less than 0.8 V. As VCC decays even further, RESET also decreases to zero. VSH VSL VCC tCLK CLK CTthresh CT tPR tWDM tWDR RESET 0.8 V RESET A B C D E F G H J K TIME SL01283 Figure 20. Timing diagram. 2003 Oct 15 10 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 Application information The Reset Detection Threshold can be decreased by connecting an external resistor R1 from Pin 7 to VCC, as shown in Figure 21. See Figure 22 to determine the approximate value of R1 to use. The Watchdog timer’s external component values are critical to its performance. The detection threshold voltage can be adjusted by externally influencing the internal divider reference voltage. Figures 21 and 23 show a method to lower and raise the threshold voltage. Figures 22 and 24 show the influence of the pull-down and pull-up resistors on the threshold voltage. The use of a capacitor (1000 pF or larger) from Pin 7 to ground is recommended to filter out noise from being imposed on the threshold voltages. VCC The Reset Detection Threshold can be increased by connecting an external resistor R2 from Pin 7 to ground, as shown in Figure 23. See Figure 24 to determine the approximate value of R2 to use. 5.0 Vs, RESET DETECTION THRESHOLD (V) LOGIC SYSTEM R1 3 CT NE56604-42 2 RESET 8 1 CLK 7 RESET 6 GND 5 4 1000 pF VCC = 5.0 V Tamb = 25 °C VSH 4.0 VSL 3.5 3.0 0 100 200 300 400 500 600 700 R1, EXTERNAL PIN 7 TO VCC RESISTOR (kΩ) SL01327 SL01326 Figure 21. Circuit to lower detection threshold. VCC Figure 22. Reset detection threshold vs. external R1. 5.1 3 CT NE56604-42 2 RESET 8 1 Vs, RESET DETECTION THRESHOLD (V) LOGIC SYSTEM CLK 7 RESET 6 GND 4 5 R2 1000 pF VCC = 5.0 V Tamb = 25 °C 5.0 4.9 4.8 4.7 4.6 VSH 4.5 VSL 4.4 4.3 0 100 200 300 400 500 600 700 R2, EXTERNAL PIN 7 TO GROUND RESISTOR (kΩ) SL01328 SL01325 Figure 23. Circuit to raise detection threshold. 2003 Oct 15 Figure 24. Reset detection threshold vs. external R2. 11 Philips Semiconductors Product data System reset with built-in Watchdog timer The values of RCT and CT affect the Watchdog monitoring time (tWDM), the Watchdog reset time (tWDR), and power-on reset delay time (tPR). See Formula 1 in the AC Electrical Characteristics and the Timing diagram shown in Figure 20 for parameter definitions. Also see Figures 11 through 18 for typical time relationship performance. NE56604-42 t WDM , WATCHDOG MONITOR TIME (ms) 100 The effect of RCT on the Watchdog timer monitoring time at room temperature for CT = 0.1 mF is shown in Figure 25. CT = 0.1 µF Tamb = 25 °C 80 60 40 20 0 10k 100k 1M 10M 100M ∞ RCT, WATCHDOG TIMER CURRENT RESISTOR (Ω) SL01329 Figure 25. Watchdog monitoring vs. pull-up resistor RCT. 2003 Oct 15 12 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 Parametric testing DC and AC Characteristics can be tested using the circuits shown in Figures 26 and 27. Associated switch and power supply settings are shown in Table 1 and Table 2, respectively. S5 1000 pF S2 IO1 A A B C V S1 8 7 6 5 RESET VS RCT VCC RESET CLK GND S3 VO1 CT 1 IRESET CRT A CRT1 3 A ICT VO0 VCT 2 0.1 µF A ICC 4 A IO2 VCC ICLK S4 A S7 S6 V C VO2 B CRT R 1.0 MΩ VCLK CRT2 IRESET SL01284 Figure 26. Test Circuit 1 (DC parameters). Table 1. DC characteristics Test Circuit 1 switch and power supply settings Parameter Symbol S1 S2 S3 S4 S5 S6 S7 VCC VCLK VCT IRESET IRESET Read ICC B OFF OFF B OFF ON ON 5.0 V 5.0 V 0V – – ICC Reset threshold (LOW) (Note 1) VSL B OFF OFF B ON ON ON 5.0 to 4.0 V 3.0 V 3.0 V – – VO1, CRT1 Reset threshold (HIGH) (Note 2) VSH B OFF OFF B ON ON ON 4.0 to 5.0 V 3.0 V 3.0 V – – VO1, CRT1 Clock input threshold (Note 3) VTH B OFF OFF B OFF ON ON 5.0 V 0 to 3.0 V 1.0 V – – ICLK Clock input current (HIGH) ITH B OFF OFF B OFF ON ON 5.0 V 5.0 V 0V – – ICLK Clock input current (LOW) ITL B OFF OFF B OFF ON ON 5.0 V 0V 0V – – ICLK VOH1 B OFF ON B ON ON ON 5.0 V 5.0 V 3.0 V –5.0 µA – VO1 VOH2 B ON OFF C ON ON ON 5.0 V 5.0 V 3.0 V – –5.0 µA VO2 VOL1 B ON ON B ON ON ON 5.0 V 5.0 V 3.0 V 3.0 mA – VO1 VOL2 B ON ON B ON ON ON 5.0 V 5.0 V 3.0 V 10 mA – VO1 VOL3 B OFF OFF C ON ON ON 5.0 V 5.0 V 3.0 V – 0.5 mA VO2 VOL4 B OFF OFF C ON ON ON 5.0 V 5.0 V 3.0 V – 1 mA VO2 Reset output sink current (N t 4) (Note IOL1 C ON OFF B ON ON ON 5.0 V 5.0 V 3.0 V – – IO1 IOL2 A OFF OFF B ON ON ON 5.0 V 5.0 V 3.0 V – – IO2 CT charge current 1 ICT1 B OFF OFF B OFF OFF ON 5.0 V – 1.0 V – – ICT CT charge current 2 ICT2 B OFF OFF B ON OFF ON 5.0 V – 1.0 V – – ICT Minimum power supply for RESET (Note 5) VCCL1 B OFF ON B ON ON ON 0 to 2.0 V 0V 0V – – VO1, VCC Minimum power supply for RESET (Note 6) VCCL2 B ON OFF A ON ON ON 0 to 2.0 V 0V 0V – – VO2, VCC Power supply current Reset output voltage (HIGH) Reset output voltage (LOW) NOTES: 1. Decrease VCC from 5.0 V to 4.0 V and note the VCC value when VO1 (observed on CRT1) transitions to an abrupt LOW state. 2. Increase VCC from 4.0 V to 5.0 V and note the VCC value when VO1 (observed on CRT1) transitions to an abrupt HIGH state. 3. Increase the Clock voltage (VCLK) from 0 V to 3.0 V and observe the value of VCLK when ICLK transitions to an abrupt increase. 4. Measured with VO0 = 1.0 V. 5. Increase VCC from 0 V to 2.0 V and note the VCC value when VO1 (observed on CRT1) transitions to an abrupt LOW state. The VO1 value will initially track the VCC voltage increase until the internal circuit bias becomes active, at which time the VO1 value will return to a LOW state. 6. Increase VCC from 0 V to 2.0 V and note the VCC value when VO2 (observed on CRT2) starts to track the VCC voltage. 2003 Oct 15 13 Philips Semiconductors Product data System reset with built-in Watchdog timer R 2.2 kΩ 100 pF NE56604-42 VCC S1 CRT A 8 7 6 5 RESET VS RCT VCC C CRT B CRT1 CRT4 CT RESET CLK GND 1 2 3 4 VCCA S2 0.1 µF CRT A CRT2 R 10 kΩ C B 20pF VCLK CRT VCLKA CRT3 SL01285 Figure 27. Test Circuit 2 (AC parameters). Table 2. Switch and power supply settings, AC parameters Parameter VCC pulse width for detection (Note 1) Clock input pulse width (Note 2) Symbol S1 S2 tP1 C C VCCA – 5.0 V t1 4.0 V tCLKW A VCC C VCLKA 1.4 V t2 tCLK A – 1, 2, 3 – 1, 2, 3 – 1, 2, 3 t3 – C CRT 0V 5.0 V 1.4 V t2 t2 0V Clock input cycle (Note 3) VCLK – 5.0 V 1.4 V t2 0V t3 Watchdog monitoring time tWDM A A – 5.0 V – 5.0 V 1, 2, 3 Watchdog reset time Power-on reset delay time tWDR A A – 5.0 V – 5.0 V 1, 2, 3 tPR B to A A – 5.0 V – 5.0 V 1, 2, 3 RESET, RESET propagation delay time tPD1 C B – – 0V 1, 2 – – 0V 2, 3 5.0 V 4.0 V tPD2 C B 5.0 V 4.0 V RESET, RESET rise time RESET, RESET fall time tR1 A A – 5.0 V – 5.0 V 1 tR2 A A – 5.0 V – 5.0 V 3 tF1 A A – 5.0 V – 5.0 V 1 tF2 A A – 5.0 V – 5.0 V 3 NOTES: 1. t1 = 8.0 µs. 2. t2 = 3.0 µs. 3. t3 = 20 µs. 2003 Oct 15 14 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 PACKING METHOD The NE56604-42 is packed in reels, as shown in Figure 28. GUARD BAND TAPE REEL ASSEMBLY TAPE DETAIL COVER TAPE CARRIER TAPE BARCODE LABEL BOX SL01305 Figure 28. Tape and reel packing method 2003 Oct 15 15 Philips Semiconductors Product data System reset with built-in Watchdog timer SO8: plastic small outline package; 8 leads; body width 3.9 mm 2003 Oct 15 16 NE56604-42 SOP005 Philips Semiconductors Product data System reset with built-in Watchdog timer NE56604-42 REVISION HISTORY Rev Date Description _4 20031015 Product data (9397 750 12115). ECN 853-2250 30313 of 08 September 2003. Super sedes data of 2001 Aug 22 (9397 750 08732). Modifications: • Change package version to SOP005 in Ordering information and Package outline sections. _3 20010822 Product data (9397 750 08732). ECN 853-2250 26949 of 22 August 2001. Supersedes data of 2001 Jun 19. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 10-03 For sales offices addresses send e-mail to: [email protected]. Document order number: 2003 Oct 15 17 9397 750 12115