MOSEL V436632Y24VXTG-75

MOSEL VITELIC
V436632Y24V
256MB 144-PIN UNBUFFERED SDRAM
SODIMM, 32M X 64 3.3VOLT
PRELIMINARY
Features
Description
■ JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
■ Serial Presence Detect with E2PROM
■ Nonbuffered
■ Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
■ Single +3.3V (± 0.3V) Power Supply
■ All Device Pins are LVTTL Compatible
■ 8192 Refresh Cycles every 64 ms
■ Self-Refresh Mode
■ Internal Pipelined Operation; Column Address
can be changed every System Clock
■ Programmable Burst Lengths: 1, 2, 4, 8
■ Auto Precharge and Piecharge all Banks by A10
■ Data Mask Function by DQM
■ Mode Register Set Programming
■ Programmable (CAS Latency: 2, 3 Clocks)
■ TSOP component package
The V436632Y24V memory module is organized
33,554,432 x 64 bits in a 144 pin SODIMM. The
32M x 64 memory module uses 8 Mosel-Vitelic 16M
x 16 SDRAM. The x64 modules are ideal for use in
high performance computer systems where
increased memory density and fast access times
are required.
32M x 8
32M x 8
59
1
Configuration
V436632Y24VXTG-75PC
-75PC, CL=2,3
(133 MHz)
32M x 64
V436632Y24VXTG-75
-75, CL=3
(133 MHz)
32M x 64
V436632Y24VXTG-10PC
-10PC, CL=2,3
(100 MHz)
32M x 64
32M x 8
32M x 8
61
143
Pin 2 on Backside
V436632Y24V Rev.1.2 March 2002
Speed
Grade
Part Number
Pin 144 on Backside
1
V436632Y24V
MOSEL VITELIC
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB1
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
CKE1
CS0
NC
CS1
A12
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Note:
1. RAS, CAS, WE CASx, CSx are active low signals.
Pin Names
A0–A12, BA0, BA1
Address, Bank Select
DQ0–DQ63
Data Inputs/Outputs
RAS
Row Address Strobes
CAS
Column Address Strobes
WE
Write Enable
CS0, CS1
Chip Select
DQMB0–DQMB7
Output Enable
CKE0, CKE1
Clock Enable
CLK0, CLK1
Clock
SDA
Serial Input/Output
SCL
Serial Clock
VDD
Power Supply
VSS
Ground
NC
No Connect (Open)
V436632Y24V Rev. 1.2 March 2002
2
V436632Y24V
MOSEL VITELIC
Part Number Information
V
4
3
66
32
Y 2
4
V
X T
G - XX
MOSEL VITELIC
MANUFACTURED
SDRAM
SPEED
75PC = PC133 CL2,3
75
= PC133 CL3
10PC = PC100 CL2,3
LEAD FINISH
G = GOLD
3.3V
COMPONENT
PACKAGE, T=TSOP
WIDTH
DEPTH
COMPONENT A=0.17u B=0.14u
REV LEVEL
144 PIN SODIMM
X16 COMPONENT
LVTTL
REFRESH
RATE 8K
4 BANKS
Block Diagram
CS0
WE
DQMB0
WE CS
UDQM
DQ0–7
DQMB4
WE CS
UDQM
DQMB1
LDQM
DQ8–15
DQMB5
LDQM
DQ40–47
DQMB2
WE CS
UDQM
DQ16–23
DQMB6
WE CS
UDQM
DQ43–54
U0
DQ32–39
U2
U1
U3
LDQM
DQ24–31
DQMB7
LDQM
DQ55–63
WE CS
UDQM
DQ0–7
DQMB4
WE CS
UDQM
DQ32–39
DQMB3
CS1
WE
DQMB0
U4
U6
DQMB1
LDQM
DQ8–15
DQMB5
LDQM
DQ40–47
DQMB2
WE CS
UDQM
DQ16–23
DQMB6
WE CS
UDQM
DQ43–54
U5
DQMB3
LDQM
VDD
VSS
U7
DQ24–31
U0, U1
CLK0
U0–U7
CKE0
U0–U3
CKEI
U4–U7
RAS
U0–U7
U2, U3
0Ω
U4, U5
CLKI
0Ω
U6, U7
SPD
U0–U7
SCL
Note: All resistors are 10 Ohms
V436632Y24V Rev. 1.2 March 2002
DQ55–63
LDQM
U0–U7
A0–A11, BA0, BA1
CAS
DQMB7
3
A0 A1 A2
SDA
V436632Y24V
MOSEL VITELIC
Serial Presence Detect Information
A serial presence detect storage device - E2PROM is assembled onto the module. Information about the
module configuration, speed, etc. is written into the
E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire
bus)
SPD-Table for modules:
Byte
Number
Hex Value
Function Described
SPD Entry Value
-75PC
-75
-10PC
0
Number of SPD bytes
128
80
80
80
1
Total bytes in Serial PD
256
08
08
08
2
Memory Type
SDRAM
04
04
04
3
Number of Row Addresses (without BS bits)
13
0D
0D
0D
4
Number of Column Addresses ( x16 SDRAM)
9
09
09
09
5
Number of DIMM Banks
2
02
02
02
6
Module Data Width
64
40
40
40
7
Module Data Width (continued)
0
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
9
SDRAM Cycle Time at CL=3
7.5 ns/10.0 ns
75
75
A0
10
SDRAM Access Time from Clock at CL=3
5.4 ns/10.0ns
54
54
60
11
Dimm Config (Error Det/Corr.)
none
00
00
00
12
Refresh Rate/Type
Self-Refresh, 7.8 µs
82
82
82
13
SDRAM width, Primary
x16
10
10
10
14
Error Checking SDRAM Data Width
n/a / x16
00
00
00
15
Minimum Clock Delay from Back to Back Random Column Address
tccd = 1 CLK
01
01
01
16
Burst Length Supported
1, 2, 4 & 8
0F
0F
0F
17
Number of SDRAM Banks
4
04
04
04
18
Supported CAS Latencies
CL = 2 / 3
06
06
06
19
CS Latencies
CS Latency = 0
01
01
01
20
WE Latencies
WL = 0
01
01
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
00
00
22
SDRAM Device Attributes: General
Vcc tol ± 10%
0E
0E
0E
23
Minimum Clock Cycle Time at CAS Latency = 2
7.5 ns/10.0 ns &
Not Supported
75
A0
A0
24
Maximum Data Access Time from Clock for CL
=2
7.5ns/10.0ns &
Not Supported
54
60
60
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
00
00
26
Maximum Data Access Time from Clock at CL
=1
Not Supported
00
00
00
27
Minimum Row Precharge Time
15 ns / 20 ns
0F
14
14
28
Minimum Row Active to Row Active Delay tRRD
14 ns/15 ns/16 ns
0E
0F
10
V436632Y24V Rev. 1.2 March 2002
4
V436632Y24V
MOSEL VITELIC
SPD-Table for modules: (Continued)
Byte
Number
Hex Value
Function Described
SPD Entry Value
-75PC
-75
-10PC
29
Minimum RAS to CAS Delay tRCD
15 ns/20 ns
0F
14
14
30
Minimum RAS Pulse Width tRAS
42 ns/45 ns
2A
2D
2D
31
Module Bank Density (Per Bank)
128 Mbyte
20
20
20
64
SDRAM Input Setup Time
1.5 ns/2.0 ns
15
15
20
33
SDRAM Input Hold Time
0.8 ns/ 1.0 ns
08
08
10
34
SDRAM Data Input Setup Time
1.5 ns/2.0 ns
15
15
20
35
SDRAM Data Input Hold Time
0.8 ns/1.0 ns
08
08
10
00
00
00
02
02
12
E5
2A
98
40
40
40
00
00
00
Reserved
00
00
00
126
Intel Specification for Frequency
64
64
64
127
Supported Frequency
128+
Unused Storage Location
00
00
00
62-61
Superset Information (May be used in Future)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65-71
72
Revision 2 / 1.2
Mosel Vitelic
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
73-90
Module Part Number (ASCII)
91-92
PCB Identification Code
1 = US, 2 = Taiwan
V436632Y24V
Current PCB Revision
93
Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
94
Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
95-98
99-125
Assembly Serial Number
V436632Y24V Rev. 1.2 March 2002
byte 95 = LSB, byte 98 =
MSB
5
V436632Y24V
MOSEL VITELIC
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Limit Values
Symbol
Parameter
Min.
Max.
Unit
VIH
Input High Voltage
2.0
VCC +0.3
V
VIL
Input Low Voltage
–0.5
0.8
V
V OH
Output High Voltage (IOUT = –4.0 mA)
2.4
—
V
VOL
Output Low Voltage (IOUT = 4.0 mA)
—
0.4
V
II(L)
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V)
–10
10
µA
IO(L)
Output leakage current
(DQ is disabled, 0V < VOUT < VCC)
–10
10
µA
Capacitance
TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz
Symbol
Parameter
Limit Values (Max.)
Unit
CI1
Input Capacitance (A0 to A11, RAS, CAS, WE)
40
pF
CI2
Input Capacitance (CS0, CSI)
25
pF
CICL
Input Capacitance (CLK0-CLK1)
28
pF
CI3
Input Capacitance (CKE0, CKEI)
20
pF
CI4
Input Capacitance (DQMB0-DQMB7)
10
pF
CSC
Input Capacitance (SCL, SA0-2)
8
pF
CIO
Input/Output Capacitance
18
pF
Absolute Maximum Ratings
Parameter
Max.
Units
Voltage on VDD Supply Relative to V SS
-1 to 4.6
V
Voltage on Input Relative to VSS
-1 to 4.6
V
Operating Temperature
0 to +70
°C
-55 to 125
°C
6.5
W
Storage Temperature
Power Dissipation
V436632Y24V Rev. 1.2 March 2002
6
V436632Y24V
MOSEL VITELIC
Standby and Refresh Currents1
TA = 0°C to 70°C, VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
75PC/75
10PC
Unit
Note
ICC1
Operating Current
Burst length = 4, CL = 3
tRC> = tRC(min),
tCK> = tCK(min), IO = 0 mA
2 Bank Interleave Operation
920
680
mA
1,2
ICC2P
Precharged Standby Current in
Power Down Mode
CKE< = VIL(max), tCK> = tCK(min)
16
16
mA
ICC2N
Precharged Standby Current in
Non-Power Down Mode
CKE> = VIH(min), tCK> = tCK(min), Input changed once in 3 cycles
160
120
mA
ICC3P
Active Standby Current in Power
Down Mode
CKE< = VIL(max), tCK> = tCK(min)
80
80
mA
ICC3N
Active Standby Current in Non-Pow- CKE> = VIH(min), tCK> = tCK(min), Iner Down Mode
put changed one time
200
180
mA
CS = High
ICC4
Burst Operating Current
Burst length = Full Page,
tRC = Infinite, CL = 3,
tCK> = tCK(min), IO = 0 mA
2 Banks Activated
600
400
mA
1, 2
ICC5
Auto Refresh Current
tRC>= tRC(min)
1920
1760
mA
1,2
ICC6
Self Refresh Current
CKE = <0.2 V
Standard
24
24
mA
1,2
L-Version
13.6
13.6
V436632Y24V Rev. 1.2 March 2002
7
CS = High
V436632Y24V
MOSEL VITELIC
AC Characteristics 3,4
TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns
Limit Values
-75PC
#
Symbol Parameter
Min.
-75
Max.
Min.
-10PC
Max.
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
tCK
fCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
7.5
System frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
133
–
–
133
100
–
–
100
100
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
–
–
5.4
6
–
–
5.4
6
–
–
6
6
ns
ns
7.5
10
10
10
ns
ns
4,5
4
tCH
Clock High Pulse Width
2.5
–
2.5
–
3
–
ns
6
5
tCL
Clock Low Pulse Width
2.5
–
2.5
–
3
–
ns
6
6
tCS
Input Setup time
1.5
–
1.5
–
2
–
ns
7
7
tCH
Input Hold Time
0.8
–
0.8
–
1
–
ns
7
8
tCKSP
CKE Setup Time (Power down mode)
2
–
2
–
2
–
ns
8
9
tCKSR
CKE Setup Time (Self Refresh Exit)
8
–
8
–
8
–
ns
9
10
tT
Transition time (rise and fall)
1
–
1
–
1
–
ns
RAS to CAS delay
15
–
20
–
20
–
ns
Common Parameters
11
tRCD
12
tRC
Cycle Time
70
120k
70
120k
70
120k
ns
13
tRAS
Active Command Period
42
–
45
–
45
–
ns
14
tRP
Precharge Time
15
–
20
–
20
–
ns
15
tRRD
Bank to Bank Delay Time
14
–
15
–
20
–
ns
16
tCCD
CAS to CAS delay time (same bank)
1
–
1
–
1
–
CLK
Refresh Cycle
17
tSREX
Self Refresh Exit Time
10
–
10
–
10
–
ns
9
18
tREF
Refresh Period (8192 cycles)
64
–
64
–
64
–
ms
8
4
Read Cycle
19
tOH
Data Out Hold Time
3
–
3
–
3
–
ns
20
tLZ
Data Out to Low Impedance Time
0
–
0
–
0
–
ns
21
tHZ
Data Out to High Impedance Time
3
7.5
3
7.5
3
8
ns
22
tDQZ
DQM Data Out Disable Latency
2
–
2
–
2
–
CLK
10
Write Cycle
23
tDPL
Data input to Precharge (write recovery)
1
–
1
–
1
–
CLK
24
tDAL
Data In to Active/refresh
5
–
5
–
5
–
CLK
25
tDQW
DQM Write Mask Latency
0
–
0
–
0
–
CLK
V436632Y24V Rev. 1.2 March 2002
8
11
V436632Y24V
MOSEL VITELIC
Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No
Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
CLOCK
50 Ohm
0.4V
tCL
tSETUP
Z=50 Ohm
tT
I/O
tHOLD
50 pF
1.4V
INPUT
tAC
tAC
tLZ
I/O
tOH
50 pF
1.4V
OUTPUT
Measurement conditions for
tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
tDAL is equivalent to tDPL + tRP.
V436632Y24V Rev. 1.2 March 2002
9
V436632Y24V
MOSEL VITELIC
Package Diagram
144 Pin SODIMM
144 Pin SODIMM
TSOP component package
0.039
1.25
0.787
59
1
Pin 2 on Backside
61
143
3.3V
Pin 144 on Backside
2.661
NOTE:
1. All dimensions in inches.
Tolerances ±0.005 unless otherwise specified.
V436632Y24V Rev. 1.2 March 2002
10
0.140
0.143
V436632Y24V
MOSEL VITELIC
Module Label Information
Label Information
Module Density
MOSEL VITELIC
Part Number
Criteria of PC100 or PC133
(refer to MVI datasheet)
DIMM manufacture date code
CLX
512MB
V436664S24VATG-10PC
V436632Y24VXTG-XX
256MBCLX
CLX
V436616R24XXX-XX
128MB
PC133U-XXX-542-A
0130-M 682165
0130-K682165
Assembly in Taiwan
CAS Latency
2 = CL2
3 = CL3
PC133 U - XXX - 54 2 - A
UNBUFFERED DIMM
16Based
Based
8
Gerber file Intel® PC100 x 16
CL = 3 or 2 (CLK)
tRCD = 3 or 2 (CLK)
tRP = 3 or 2 (CLK)
V436632Y24V Rev. 1.2 March 2002
JEDEC SPD Revision 2
tAC = 5.4 ns
11
V436632Y24V
MOSEL VITELIC
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RICHARDSON, TX 75081
PHONE: 214-352-3775
FAX: 214-904-9029
© Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
V436632Y24V Rev. 1.2 March 2002
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