MOSEL V437216C04VDTG-75

MOSEL VITELIC
PRELIMINARY
V437216C04VDTG-75
3.3 VOLT 16M x 72 HIGH PERFORMANCE
PC133 REGISTER PLL ECC SDRAM
MODULE
Features
Description
■ 168 Pin Registered ECC 16,777,216 x 72 bit
Oganization SDRAM Modules
■ Utilizes High Performance 16M x 4 SDRAM in
TSOPII-54 Packages
■ Fully PC Board Layout Compatible to INTEL’S
Rev 1.2 Module Specification
■ Single +3.3V (± 0.3V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are LVTTL Compatible
■ 4096 Refresh Cycles every 64 ms
■ Serial Present Detect (SPD)
■ SDRAM Performance
The V437216C04VDTG-75 memory module is
organized 16,777,216 x 72 bits in a 168 pin dual in
line memory module (DIMM). The 16M x 72
registered DIMM uses 18 Mosel-Vitelic 16M x 4
ECC SDRAM. The x72 registered modules are ideal
for use in high performance computer systems
where increased memory density and fast access
times are required.
Key Component Timing Parameters
-7
Units
tCK
Clock Frequency (max.)
143
MHz
tAC
Clock Access Time CAS
Latency = 3
5.4
ns
■ Module Frequency vs AC Parameter
Frequency
V437216C04VDTG-75
133 MHz (PC)
V437216C04VDTG-75 Rev. 1.2 July 2001
CL
(CAS Latency)
tRCD
tRP
tRC
Unit
3
3
3
8
CLK
1
MOSEL VITELIC
V437216C04VDTG-75
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO
CB1
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2
CB3
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1*
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2*
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4
CB5
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1*
A12
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6
CB7
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
REGE
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3*
NC
SA0
SA1
SA2
VCC
Notes:
*
These pins are not used in this module.
Pin Names
A0–A11
Address Inputs
SDA
Serial Data OUT for Presence
Detect
SA0–A2
Serial Data IN for Presence
Detect
I/O1–I/O64
Data Inputs/Outputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Read/Write Input
CB0–CB4
Check Bits (x72 Organization)
BA0, BA1
Bank Selects
NC
No Connection
CKE0
Clock Enable
REGE
Register Enable
CS0, CS2
Chip Select
DU
Don’t Use
CLK0–CLK3
Clock Input
DQM0–DQM7
Data Mask
VCC
Power (+3.3 Volts)
VSS
Ground
SCL
Clock for Presence Detect
V437216C04VDTG-75 Rev. 1.2 July 2001
2
MOSEL VITELIC
V437216C04VDTG-75
Module Part Number Information
V
4
3
72
16
C
0
4
V
D
G
T
-
75
MOSEL-VITELIC
MANUFACTURED
-75
SDRAM
PC133 3-3-3
GOLD
TSOP
D VERSION
3.3V
LVTTL
WIDTH
DEPTH
4 BANKS
168 PIN REGISTERED
DIMM X 4 COMPONENT
REFRESH
RATE 4K
Block Diagram
RCS0
RQM0
I/O1–I/O4
10Ω
I/O5–I/O8
10Ω
RQM1
I/O9–I/O12
10Ω
I/O13–I/O16
10Ω
CS
DQM
I/O1–I/O4 D0
CS
DQM
I/O1–I/O4 D1
CS
DQM
I/O1–I/O4 D2
CS
DQM
I/O1–I/O4 D3
RQM4
I/O33–I/O36
10Ω
I/O37–I/O40
10Ω
RQM5
I/O41–I/O44
10Ω
I/O45–I/O48
10Ω
CS
DQM
I/O1–I/O4 D9
CS
DQM
I/O1–I/O4 D10
CS
DQM
I/O1–I/O4 D11
CS
DQM
I/O1–I/O4 D12
RAS
CAS
CS
CB1–CB3
10Ω
DQM
I/O1–I/O4 D4
CS
CB4–CB7
10Ω
WE
DQM
I/O1–I/O4 D13
CKE0
DQM0–DQM7
RCS2
RQM2
I/O17–I/O20
10Ω
CS
DQM
I/O1–I/O4 D5
RQM6
I/O49–I/O52
10Ω
CS
DQM
I/O1–I/O4 D14
I/O21–I/O24
10Ω
I/O53–I/O56
10Ω
CS
DQM
I/O1–I/O4 D15
RRAS
D0–D17
RCAS
D0–D17
RWE
D0–D17
R0CKE0, R1CKE0
RDQM0–RDQM7
CS0, CS
RC0, RCS2
A0–A11
RA0–RA11
D0–D17
RBA0, RBA1
D0–D17
BA0, BA1
CS
DQM
I/O1–I/O4 D6
R
E
G
I
S
T
E
R
VDD
10K
REGE
RQM3
I/O25–I/O28
10Ω
I/O29–I/O32
10Ω
CS
DQM
I/O1–I/O4 D7
CS
DQM
I/O1–I/O4 D8
V437216C04VDTG-75 Rev. 1.2 July 2001
RQM7
I/O57–I/O60
10Ω
I/O61–I/O64
10Ω
CS
DQM
I/O1–I/O4 D16
PLL CLK
CLK0
10K
10K
CS
DQM
I/O1–I/O4 D17
3
CLK1–CLK3
PLL
12pF
12pF
D0–D17
MOSEL VITELIC
V437216C04VDTG-75
Serial Presence Detect Information
written into the E2PROM device during module production using a serial presence detect protocol (I2C
synchronous 2-wire bus)
A serial presence detect storage device –
– is assembled onto the module. Information about the module configuration, speed, etc. is
E2PROM
SPD-Table for 75 modules:
Hex Value
Byte Number
Function Described
SPD Entry Value
16Mx72
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
12
0C
4
Number of Column Addresses (for x4 SDRAM)
10
0A
5
Number of DIMM Banks
1
01
6
Module Data Width
72
48
7
Module Data Width (continued)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAM Cycle Time at CL=3
7.5 ns
75
10
SDRAM Access Time from Clock at CL=3
5.4 ns
54
11
Dimm Config (Error Det/Corr.)
ECC
02
12
Refresh Rate/Type
Self-Refresh, 15.8µs
80
13
SDRAM width, Primary
x4
04
14
Error Checking SDRAM Data Width
n/a / x4
04
15
Minimum Clock Delay from Back to Back Random
Column Address
tccd = 1 CLK
01
16
Burst Length Supported
1, 2, 4, 8, full page
8F
17
Number of SDRAM Banks
4
04
18
Supported CAS Latencies
CL = 3
04
19
CS Latencies
CS Latency = 0
01
20
WE Latencies
WL = 0
01
21
SDRAM DIMM Module Attributes
Registered/Buffered
1F
22
SDRAM Device Attributes: General
Vcc tol ± 10%
0E
23
Minimum Clock Cycle Time at CAS Latency = 2
Not Supported
00
24
Maximum Data Access Time from Clock for CL = 2
Not Supported
00
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
26
Maximum Data Access Time from Clock at CL = 1
Not Supported
00
27
Minimum Row Precharge Time
20 ns
14
28
Minimum Row Active to Row Active Delay tRRD
15 ns
0F
29
Minimum RAS to CAS Delay tRCD
20 ns
14
30
Minimum RAS Pulse Width tRAS
45 ns
2D
V437216C04VDTG-75 Rev. 1.2 July 2001
4
MOSEL VITELIC
V437216C04VDTG-75
SPD-Table for 75 modules: (Continued)
Hex Value
Byte Number
Function Described
SPD Entry Value
16Mx72
128 MByte
20
31
Module Bank Density (Per Bank)
32
SDRAM Input Setup Time
1.5 ns
15
33
SDRAM Input Hold Time
0.8 ns
08
34
SDRAM Data Input Setup Time
1.5 ns
15
35
SDRAM Data Input Hold Time
0.8 ns
08
62-61
Superset Information (May be used in Future)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65-71
72
00
Revision 2
02
C6
Mosel Vitelic
40
Manufacturer’s JEDEC ID Code (cont.)
00
Manufacturing Location
73-90
Module Part Number (ASCII)
91-92
PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
V437216C04VDTG-75
95-98
Assembly Serial Number
99-125
Reserved
00
126
Intel Specification for Frequency
64
127
Reserved
8D
128+
Unused Storage Location
00
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Limit Values
Symbol
Parameter
Min.
Max.
Unit
VIH
Input High Voltage
2.0
VCC+0.3
V
VIL
Input Low Voltage
–0.3
0.8
V
VOH
Output High Voltage (IOUT = –4.0 mA)
2.4
—
V
VOL
Output Low Voltage (IOUT = 4.0 mA)
—
0.4
V
II(L)
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V)
–10
10
µA
IO(L)
Output leakage current
(DQ is disabled, 0V < VOUT < VCC)
–10
10
µA
V437216C04VDTG-75 Rev. 1.2 July 2001
5
MOSEL VITELIC
V437216C04VDTG-75
Capacitance
TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz
Symbol
Parameter
Limit Values
Unit
CI1
Input Capacitance (A0 to A11, RAS, CAS, WE)
15
pF
CI2
Input Capacitance (CS0-CS3)
15
pF
CICL
Input Capacitance (CLK0)
20
pF
CI3
Input Capacitance (CKE0)
15
pF
CI4
Input Capacitance (DQM0-DQM7)
15
pF
CIO
Input/Output Capacitance (I/O1-I/064)
16
pF
CSC
Input Capacitance (SCL, SA0-2)
8
pF
CSD
Input/Output Capacitance
18
pF
Absolute Maximum Ratings
Parameter
Max.
Units
Voltage on VDD Supply Relative to VSS
-1 to 4.6
V
Voltage on Input Relative to VSS
-1 to 4.6
V
Operating Temperature
0 to +70
°C
-55 to 125
°C
9
W
Storage Temperature
Power Dissipation
V437216C04VDTG-75 Rev. 1.2 July 2001
6
MOSEL VITELIC
V437216C04VDTG-75
Standby and Refresh Currents1
TA = 0°C to 70°C, VCC = 3.3V ± 0.3V
Symbol Parameter
Test Conditions
16M x 72
Unit
Note
ICC1
Operating Current
Burst length = 4, CL = 3
tRC> = tRC(min),
tCK> = tCK(min), IO = 0 mA
2 Bank Interleave Operation
2700
mA
1,2
ICC2P
Precharged Standby Current in Power
Down Mode
CKE< = VIL(max), tCK> = tCK(min)
36
mA
ICC2N
Precharged Standby Current in
Non-Power Down Mode
CKE> = VIH(min), tCK> = tCK(min), Input
changed once in 3 cycles
810
mA
ICC3P
Active Standby Current in Power
Down Mode
CKE< = VIL(max), tCK> = tCK(min)
144
mA
ICC3N
Active Standby Current in Non-Power
Down Mode
CKE> = VIH(min), tCK> = tCK(min), Input
changed one time
990
mA
CS =
High
ICC4
Burst Operating Current
tRC = Infinite, CL = 3,
tCK> = tCK(min), IO = 0 mA
2 Banks Activated
2160
mA
1, 2
ICC5
Auto Refresh Current
tRC>= tRC(min)
2700
mA
1,2
ICC6
Self Refresh Current
CKE = <0,2 V
Standard
18
mA
1,2
L-version
7.2
V437216C04VDTG-75 Rev. 1.2 July 2001
7
CS =
High
MOSEL VITELIC
V437216C04VDTG-75
AC Characteristics 3,4
TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns
Limit Values
-75
#
Symbol
Parameter
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
tCK
fCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
10
System frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
100
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
–
–
5.4
6
ns
ns
ns
ns
4,5
4
tCH
Clock High Pulse Width
2.5
–
ns
6
5
tCL
Clock Low Pulse Width
2.5
–
ns
6
6
tCS
Input Setup time
1.5
–
ns
7
7
tCH
Input Hold Time
0.8
–
ns
7
8
tCKSP
CKE Setup Time (Power down mode)
2.5
–
ns
8
9
tCKSR
CKE Setup Time (Self Refresh Exit)
8
–
ns
9
10
tT
0.3
1.2
ns
Transition time (rise and fall)
Common Parameters
11
tRCD
RAS to CAS delay
20
–
ns
6
12
tRC
Cycle Time
60
–
ns
6
13
tRAS
Active Command Period
45
100K
ns
6
14
tRP
Precharge Time
20
–
ns
6
15
tRRD
Bank to Bank Delay Time
15
–
ns
6
16
tCCD
CAS to CAS delay time (same bank)
1
–
CLK
Refresh Cycle
17
tSREX
Self Refresh Exit Time
10
–
ns
18
tREF
Refresh Period (8192 cycles)
64
–
ms
Read Cycle
19
tOH
Data Out Hold Time
3
–
ns
20
tLZ
Data Out to Low Impedance Time
1
–
ns
21
tHZ
Data Out to High Impedance Time
3
7
ns
22
tDQZ
DQM Data Out Disable Latency
–
2
CLK
Write Cycle
23
tDPL
Data input to Precharge (write recovery)
2
–
CLK
24
tDQW
DQM Write Mask Latency
0
–
CLK
V437216C04VDTG-75 Rev. 1.2 July 2001
8
2
7
MOSEL VITELIC
V437216C04VDTG-75
Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No
Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have VIL = 0.4V and VIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
CLOCK
50 Ohm
0.4V
tCL
tSETUP
Z=50 Ohm
tT
I/O
tHOLD
50 pF
1.4V
INPUT
tAC
tAC
tLZ
I/O
tOH
50 pF
1.4V
OUTPUT
Measurement conditions for
tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11. tDAL is equivalent to tDPL + tRP.
V437216C04VDTG-75 Rev. 1.2 July 2001
9
MOSEL VITELIC
V437216C04VDTG-75
Package Diagram
L-DIM-168-30
SDRAM DIMM Module Package
All measurements in mm
133.37
127.35
17.80
43.15
(4.0 max)
10
11
40
41
84
3.0
1
42.18
1.27 ± 0.100
63.68
A
94
95
124
125
168
4.0
85
B
D
6.35
2.50
2.0
4.45
Detail B
2.26
RADIUS
1.27 + 0.10
Tolerances: ± (0.13) unless otherwise specified.
V437216C04VDTG-75 Rev. 1.2 July 2001
0.2 ± 0.15
2.0
3.175
Detail A
1.0 ± 0.05
1.27
3.125
3.125
6.35
10
Detail C
MOSEL VITELIC
V437216C04VDTG-75
Label Information
MOSEL VITELIC
Part Number
Criteria of PC100 or PC133
(refer to MVI datasheet)
V437216C04VDTG-75
PC133R-333-542-A
Taiwan XXXX-XXXXXXX
DIMM manufacture date code
Trace Code
PC133 R - 333 - 54 2 - A
Registered DIMM
Gerber file Intel® PC100 x 4 Based
CL = 3 (CLK)
tRCD = 3 (CLK)
tRP = 3 (CLK)
V437216C04VDTG-75 Rev. 1.2 July 2001
JEDEC SPD Revision 2.0
tAC = 5.4 ns
11
MOSEL VITELIC
WORLDWIDE OFFICES
V437216C04VDTG-75
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
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TAIPEI
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FAX: +49 7032 2796 22
U.S. SALES OFFICES
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FAX: 408-433-0952
302 N. EL CAMINO REAL #200
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FAX: 949-361-7807
© Copyright 2001, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
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means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 214-826-6176
FAX: 214-828-9754
7/01
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461