MOSEL V436664S24VXTG-75

MOSEL VITELIC
V436664S24V
3.3 VOLT 64M x 64 HIGH PERFORMANCE
UNBUFFERED SDRAM MODULE
PRELIMINARY
Features
Description
■ 168 Pin Unbuffered 67,108,864 x 64 bit
Oganization SDRAM Modules
■ Utilizes High Performance 32M x 8 SDRAM in
TSOPII-54 Packages
■ Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
■ Single +3.3V (± 0.3V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are LVTTL Compatible
■ 8192 Refresh Cycles every 64 ms
■ Serial Present Detect (SPD)
The V436664S24V memory module is organized
67,108,864 x 64 bits in a 168 pin dual in line memory module (DIMM). The 64M x 64 unbuffered
DIMM uses 16 Mosel-Vitelic 32M x 8 SDRAM. The
x64 modules are ideal for use in high performance
computer systems where increased memory density and fast access times are required.
Part Number
Speed
Grade
Configuration
V436664S24VXTG-75PC
-75PC, CL=2,3
(133 MHz)
64M x 64
V436664S24VXTG-75
-75, CL=3
(133 MHz)
64M x 64
V436664S24VXTG-10PC
-10PC, CL=2,3
(100 MHz)
64M x 64
V436664S24V Rev. 1.1 March 2002
1
V436664S24V
MOSEL VITELIC
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO*
CB1*
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2*
CB3*
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4*
CB5*
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
A12
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6*
CB7*
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Notes:
*
These pins are not used in this module.
Pin Names
A0–A12
Address Inputs
I/O1–I/O64
Data Inputs/Outputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
BA0, BA1
SDA
Serial Data OUT for Presence
Detect
SA0–A2
Serial Data IN for Presence
Detect
Read/Write Input
CB0–CB7
Check Bits (x72 Organization)
Bank Selects
NC
No Connection
CKE0, CKE1
Clock Enable
DU
Don’t Use
CS0–CS3
Chip Select
CLK0–CLK3
Clock Input
DQM0–DQM7
Data Mask
VCC
Power (+3.3 Volts)
VSS
Ground
SCL
Clock for Presence Detect
V436664S24V Rev. 1.1 March 2002
2
V436664S24V
MOSEL VITELIC
Module Part Number Information
V
4
3
66
64
S
2
4
V
X
T
G - XX
SPEED
75PC = PC133 CL3,2
75 = PC133 CL3
10PC = PC133 CL3,2
LEAD FINISH
G = GOLD
MOSEL VITELIC
MANUFACTURED
SDRAM
3.3V
COMPONENT
PACKAGE, T = TSOP
WIDTH
DEPTH
COMPONENT A=0.17u B=0.14u
REV LEVEL
168 PIN Unbuffered
DIMM X8 COMPONENT
LVTTL
REFRESH
RATE 8K
4 BANKS
Block Diagram
CS1
CS0
DQM0
I/O1–I/O8
DQM CS
I/O1–I/O8 D0
DQM CS
I/O1–I/O8 D8
DQM CS
I/O1–I/O8 D1
DQM CS
I/O1–I/O8 D9
DQM4
I/O33–I/O40
10Ω
DQM1
I/O9–I/O16
DQM CS
I/O1–I/O8 D4
DQM CS
I/O1–I/O8 D12
DQM CS
I/O1–I/O8 D5
DQM CS
I/O1–I/O8 D13
CS
DQM
I/O1–I/O8 D6
CS
DQM
I/O1–I/O8 D14
CS
DQM
I/O1–I/O8 D7
CS
DQM
I/O1–I/O8 D15
10Ω
DQM5
I/O41–I/O48
10Ω
10Ω
CS3
CS2
CS
DQM
I/O1–I/O8 D2
DQM2
I/O17–I/O24
CS
DQM
I/O1–I/O8 D10
DQM6
I/O49–I/O56
10Ω
10Ω
CS
DQM3
I/O25–I/O32
DQM
I/O1–I/O8
CS
DQM
I/O1–I/O8 D11
D3
DQM7
I/O57–I/O64
10Ω
10Ω
E2PROM SPD (256 WORD X 8 BIT)
SA0
SA1
SA2
SCL
SA0
SA1
SA2
SCL
A12-A0, BA0, BA1
D0-D15
VDD
VSS
D0-D15
C0-C31 ,C32-C42
D0-D7
RAS, CAS, WE
D0-D15
SDA
WP
47K
D0-D7
CKE0
VCC
10K
CKE1
CLOCK WIRING
16M X 64
CLK0
CLK1
CLK2
CLK3
V436664S24V Rev. 1.1 March 2002
4 SDRAM +3.3pF
4 SDRAM +3.3pF
4 SDRAM +3.3pF
4 SDRAM +3.3pF
3
D9-D15
V436664S24V
MOSEL VITELIC
Serial Presence Detect Information
written into the E2PROM device during module production using a serial presence detect protocol (I2C
synchronous 2-wire bus)
A serial presence detect storage device –
– is assembled onto the module. Information about the module configuration, speed, etc. is
E2PROM
SPD-Table :
Byte Number
Function Described
Hex Value
SPD Entry Value
-75PC
-75
-10PC
0
Number of SPD bytes
128
80
80
80
1
Total bytes in Serial PD
256
08
08
08
2
Memory Type
SDRAM
04
04
04
3
Number of Row Addresses (without BS bits)
13
0D
0D
0D
4
Number of Column Addresses (for x8
SDRAM)
10
0A
0A
09
5
Number of DIMM Banks
2
02
02
02
6
Module Data Width
64
40
40
40
7
Module Data Width (continued)
0
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
9
SDRAM Cycle Time at CL=3
7.5 ns/10.0 ns
75
75
A0
10
SDRAM Access Time from Clock at CL=3
5.4 ns/6.0 ns
54
54
60
11
Dimm Config (Error Det/Corr.)
none
00
00
00
12
Refresh Rate/Type
Self-Refresh, 7.8µs
82
82
82
13
SDRAM width, Primary
x8
08
08
08
14
Error Checking SDRAM Data Width
n/a / x8
00
00
00
15
Minimum Clock Delay from Back to Back
Random Column Address
tccd = 1 CLK
01
01
01
16
Burst Length Supported
1, 2, 4, 8
0F
0F
0F
17
Number of SDRAM Banks
4
04
04
04
18
Supported CAS Latencies
CL = 3, 2
06
06
06
19
CS Latencies
CS Latency = 0
01
01
01
20
WE Latencies
WL = 0
01
01
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
00
00
22
SDRAM Device Attributes: General
Vcc tol ± 10%
0E
0E
0E
23
Minimum Clock Cycle Time at CAS Latency
=2
7.5ns/10.0 ns
75
A0
A0
24
Maximum Data Access Time from Clock for
CL = 2
5.4ns/6.0 ns
54
60
60
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
00
00
26
Maximum Data Access Time from Clock at
CL = 1
Not Supported
00
00
00
27
Minimum Row Precharge Time
15 ns/20 ns
0F
14
14
V436664S24V Rev. 1.1 March 2002
4
V436664S24V
MOSEL VITELIC
SPD-Table : (Continued)
Byte Number
Function Described
Hex Value
SPD Entry Value
-75PC
-75
-10PC
14 ns/15 ns/16 ns
0E
0F
10
28
Minimum Row Active to Row Active Delay
tRRD
29
Minimum RAS to CAS Delay tRCD
15 ns/20 ns
0F
14
14
30
Minimum RAS Pulse Width tRAS
42 ns/45 ns
2A
2D
2D
31
Module Bank Density (Per Bank)
256 MByte
40
40
40
32
SDRAM Input Setup Time
1.5 ns/2.0 ns
15
15
20
33
SDRAM Input Hold Time
0.8 ns/1.0 ns
08
08
10
34
SDRAM Data Input Setup Time
1.5 ns/2.0 ns
15
15
20
35
SDRAM Data Input Hold Time
0.8 ns/1.0 ns
08
08
10
00
00
00
02
02
12
FE
43
B1
40
40
40
00
00
00
36-61
Superset Information (May be used in Future)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65-71
72
Revision 2/1.2
Mosel Vitelic
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
73-90
Module Part Number (ASCII)
91-92
PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
V436664S24V
95-98
Assembly Serial Number
99-125
Reserved
00
00
00
126
Intel Specification for Frequency
64
64
64
127
Reserved
00
00
00
128+
Unused Storage Location
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Limit Values
Symbol
Parameter
Min.
Max.
Unit
VIH
Input High Voltage
2.0
VCC +0.3
V
VIL
Input Low Voltage
–0.5
0.8
V
V OH
Output High Voltage (IOUT = –2.0 mA)
2.4
—
V
V436664S24V Rev. 1.1 March 2002
5
V436664S24V
MOSEL VITELIC
Limit Values
Symbol
Parameter
Min.
Max.
Unit
VOL
Output Low Voltage (IOUT = 2.0 mA)
—
0.4
V
II(L)
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V)
–10
10
µA
IO(L)
Output leakage current
(DQ is disabled, 0V < VOUT < VCC)
–10
10
µA
Capacitance
TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz
Symbol
Parameter
Limit Values
Unit
CI1
Input Capacitance (A0 to A11, RAS, CAS, WE)
85
pF
CI2
Input Capacitance (CS0-CS3)
30
pF
CICL
Input Capacitance (CLK0-CLK3)
22
pF
CI3
Input Capacitance (CKE0, CKE1)
50
pF
CI4
Input Capacitance (DQM0-DQM7)
20
pF
CIO
Input/Output Capacitance (I/O1-I/064)
20
pF
CSC
Input Capacitance (SCL, SA0-2)
8
pF
CSD
Input/Output Capacitance
18
pF
V436664S24V Rev. 1.1 March 2002
6
V436664S24V
MOSEL VITELIC
Absolute Maximum Ratings
Parameter
Max.
Units
Voltage on VDD Supply Relative to V SS
-1 to 4.6
V
Voltage on Input Relative to VSS
-1 to 4.6
V
Operating Temperature
0 to +70
°C
-55 to 125
°C
13
W
Storage Temperature
Power Dissipation
Standby and Refresh Currents1
TA = 0°C to 70°C, VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
ICC1
Operating Current
Burst length = 4, CL = 3
tRC > = tRC(min),
tCK> = tCK(min), IO = 0 mA
2 Bank Interleave Operation
ICC2P
Precharged Standby Current in
Power Down Mode
Precharged Standby Current in
Non-Power Down Mode
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
Active Standby Current in Power
Down Mode
-75PC/75
-10PC
Unit
Note
1840
1680
mA
1,2
CKE< = VIL(max), tCK> = tCK(min)
32
32
mA
CKE< = VIL(max), tCK = Infinite
16
16
mA
CKE> = VIH(min), tCK> = tCK(min), Input changed once in 3 cycles
360
280
mA
CKE> = VIH(min), tCK = Infinite,
No Input change
40
40
mA
CKE< = VIL(max), tCK> = tCK(min)
160
160
mA
CKE< = VIL(max), tCK = Infinite
32
32
mA
440
360
mA
CKE> = VIH(min), tCK = Infinite,
No Input change
200
200
mA
Active Standby Current in Non-Pow- CKE> = VIH(min), tCK> = tCK(min), Iner Down Mode
put changed one time
ICC3NS
CS =
High
CS =
High
ICC4
Burst Operating Current
Burst length = Full Page,
tRC = Infinite, CL = 3,
tCK> = tCK(min), IO = 0 mA
2 Banks Activated
1200
960
mA
1, 2
ICC5
Auto Refresh Current
tRC >= tRC (min)
3840
3520
mA
1,2
ICC6
Self Refresh Current
CKE = <0,2 V
48
48
mA
V436664S24V Rev. 1.1 March 2002
7
V436664S24V
MOSEL VITELIC
AC Characteristics 3,4
TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns
Limit Values
-75PC
# Symbol Parameter
Min.
-75
Max.
Min.
-10PC
Max.
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
tCK
fCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
7.5
System frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
133
–
–
133
100
–
–
100
100
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
7.5
10
10
10
ns
ns
4,5
4
tCH
Clock High Pulse Width
2.5
–
2.5
–
3
–
ns
6
5
tCL
Clock Low Pulse Width
2.5
–
2.5
–
3
–
ns
6
6
tCS
Input Setup time
1.5
–
1.5
–
2
–
ns
7
7
tCH
Input Hold Time
0.8
–
0.8
–
1
–
ns
7
8
tCKSP
CKE Setup Time (Power down mode)
2.5
–
2
–
2
–
ns
8
9
tCKSR
CKE Setup Time (Self Refresh Exit)
8
–
8
–
8
–
ns
9
10
tT
0.3
1.2
1
–
1
–
ns
RAS to CAS delay
15
–
20
–
20
–
ns
Transition time (rise and fall)
Common Parameters
11
tRCD
12
tRC
Cycle Time
60
–
70
120k
70
120k
ns
13
tRAS
Active Command Period
42
–
45
–
45
–
ns
14
tRP
Precharge Time
20
–
20
–
20
–
ns
15
tRRD
Bank to Bank Delay Time
14
–
15
–
20
–
ns
16
tCCD
CAS to CAS delay time (same bank)
1
–
1
–
1
–
CLK
Refresh Cycle
17
tSREX
Self Refresh Exit Time
10
–
10
–
10
–
ns
9
18
tREF
Refresh Period (8192 cycles)
64
–
64
–
64
–
ms
8
2.7
–
3
–
3
–
ns
4
Read Cycle
19
tOH
Data Out Hold Time
20
tLZ
Data Out to Low Impedance Time
1
–
0
–
0
–
ns
21
tHZ
Data Out to High Impedance Time
3
7.5
3
7.5
3
8
ns
22
tDQZ
DQM Data Out Disable Latency
2
–
2
–
2
–
CLK
10
Write Cycle
23
tDPL
Data input to Precharge (write recovery)
2
–
2
–
1
–
CLK
24
tDAL
Data In to Active/refresh
5
–
5
–
5
–
CLK
25
tDQW
DQM Write Mask Latency
0
–
0
–
0
–
CLK
V436664S24V Rev. 1.1 March 2002
8
11
V436664S24V
MOSEL VITELIC
Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No
Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
CLOCK
50 Ohm
0.4V
tCL
tSETUP
Z=50 Ohm
tT
I/O
tHOLD
50 pF
1.4V
INPUT
tAC
tAC
tLZ
I/O
tOH
50 pF
1.4V
OUTPUT
Measurement conditions for
tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
tDAL is equivalent to tDPL + tRP.
V436664S24V Rev. 1.1 March 2002
9
V436664S24V
MOSEL VITELIC
Package Diagram
L-DIM-168-30
SDRAM DIMM Module Package
All measurements in mm
133.37
127.35
17.80
35.00
(4.0 max)
10
11
40
41
84
3.0
1
42.18
1.27 ± 0.100
63.68
A
94
95
124
125
168
4.0
85
B
D
6.35
2.50
2.0
4.45
Detail B
2.26
RADIUS
1.27 + 0.10
Tolerances: ± (0.13) unless otherwise specified.
V436664S24V Rev. 1.1 March 2002
0.2 ± 0.15
2.0
3.175
Detail A
1.0 ± 0.05
1.27
3.125
3.125
6.35
10
Detail C
V436664S24V
MOSEL VITELIC
Label Information
Module Density
MOSEL VITELIC
Part Number
Criteria of PC100 or PC133
(refer to MVI datasheet)
DIMM manufacture date code
V436664S24VXXX-XX 512MB CLX
PC133U-XXX-542-A
XXXX-XXXXXXX
Assembly in Taiwan
PC133 U -XXX
UNBUFFERED DIMM
A
Gerber file Intel PC100 x8 Based
CL= 3 or 2 (CLK)
tRCD= 3 or 2 (CLK)
tRP= 3 or 2 (CLK)
V436664S24V Rev. 1.1 March 2002
54 2
CAS Latency
2=CL2
3=CL3
JEDEC SPD Revision 2
tAC = 5.4 ns
11
V436664S24V
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