MOSEL VITELIC V4374128C24V 1GB 168-PIN REGISTERED PLL ECC SDRAM DIMM 3.3 VOLT 128M x 72 PRELIMINARY Features Description ■ 168 Pin Registered ECC 134,217,728 x 72 bit Oganization SDRAM Modules ■ Utilizes High Performance 64M x 4 SDRAM in SOC Packages ■ Fully PC Board Layout Compatible to INTEL’S Rev 1.2 Module Specification ■ Single +3.3V (± 0.3V) Power Supply ■ Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) ■ Auto Refresh (CBR) and Self Refresh ■ All Inputs, Outputs are LVTTL Compatible ■ 8192 Refresh Cycles every 64 ms ■ Serial Presence Detect (SPD) ■ The V4374128C24V memory module is organized 134,217,728 x 72 bits in a 168 pin dual in line memory module (DIMM). The 128M x 72 registered DIMM uses 36 Mosel-Vitelic 64M x 4 ECC SDRAM. The x72 registered modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Part Number Speed Grade V4374128C24VXXG-75PC -75PC, CL=2,3 (133 MHz) V4374128C24VXXG-75 -75, CL=3 (133 MHz) V4374128C24VXXG-10PC -10PC, CL=2,3 (100 MHz) V4374128C24V Rev. 1.1 January 2002 Configuration 128M x 72 128M x 72 128M x 72 1 MOSEL VITELIC V4374128C24V Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO CB1 VSS NC NC VCC WE DQM0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2 CB3 VSS I/O17 I/O18 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 I/O19 I/O20 VCC I/O21 NC DU CKE1* VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2* NC WP SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4 CB5 VSS NC NC VCC CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1* A12 VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6 CB7 VSS I/O49 I/O50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 I/O51 I/O52 VCC I/O53 NC DU REGE VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3* NC SA0 SA1 SA2 VCC Notes: * These pins are not used in this module. Pin Names A0–A12 Address Inputs I/O1–I/O64 Data Inputs/Outputs RAS Row Address Strobe CAS Column Address Strobe WE BA0, BA1 SDA Serial Data OUT for Presence Detect SA0–A2 Serial Data IN for Presence Detect Read/Write Input CB0–CB4 Check Bits (x72 Organization) Bank Selects NC No Connection CKE0 Clock Enable REGE Register Enable CS0, CS2 Chip Select DU Don’t Use CLK0–CLK3 Clock Input DQM0–DQM7 Data Mask VCC Power (+3.3 Volts) VSS Ground SCL Clock for Presence Detect V4374128C24V Rev. 1.1 January 2002 2 MOSEL VITELIC V4374128C24V Module Part Number Information V 4 3 74 128 C 2 4 V X SDRAM 3.3V G - XX COMPONENT PACKAGE S=SOC WIDTH DEPTH COMPONENT A=0.17um REV LEVEL B=0.14um 168 PIN Registered DIMM X4 COMPONENT LVTTL REFRESH RATE 8K V4374128C24V Rev. 1.1 January 2002 X SPEED 75PC = PC133 CL3,2 75 = PC133 CL3 10PC = PC133 CL3,2 LEAD FINISH G = GOLD MOSEL VITELIC MANUFACTURED 3 4 BANKS MOSEL VITELIC V4374128C24V Block Diagram RS0 RS1 RDQMB0 RDQMB4 DQ0 DQ1 DQ2 DQ3 DQM CS DQ0 DQ1 U11 DQ2 DQ3 DQM CS DQ0 DQ1 U29 DQ2 DQ3 DQ32 DQ33 DQ34 DQ35 DQM CS DQ0 DQ1 U1 DQ2 DQ3 DQM CS DQ0 DQ1 U19 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 U12 DQ2 DQ3 DQM CS DQ0 DQ1 U30 DQ2 DQ3 DQ36 DQ37 DQ38 DQ39 DQM CS DQ0 DQ1 U2 DQ2 DQ3 DQM CS DQ0 DQ1 U20 DQ2 DQ3 DQ8 DQ9 DQ10 DQ11 DQM CS DQ0 DQ1 U13 DQ2 DQ3 DQM CS DQ0 DQ1 U31 DQ2 DQ3 DQ40 DQ41 DQ42 DQ43 DQM CS DQ0 DQ1 U3 DQ2 DQ3 DQM CS DQ0 DQ1 U21 DQ2 DQ3 DQ12 DQ13 DQ14 DQ15 DQM CS DQ0 DQ1 U14 DQ2 DQ3 DQM CS DQ0 DQ1 U32 DQ2 DQ3 DQ44 DQ45 DQ46 DQ47 DQM CS DQ0 DQ1 U4 DQ2 DQ3 DQM CS DQ0 DQ1 U22 DQ2 DQ3 CB0 CB1 CB2 CB3 DQM CS DQ0 DQ1 U5 DQ2 DQ3 DQM CS DQ0 DQ1 U23 DQ2 DQ3 CB4 CB5 CB6 CB7 DQM DQ0 DQ1 U6 DQ2 DQ3 CS DQM DQ0 DQ1 U24 DQ2 DQ3 CS DQ16 DQ17 DQ18 DQ19 DQM CS DQ0 DQ1 U15 DQ2 DQ3 DQM CS DQ0 DQ1 U33 DQ2 DQ3 DQ48 DQ49 DQ50 DQ51 DQM CS DQ0 DQ1 U7 DQ2 DQ3 DQM CS DQ0 DQ1 U25 DQ2 DQ3 DQ20 DQ21 DQ22 DQ23 DQM CS DQ0 DQ1 U16 DQ2 DQ3 DQM CS DQ0 DQ1 U34 DQ2 DQ3 DQ52 DQ53 DQ54 DQ55 DQM CS DQ0 DQ1 U8 DQ2 DQ3 DQM CS DQ0 DQ1 U26 DQ2 DQ3 DQ24 DQ25 DQ26 DQ27 DQM CS DQ0 DQ1 U17 DQ2 DQ3 DQM CS DQ0 DQ1 U35 DQ2 DQ3 DQ56 DQ57 DQ58 DQ59 DQM CS DQ0 DQ1 U9 DQ2 DQ3 DQM CS DQ0 DQ1 U27 DQ2 DQ3 DQ28 DQ29 DQ30 DQ31 DQM CS DQ0 DQ1 U18 DQ2 DQ3 DQM CS DQ0 DQ1 U36 DQ2 DQ3 DQ60 DQ61 DQ62 DQ63 DQM CS DQ0 DQ1 U10 DQ2 DQ3 DQM CS DQ0 DQ1 U28 DQ2 DQ3 RDQMB1 RDQMB5 RS2 RS3 RDQMB2 RDQMB6 RDQMB3 RDQMB7 U37, U38, U40 RAS CAS CKEO WE A0-A11 A0-A12 BA0 BA1 S0-S3 DQMB0 - DQMB7 10K Vcc REGE PLL CLK R E RRAS: SDRAMs U1-U36 RCAS: SDRAMs U1-U36 RCKE0: SDRAMs U1-U36 RWE: SDRAMs U1-U36 RA0-RA11: SDRAMs U1-U36 RA0-RA12: SDRAMs U1-U36 RBA0: SDRAMs U1-U36 RBA1: SDRAMs U1-U36 RS0-RS3 RDQMB0 - RDQMB7 G I S T E R S U41 SCL WP 47K SPD U42 A0 A1 A2 PLL 12pF CK1-CK3 12pF Vcc SDRAMs U0-U35 Vss SDRAMs U0-U35 U1-U36 = MT48BLC32M4A2F SDRAMs (512MB) U1-U36 = MT48BLC64M4A2F SDRAMs (1GB) SA0 SA1 SA2 NOTE: 1. All resistor values are 10 ohms unless otherwise specified V4374128C24V Rev. 1.1 January 2002 U39 CK0 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 REGISTER x 3 4 MOSEL VITELIC V4374128C24V Serial Presence Detect Information written into the E2PROM device during module production using a serial presence detect protocol (I 2C synchronous 2-wire bus) A serial presence detect storage device – – is assembled onto the module. Information about the module configuration, speed, etc. is E2PROM SPD-Table: Byte Number Function Described Hex Value SPD Entry Value -75PC -75 -10PC 0 Number of SPD bytes 128 80 80 80 1 Total bytes in Serial PD 256 08 08 08 2 Memory Type SDRAM 04 04 04 3 Number of Row Addresses (without BS bits) 13 0D 0D 0D 4 Number of Column Addresses (for x8 SDRAM) 11 0B 0B 0B 5 Number of DIMM Banks 2 02 02 02 6 Module Data Width 72 48 48 48 7 Module Data Width (continued) 0 00 00 00 8 Module Interface Levels LVTTL 01 01 01 9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0 10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 54 54 60 11 Dimm Config (Error Det/Corr.) ECC 02 02 02 12 Refresh Rate/Type Self-Refresh, 7.8µs 82 82 82 13 SDRAM width, Primary x4 04 04 04 14 Error Checking SDRAM Data Width n/a / x4 04 04 04 15 Minimum Clock Delay from Back to Back Random Column Address tccd = 1 CLK 01 01 01 16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F 17 Number of SDRAM Banks 4 04 04 04 18 Supported CAS Latencies CL =2, 3 06 06 06 19 CS Latencies CS Latency = 0 01 01 01 20 WE Latencies WL = 0 01 01 01 21 SDRAM DIMM Module Attributes Registered/Buffered 1F 1F 1F 22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E 23 Minimum Clock Cycle Time at CAS Latency =2 7.5 ns/10.0 ns 75 A0 A0 24 Maximum Data Access Time from Clock for CL = 2 5.4 ns/6.0 ns 54 60 60 25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00 26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00 00 00 27 Minimum Row Precharge Time 15 ns/20 ns 0F 14 14 V4374128C24V Rev. 1.1 January 2002 5 MOSEL VITELIC V4374128C24V SPD-Table: (Continued) Byte Number Function Described Hex Value SPD Entry Value -75PC -75 -10PC 14 ns/15 ns/16 ns 0F 0F 0F 28 Minimum Row Active to Row Active Delay tRRD 29 Minimum RAS to CAS Delay tRCD 15 ns/20 ns 0F 14 14 30 Minimum RAS Pulse Width tRAS 42 ns/45 ns 2A 2D 2D 31 Module Bank Density (Per Bank) 512 MByte 80 80 80 32 SDRAM Input Setup Time 1.5 ns/2.0 ns 15 15 20 33 SDRAM Input Hold Time 0.8 ns/1.0 ns 08 08 10 34 SDRAM Data Input Setup Time 1.5 ns/2.0 ns 15 15 20 35 SDRAM Data Input Hold Time 0.8 ns/1.0 ns 08 08 10 00 00 00 02 02 12 69 AD 1A 40 40 40 00 00 00 36-61 Superset Information (May be used in Future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 64 Manufacturer’s JEDEC ID Code 65-71 72 Revision 2/1.2 Mosel Vitelic Manufacturer’s JEDEC ID Code (cont.) Manufacturing Location 73-90 Module Part Number (ASCII) 91-92 PCB Identification Code 93 Assembly Manufacturing Date (Year) 94 Assembly Manufacturing Date (Week) V4374128C24V 95-98 Assembly Serial Number 99-125 Reserved 00 00 00 126 Intel Specification for Frequency 64 64 64 127 Reserved 8D 8D 8D Unused Storage Location 00 00 00 128+ V4374128C24V Rev. 1.1 January 2002 6 MOSEL VITELIC V4374128C24V DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Limit Values Symbol Parameter Min. Max. Unit VIH Input High Voltage 2.0 VCC +0.3 V V IL Input Low Voltage –0.3 0.8 V V OH Output High Voltage (IOUT = –4.0 mA) 2.4 — V V OL Output Low Voltage (IOUT = 4.0 mA) — 0.4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –10 10 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT < V CC) –10 10 µA Capacitance TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz Symbol Parameter Limit Values Unit CI1 Input Capacitance (A0 to A11, RAS, CAS, WE) 15 pF CI2 Input Capacitance (CS0-CS3) 15 pF CICL Input Capacitance (CLK0) 20 pF CI3 Input Capacitance (CKE0) 15 pF CI4 Input Capacitance (DQM0-DQM7) 15 pF CIO Input/Output Capacitance (I/O1-I/064) 16 pF CSC Input Capacitance (SCL, SA0-2) 8 pF CSD Input/Output Capacitance 18 pF V4374128C24V Rev. 1.1 January 2002 7 MOSEL VITELIC V4374128C24V Absolute Maximum Ratings Parameter Max. Units Voltage on VDD Supply Relative to VSS -1 to 4.6 V Voltage on Input Relative to V SS -1 to 4.6 V Operating Temperature 0 to +70 °C -55 to 125 °C 29 W Storage Temperature Power Dissipation Standby and Refresh Currents1 TA = 0°C to 70°C, VCC = 3.3V ± 0.3V Symbol Parameter Test Conditions -75PC/75 -10PC Unit Note ICC 1 Operating Current Burst length = 4, CL = 3 tRC > = tRC(min), tCK> = tCK(min), IO = 0 mA 2 Bank Interleave Operation 4200 3780 mA 1,2 ICC 2P Precharged Standby Current in Power Down Mode CKE< = VIL(max), tCK> = tCK(min) 72 72 mA ICC 2N Precharged Standby Current in Non-Power Down Mode CKE> = V IH(min), tCK> = tCK(min), Input changed once in 3 cycles 720 630 mA ICC 3P Active Standby Current in Power Down Mode CKE< = VIL(max), tCK> = tCK(min) 360 360 mA ICC 3N Active Standby Current in Non-Pow- CKE> = V IH(min), tCK> = tCK(min), Iner Down Mode put changed one time 900 810 mA CS = High ICC 4 Burst Operating Current tRC = Infinite, CL = 3, tCK> = tCK(min), IO = 0 mA 2 Banks Activated 2700 1920 mA 1, 2 ICC 5 Auto Refresh Current tRC >= tRC (min) 8640 7920 mA 1,2 ICC 6 Self Refresh Current CKE = <0,2 V Standard 108 108 mA 1,2 L-version 62 62 V4374128C24V Rev. 1.1 January 2002 8 CS = High MOSEL VITELIC V4374128C24V AC Characteristics 3,4 TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns Limit Values -75PC # Symbol Parameter Min. -75 Max. Min. -10PC Max. Min. Max. Unit Note Clock and Clock Enable 1 2 3 tCK fCK tAC Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 7.5 System frequency CAS Latency = 3 CAS Latency = 2 – – 133 133 – – 133 100 – – 100 100 MHz MHz Clock Access Time CAS Latency = 3 CAS Latency = 2 – – 5.4 6 – – 5.4 6 – – 6 6 ns ns 7.5 10 10 10 ns ns 4,5 4 tCH Clock High Pulse Width 2.5 – 2.5 – 3 – ns 6 5 tCL Clock Low Pulse Width 2.5 – 2.5 – 3 – ns 6 6 tCS Input Setup time 1.5 – 1.5 – 2 – ns 7 7 tCH Input Hold Time 0.8 – 0.8 – 1 – ns 7 8 tCKSP CKE Setup Time (Power down mode) 2.5 – 2.5 – 2 – ns 8 9 tCKSR CKE Setup Time (Self Refresh Exit) 8 – 8 – 8 – ns 9 10 tT Transition time (rise and fall) 1 – 1 – 1 – ns RAS to CAS delay 15 – 20 – 20 – ns 6 Common Parameters 11 tRCD 12 tRC Cycle Time 70 120K 70 120K 60 120K ns 6 13 tRAS Active Command Period 42 – 45 – 45 – ns 6 14 tRP Precharge Time 15 – 20 – 20 – ns 6 15 tRRD Bank to Bank Delay Time 14 – 15 – 20 – ns 6 16 tCCD CAS to CAS delay time (same bank) 1 – 1 – 1 – CLK Refresh Cycle 17 tSREX Self Refresh Exit Time 10 – 10 – 10 – ns 18 tREF Refresh Period (8192 cycles) 64 – 64 – 64 – ms Read Cycle 19 tOH Data Out Hold Time 3 – 3 – 3 – ns 20 tLZ Data Out to Low Impedance Time 1 – 1 – 1 – ns 21 tHZ Data Out to High Impedance Time 3 7.5 3 7.5 3 8 ns 22 tDQZ DQM Data Out Disable Latency – 2 – 2 – 2 CLK Write Cycle 23 tDPL Data input to Precharge (write recovery) 2 – 2 – 1 – CLK 24 tDQW DQM Write Mask Latency 0 – 0 – 0 – CLK V4374128C24V Rev. 1.1 January 2002 9 2 7 MOSEL VITELIC V4374128C24V Notes: 1. The specified values are valid when addresses are changed no more than once during t CK(min.) and when No Operation commands are registered on every rising clock edge during t RC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during t RC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. + 1.4 V tCH 2.4V CLOCK 50 Ohm 0.4V tCL tSETUP Z=50 Ohm tT I/O tHOLD 50 pF 1.4V INPUT tAC tAC tLZ I/O tOH 50 pF 1.4V OUTPUT Measurement conditions for tac and toh tHZ 5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to t DPL + tRP. V4374128C24V Rev. 1.1 January 2002 10 MOSEL VITELIC V4374128C24V Package Diagram SDRAM DIMM Module Package FRONT VIEW .157 (3.99) MAX 5.256 (133.50) 5.244 (133.20) 1.705 (43.31) .079 (2.00) R (2X) 1.695 (43.05) .118 (3.00) R (2X) .700 (17.78) TYP. .118 (3.00) TYP. .054 (1.37) .250 (6.35) TYP. .118 (3.00) TYP. .039 (1.00) R(2X) PIN 1 .040 (1.02) TYP. 4.550 (115.57) .046 (1.17) PIN 84 .050 (1.27) TYP. BACK VIEW .128 (3.25) .118 (3.00) 1.661 (42.18) PIN 168 2.625 (66.68) PIN 85 NOTE: All dimensions in inches (millimeters) V4374128C24V Rev. 1.1 January 2002 MAX or typical where noted. MIN 11 (2X) MOSEL VITELIC V4374128C24V Label Information Module Density MOSEL VITELIC Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) DIMM manufacture date code V4374128C24VXXX-XX PC133R-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan PC133 R -XXX REGISTERED DIMM CAS Latency 2=CL2 3=CL3 A Gerber file Intel PC100 x4 Based CL= 3 or 2 (CLK) tRCD= 3 or 2 (CLK) tRP= 3 or 2 (CLK) V4374128C24V Rev. 1.1 January 2002 54 2 1GB CLX JEDEC SPD Revision 2 tAC = 5.4 ns 12 MOSEL VITELIC V4374128C24V WORLDWIDE OFFICES U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. 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MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. V4374128C24V Rev. 1.1 January 2002 13