MOSEL V53C316405A

MOSEL VITELIC
V53C316405A
3.3 VOLT 4M x 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C316405A
50
60
Max. RAS Access Time, (tRAC)
50 ns
60 ns
Max. Column Address Access Time, (tCAA)
25 ns
30 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC)
20 ns
25 ns
Min. Read/Write Cycle Time, (tRC)
84 ns
104 ns
Features
Description
■ 4M x 4-bit organization
■ EDO Page Mode for a sustained data rate
of 50 MHz
■ RAS access time: 50, 60 ns
■ Low power dissipation
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh and Hidden Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
■ Single +3.3V ± 0.3V Power Supply
■ TTL Interface
The V53C316405A is a 4,194,304 x 4 bit highperformance CMOS dynamic random access memory. The V53C316405A offers Page mode operation with Extended Data Output. The V53C316405A
has asymmetric address, 12-bit row and 10-bit column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 4 bits,
within a page, with cycle times as short as 20ns.
These features make the V53C316405A ideally
suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
K
T
50
60
Std.
Temperature
Mark
•
•
•
•
•
Blank
0°C to 70°C
V53C316405A Rev. 1.2 March 1998
1
Power
V53C316405A
MOSEL VITELIC
24/26-Pin Plastic SOJ/TSOP-II
PIN CONFIGURATION
Top View
VCC
I/O1
I/O2
WE
RAS
A11
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
A9
A10
A0
A1
A2
A3
VCC
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
311640500-02
Pin Names
V53C316405A Rev. 1.2 March 1998
A0–A11
Row, Column Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O1–I/O4
Data Input, Output
VCC
+3.3V Supply
VSS
0V Supply
NC
No Connect
2
V53C316405A
MOSEL VITELIC
Absolute Maximum Ratings*
Capacitance*
Operating temperature range ..................0 to 70 °C
Storage temperature range ............... -55 to 150 °C
Input/output voltage .... -0.5 to min (VCC+0.5, 4.6) V
Power supply voltage .......................... -1.0 to 4.6 V
Power dissipation .......................................... 0.5 W
Data out current (short circuit) ...................... 50 mA
TA = 25°C, VCC = 3.3 V ± 0.3V, VSS = 0 V
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Symbol
Parameter
Typ.
Max.
Unit
CIN1
Address Input
—
5
pF
CIN2
RAS, CAS, WE, OE
—
7
pF
COUT
Data Input/Output
—
7
pF
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
4096 x 4
I/O1 I/O2 I/O3 I/O4
Data In
Buffer
Data Out
Buffer
OE
4
WE
CAS
4
No. 2 Clock
Generator
10
A0
A1
A2
A3
RAS
10
Sense Amplifier
I/O Gating
Refresh
Counter (12)
4
1024
x4
12
12
Row
Address
Buffers (11)
12
Row
Decoder 4096
Memory Array
4096 x 1024 x 4
No. 1 Clock
Generator
Voltage Down
Generator
V53C316405A Rev. 1.2 March 1998
Column
Decoder
Refresh
Controller
A4
A5
A6
A7
A8
A9
A10
A11
Column
Address
Buffers (10)
3
VCC
311640502-04
VCC (internal)
V53C316405A
MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 3.3 V ± 0.3V, VSS = 0 V, VT = 2ns unless otherwise specified.
Symbol
Parameter
ILI
Input Leakage Current
(any input pin)
ILO
Output Leakage Current
(for High-Z State)
ICC1
VCC Supply Current,
Operating
Access
Time
V53C316405A
Min.
Typ.
Max.
Unit
Test Conditions
Notes
–10
10
µA
VSS ≤ VIN ≤ VCC+0.3V
1
–10
10
µA
VSS ≤ VOUT ≤
VCC+0.3V
RAS, CAS at VIH
1
50
50
mA
tRC = tRC (min.)
60
40
2
mA
RAS, CAS at VIH
other inputs ≥ VSS
mA
tRC = tRC (min.)
2, 4
mA
Minimum Cycle
2, 3, 4
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
50
50
60
40
VCC Supply Current,
EDO Page Mode Operation
50
35
60
30
VCC Supply Current,
during CAS-before-RAS Refresh
50
50
60
40
ICC4
ICC5
ICC6
VCC Supply Current,
CMOS Standby
VCC
Power Supply Voltage
3.0
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
TTL Output Low Voltage
VOH
TTL Output High Voltage
VOL
CMOS Output Low Voltage
VOH
CMOS Output High Voltage
V53C316405A Rev. 1.2 March 1998
mA
2, 3, 4
2, 4
RAS ≥ VCC – 0.2 V,
CAS ≥ VCC – 0.2 V,
other input pins ≥ VSS
1.0
mA
3.6
V
–0.5
0.8
V
1
2.0
VCC + 0.5
V
1
0.4
V
IOL = 2 mA
1
V
IOH = –2 mA
1
0.2
V
IOL = 100 µA
1
VCC – 0.2
V
IOH = –100 µA
1
3.3
2.4
4
1
V53C316405A
MOSEL VITELIC
AC Characteristics(5,6)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V, tT = 2 ns
-50
#
Symbol
Parameter
-60
min.
max.
min.
max.
Unit
Note
Common Parameters
1
tRC
Random read or write cycle time
84
–
104
–
ns
2
tRP
RAS precharge time
30
–
40
–
ns
3
tRAS
RAS pulse width
50
10k
60
10k
ns
4
tCAS
CAS pulse width
8
10k
10
10k
ns
5
tASR
Row address setup time
0
–
0
–
ns
6
tRAH
Row address hold time
8
–
10
–
ns
7
tASC
Column address setup time
0
–
0
–
ns
8
tCAH
Column address hold time
8
–
10
–
ns
9
tRCD
RAS to CAS delay time
12
37
14
45
ns
10
tRAD
RAS to column address delay
10
25
12
30
ns
11
tRSH
RAS hold time
13
15
–
ns
12
tCSH
CAS hold time
40
50
–
ns
13
tCRP
CAS to RAS precharge time
5
–
5
–
ns
14
tT
Transition time (rise and fall)
1
50
1
50
ns
15
tREF
Refresh period
–
64
–
64
ms
7
Read Cycle
16
tRAC
Access time from RAS
–
50
–
60
ns
8, 9
17
tCAC
Access time from CAS
–
13
–
15
ns
8, 9
18
tCAA
Access time from column address
–
25
–
30
ns
8,10
19
tOEA
OE access time
–
13
–
15
ns
20
tRAL
Column address to RAS lead time
25
–
30
–
ns
21
tRCS
Read command setup time
0
–
0
–
ns
22
tRCH
Read command hold time
0
–
0
–
ns
11
23
tRRH
Read command hold time referenced to RAS
0
–
0
–
ns
11
24
tCLZ
CAS to output in low-Z
0
–
0
–
ns
8
25
tOFF
Output buffer turn-off delay
0
13
0
15
ns
12
26
tOEZ
Output turn-off delay from OE
0
13
0
15
ns
12
27
tDZC
Data to CAS low delay
0
–
0
–
ns
13
28
tDZO
Data to OE low delay
0
–
0
–
ns
13
29
tCDD
CAS high to data delay
10
–
13
–
ns
14
30
tODD
OE high to data delay
10
–
13
–
ns
14
V53C316405A Rev. 1.2 March 1998
5
V53C316405A
MOSEL VITELIC
AC Characteristics(5,6)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V, tT = 2 ns
-50
#
Symbol
Parameter
-60
min.
max.
min.
max.
Unit
Note
Write Cycle
31
tWCH
Write command hold time
8
–
10
–
ns
32
tWP
Write command pulse width
8
–
10
–
ns
33
tWCS
Write command setup time
0
–
0
–
ns
34
tRWL
Write command to RAS lead time
13
–
15
–
ns
35
tCWL
Write command to CAS lead time
13
–
15
–
ns
36
tDS
Data setup time
0
–
0
–
ns
16
37
tDH
Data hold time
8
–
10
–
ns
16
15
Read-modify-Write Cycle
38
tRWC
Read-write cycle time
113
–
138
–
ns
39
tRWD
RAS to WE delay time
64
–
77
–
ns
15
40
tCWD
CAS to WE delay time
27
–
32
–
ns
15
41
tAWD
Column address to WE delay time
39
–
47
–
ns
15
42
tOEH
OE command hold time
10
–
13
–
ns
EDO Page Mode Cycle
43
tPC
EDO page mode cycle time
20
–
25
–
ns
44
tCP
CAS precharge time
8
–
10
–
ns
45
tCPA
Access time from CAS precharge
–
27
–
32
ns
46
tCOH
Output data hold time
5
–
5
–
ns
47
tRAS
RAS pulse width in EDO mode
50
200k
60
200k
ns
48
tRHPC
CAS precharge to RAS Delay
27
–
32
–
ns
tDES
OE setup time prior to CAS
5
5
ns
EDO Page Mode Read-modify-Write Cycle
49
tPRWC
EDO page mode read-write cycle time
58
–
68
–
ns
50
tCPWD
CAS precharge to WE
41
–
49
–
ns
CAS-before-RAS Refresh Cycle
51
tCSR
CAS setup time
10
–
10
–
ns
52
tCHR
CAS hold time
10
–
10
–
ns
53
tRPC
RAS to CAS precharge time
5
–
5
–
ns
54
tWRP
Write to RAS precharge time
10
–
10
–
ns
55
tWRH
Write hold time referenced to RAS
10
–
10
–
ns
V53C316405A Rev. 1.2 March 1998
6
7
V53C316405A
MOSEL VITELIC
AC Characteristics(5,6)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V, tT = 2 ns
-50
#
Symbol
Parameter
-60
min.
max.
min.
max.
Unit
CAS precharge time
35
–
40
–
ns
CAS-before-RAS Counter Test Cycle
56
tCPT
Test Mode
60
tWTS
Write command setup time
10
–
10
–
ns
61
tWTH
Write command hold time
10
–
10
–
ns
62
tCHRT
CAS hold time
30
–
30
–
ns
63
tRAHT
RAS hold time
30
V53C316405A Rev. 1.2 March 1998
7
30
ns
Note
V53C316405A
MOSEL VITELIC
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC5 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a
EDO page mode cycle
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum
of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured
between VIH and VIL.
8) Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by
the latter of tRAC, tCAC, tCAA,tCPA, tOEA . tCAC is measured from tristate.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced
to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit
(high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle
is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions
is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in readwrite cycles.
V53C316405A Rev. 1.2 March 1998
8
V53C316405A
MOSEL VITELIC
Waveforms of Read Cycle
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
VIH
CAS
t CRP
t RSH
t CAS
VIL
t RAD
t ASR
t RAL
t CAH
t ASC
t ASR
VIH
Address
VIL
Column
Row
Row
t RCH
t RAH
t RCS
t RRH
VIH
WE
VIL
t CAA
t OEA
VIH
OE
VIL
t DZC
I/O
(Inputs)
I/O
(Outputs)
t CDD
t ODD
t DZO
VIH
VIL
t CAC
t CLZ
VOH
Hi Z
t OFF
t OEZ
Valid Data Out
Hi Z
VOL
t RAC
“H” or “L”
WL1
V53C316405A Rev. 1.2 March 1998
9
V53C316405A
MOSEL VITELIC
Waveforms of Write Cycle (Early Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tRSH
VIH
CAS
tCRP
tCAS
VIL
tRAD
tASR
tRAL
tCAH
tASC
tASR
.
VIH
Address
Column
Row
Row
VIL
tCWL
tRAH
tWCS
tWP
VIH
WE
VIL
tWCH
tRWL
VIH
OE
VIL
tDS
I/O
(Inputs)
I/O
(Outputs)
tDH
VIH
Valid Data In
VIL
VOH
Hi Z
VOL
“H” or “L”
WL2
V53C316405A Rev. 1.2 March 1998
10
V53C316405A
MOSEL VITELIC
Waveforms of Write Cycle (OE Controlled Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
VIH
CAS
tCSH
tRSH
tCAS
VIL
t RAD
t ASR
t RAL
t CAH
t ASC
t ASR
.
VIH
Address
Row
Column
Row
VIL
tCWL
tRWL
t RAH
tWP
VIH
WE
VIL
tOEH
VIH
OE
VIL
tODD
tDH
tDZO
tDZC
I/O
(Inputs)
tOEZ
tDS
VIH
Valid Data
VIL
tCLZ
tOEA
VOH
I/O
(Outputs)
Hi-Z
Hi-Z
VOL
WL3
“H” or “L”
V53C316405A Rev. 1.2 March 1998
11
V53C316405A
MOSEL VITELIC
Waveforms of Read-Write (Read-Modify-Write) Cycle
tRWC
tRAS
tRP
VIH
VIL
RAS
tCSH
tRCD
tRSH
tCAS
VIH
CAS
tCRP
VIL
tRAH
tCAH
tASR
tASC
tASR
VIH
Address
Row
Column
Row
VIL
tCWL
tAWD
tRAD
tCWD
tRWL
tRWD
tWP
VIH
WE
VIL
tCAA
tRCS
tOEA
tOEH
VIH
OE
VIL
tDS
tDZO
tDZC
tDH
VIH
I/O
(Inputs)
Valid
Data in
VIL
tCLZ
tODD
tCAC
tOEZ
I/O
(Outputs)
VOH
Data
Out
VOL
t RAC
“H” or “L”
V53C316405A Rev. 1.2 March 1998
WL4
12
V53C316405A
MOSEL VITELIC
Waveforms of EDO Page Mode Read Cycle
t RP
tRAS
VIH
tRCD
RAS
tRHPC
VIL
tRSH
tPC
tCRP
tCAS
tCAS
tCP
tCRP
tCAS
VIH
CAS
VIL
tCRH
tASR
tRAL
tRAH tASC
tCAH
tASC
tCAH
tASC tCAH
Column 2
Column N
VIH
Address
Row
Column 1
VIL
tRAD
tRRH
tRCS
tRCH
VIH
WE
VIL
tCAC
tCAA
tOES
tCAC
tCAA
tCPA
tCPA
tCOH
tCOH
tOFF
tOEA
VOH
OE
VOL
tRAC
tOEZ
tCAA
tCAC
I/O
(Output)
tCLZ
VIH
Data Out
1
VIL
Data Out
2
Data Out
N
WL5
“H” or “L”
V53C316405A Rev. 1.2 March 1998
13
V53C316405A
MOSEL VITELIC
Waveforms of EDO Page Mode Early Write Cycle
tRP
tRAS
VIH
tRCD
tRHPC
RAS
VIL
tRSH
tPC
tCRP
tCAS
tCAS
tCAS
tCP
tCRP
VIH
CAS
VIL
tRAL
tCSH
tASR
tRAH tASC
tCAH
tASC
tASC
tCAH
tCAH
VIH
Address
VIL
Row
Addr
Column 1
Column 2
Column N
tRAD
tRWL
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tWP
VIH
tCWL
tWCS
tWCH
tWP
tWP
WE
VIL
VOH
OE
VOL
tDS
tDH
tDS
tDH
tDS
tDH
VIH
I/O (Input)
Data In 1
Data In 2
VIL
“H” or “L”
V53C316405A Rev. 1.2 March 1998
Data In N
WL8
14
VIL
tRP
tCSH
tPRWC
tRSH
tRCD
tCAS
VIH
tCAS
tCRP
tCAS
CAS
VIL
tRAD
tASR
tCAH
tCAH
tRAH
tASC
tASC
tRAL
tCAH
tASR
tASC
VIH
Address
Row
tRCS
Column
Column
Column
VIL
tRWD
tCWD
tCPWD
tCWD
tCWL
Row
tCPWD
tCWD
tCWL
tRWL
tCWL
VIH
15
WE
tAWD
tAWD
tAWD
tCAA
tOEA
VIL
tWP
tWP
tWP
tOEA
tOEA
VIH
OE
VIL
tDZC
I/O
(Inputs)
tDZC
tDZO
VIH
Data In
VIL
tCAC
tODD
tRAC
tOEZ
Data
Out
tDZC
Data In
tCLZ
tOEH
tDH
tODD
Data In
tCLZ
tOEH
tCAA
tOEZ
tDH
tCAA
tOEH
tCAC
tDH
tDS
tDS
VOH
VOL
tODD
Data
Out
tDS
Data
Out
WL17
V53C316405A
I/O
(Outputs)
tCPA
tCPA
tCLZ
MOSEL VITELIC
RAS
Waveforms of EDO Page Mode Late Write and Read-Modify-Write Cycle
V53C316405A Rev. 1.2 March 1998
tRAS
VIH
V53C316405A
MOSEL VITELIC
Waveforms of RAS Only Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCRP
tRPC
VIH
CAS
VIL
tRAH
tASR
tASR
VIH
Address
Row
Row
VIL
I/O
(Outputs)
VOH
HI-Z
VOL
“H” or “L”
V53C316405A Rev. 1.2 March 1998
WL9
16
V53C316405A
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Cycle
tRC
tRP
tRAS
tRP
VIH
RAS
VIL
tRPC
tCP
tCRP
tCSR
tRPC
tCHR
VIH
CAS
VIL
tWRP
tWRH
VIH
WE
VIL
tOEZ
VIH
OE
VIL
tCDD
I/O
(Inputs)
VIH
VIL
tODD
I/O
(Outputs)
VOH
HI-Z
VOL
tOFF
“H” or “L”
WL10
V53C316405A Rev. 1.2 March 1998
17
V53C316405A
MOSEL VITELIC
Waveforms of Hidden Refresh Read Cycle
tRC
tRC
tRP
tRAS
VIH
tRP
tRAS
RAS
VIL
tRSH
tRCD
tCHR
tCRP
VIH
CAS
VIL
tRAD
tWRP
tASC
tRAH
tASR
tWRH
tCAH
tASR
VIH
Address
Column
Row
Row
VIL
tRRH
tRCS
VIH
WE
VIL
tCAA
tOEA
VIH
OE
VIL
tDZC
tCDD
tDZO
tODD
I/O
(Inputs)
VIH
VIL
tCAC
tOFF
tCLZ
tOEZ
tRAC
I/O
(Outputs)
VOH
Valid Data Out
VOL
“H” or “L”
V53C316405A Rev. 1.2 March 1998
HI-Z
WL11
18
V53C316405A
MOSEL VITELIC
Waveforms of Hidden Refresh Early Write Cycle
tRC
tRC
tRP
tRAS
VIH
RAS
tRAS
tRP
VIL
tRCD
tRSH
tCHR
tCRP
VIH
CAS
tRAD
VIL
tRAH
tASC
tASR
tASR
tCAH
VIH
Address
Row
Row
Column
VIL
tWCS
tWRP
tWCH
tWRH
tWP
VIH
WE
VIL
tDS
I/O
(Input)
I/O
(Output)
tDH
VIH
Valid Data
VIL
VOH
HI-Z
VOL
“H” or “L”
WL12
V53C316405A Rev. 1.2 March 1998
19
V53C316405A
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
tRAS
Read Cycle:
RAS
tCSB
CAS
tRP
VIH
VIL
tRSH
tCAS
tCP
tCHR
VIH
VIL
tRAL
tASC
Address
WE
OE
I/O
(Inputs)
VIH
VIL
tASR
tCAH
Column
tWRP
VIH
VIL
Row
tRRH
tCAA
tWRH
tRCS
VIH
VIL
tOEA
tDZC
tDZO
tOFF
Data Out
tWCS
Write Cycle:
OE
tOEZ
VOH
VOL
tWRP
WE
VIH
VIL
tRWL
tCWL
tWCH
tWRH
VIH
VIL
tDS
I/O
(Inputs)
VIH
VIL
I/O
(Outputs)
VIH
VIL
V53C316405A Rev. 1.2 March 1998
tCDD
tODD
VIH
VIL
tCLZ
I/O
(Outputs)
tRCH
tCAC
tDH
Data In
HI-Z
20
V53C316405A
MOSEL VITELIC
Waveforms of Test Mode Entry
tRC
tRP
tRAS
VIH
tRP
RAS
VIL
tRPC
tCP
tCSR
tCHRT
tRPC
tCRP
VIH
CAS
VIL
tASR
tRAHT
VIH
Address
Row
VIL
tWTS
tWTH
VIH
WE
VIL
VIH
OE
VIL
tODD
I/O
(Inputs)
VIH
HI-Z
VIL
tCDD
tOEZ
I/O
(Outputs)
VOH
HI-Z
VOL
tOFF
“H” or “L”
WL15
V53C316405A Rev. 1.2 March 1998
21
V53C316405A
MOSEL VITELIC
Test Mode
they were not equal, the I/O would indicate a “0”. The
WCBR cycle (WE, CAS before RAS) puts the device
into test mode. To exit from test mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be used.Refresh during test mode
operation can be performed by normal read cycles or
by WCBR refresh cycles.
Row addresses A0 through A11 have to kept high
to perform a testmode entry cycle. All other addresses are don’t care.
As the V53C316405A is organized internally as
4M x 4-bits, a test mode cycle using 4:1 compression
can be used to improve test time. Note that in the 4M
x 4 version the test time is reduced by 1/4 for a N test
pattern.
In a test mode “write” the data from each I/O pin is
written into four 1M blocks simultaneously (all “1” s
or all “0” s). In test mode “read” each I/O output is
used for indicating the test mode result. If the internal
four bits are equal, the I/O would indicate a “1”. If
Block Diagram in Test Mode
A0C,A1C
A0C,A1C
Normal
1 M Block
Vcc
1 M Block
Normal
I/O 1
Test
I/O 1
1 M Block
Test
1 M Block
A0C,A1C
A0C,A1C
Normal
Vss
Vcc
1 M Block
Normal
1 M Block
I/O 2
I/O 2
1 M Block
Test
Test
1 M Block
A0C,A1C
A0C,A1C
Normal
1 M Block
Vss
Vcc
1 M Block
I/O 3
Normal
Test
1 M Block
I/O 3
Test
1 M Block
A0C,A1C
A0C,A1C
1 M Block
Vss
Vcc
Normal
1 M Block
Normal
I/O 4
Test
I/O 4
1 M Block
Test
1 M Block
Vss
V53C316405A Rev. 1.2 March 1998
22
V53C316405A
MOSEL VITELIC
Package Diagrams
24/26-pin 300 mil SOJ
0.104 ± 0.003
[2.64 ± 0.1]
0.315 min
[0.8] min
0.020 [0.5]
30°
0.148 -0.020
[3.75 -0.5]
0.335 [0.85] Max
.05 [1.27]
0.020 -0.003
[0.51 -0.1]
[0.003] 0.1
0.007 [0.18] M 24x
0.009 [0.25] A
0.6 [15.24]
26
21
19
1
6
8
1
0.008 +0.003
[0.2 +0.1]
B
0.268 ±0.008
[6.8 ±0.2]
0.009 [0.25] B
0.340 -0.009
[8.63 -0.25]
0.007 [0.18] M B
14
13
1
A
0.680 -0.009
[17.27 -0.25]
Index Marking
1
0.305 -0.009
[7.75 -0.25]
Units in inches [mm]
Does not include plastic or metal protrusion of 0.15 max. per side
24/26-pin 300 mil TSOP-II
0.039 ± 0.002
[1.0 ± 0.05]
0.006 ±0.002
[0.15±0.05]
0.050 max
[1.27 max]
0.3 ± 0.005
[7.62 ± 0.13]
0.006
+0.003
–0.004
0.15 +0.08
–0.09
5° max.
0.05 [1.27]
0.016
+0.005
–0.004
0.4
0.004 [0.1]
+0.12
–0.1
0.008 [0.2] M 24x
26
0.363 ± 0.008
[9.22 ± 0.2]
14
1
Unit in inches [mm]
13
1
0.680±0.005
[17.27±0.13]
1
Does not include plastic or metal protrusion of 0.15 max. per side
V53C316405A Rev. 1.2 March 1998
0.024 -0.008
[0.6 -0.2]
23
MOSEL VITELIC
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V53C316405A
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FAX: 603-889-9347
© Copyright 1998, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
3/98
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461