MOSEL VITELIC V58C3643204SAT HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32 System Frequency (fCK) 45 50 55 60 225MHz 200 MHz 183 MHz 166 MHz 5 ns 5.5 ns 6 ns Clock Cycle Time (tCK3) Clock Cycle Time (tCK4) PRELIMINARY 4.5 ns Features Description ■ 4 banks x 512K x 32 organization ■ High speed data transfer rates with system frequency up to 225 MHz ■ Data Mask for Write Control (DM) ■ Four Banks controlled by BA0 & BA1 ■ Programmable CAS Latency: 3, 4 ■ Programmable Wrap Sequence: Sequential or Interleave ■ Programmable Burst Length: 2, 4, 8 full page for Sequential Type 2, 4, 8 full page for Interleave Type ■ Automatic and Controlled Precharge Command ■ Suspend Mode and Power Down Mode ■ Auto Refresh and Self Refresh ■ Refresh Interval: 2048 cycles/16ms ■ Available in 100-pin TQFP ■ SSTL-2 Compatible I/Os ■ Double Data Rate (DDR) ■ Bidirectional Data Strobe (DQs) for input and output data, active on both edges ■ On-Chip DLL aligns DQ and DQs transitions with CLK transitions ■ Differential clock inputs CLK and CLK ■ Power Supply 3.3V ± 0.3V The V58C3643204SAT is a four bank DDR DRAM organized as 4 banks x 512K x 32. The V58C3643204SAT achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Device Usage Chart Operating Temperature Range Package Outline 100-pin TQFP -45 -50 -55 -60 Std. L Temperature Mark 0°C to 70°C • • • • • • • Blank V58C3643204SAT Rev. 1.4 August 2001 CLK Cycle Time (ns) 1 Power MOSEL VITELIC V58C3643204SAT Block Diagram Row Addresses Column Addresses A0 - A7, AP, BA0, BA1 Row address buffer Column address buffer Refresh Counter Row decoder Row decoder Memory array Memory array Memory array Memory array Bank 0 512K x 32 Bank 1 512K x 32 Input buffer Column decoder Sense amplifier & I(O) bus Row decoder Column decoder Sense amplifier & I(O) bus Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Column address counter A0 - A10, BA0, BA1 Bank 2 512K x 32 Output buffer Bank 3 512K x 32 Control logic & timing generator Strobe Gen. Data Strobe V58C3643204SAT Rev. 1.4 August 2001 2 WE CAS CS RAS CKE DM0-DM3 DQS DLL CLK CLK, CLK CLK DQ0-DQ MOSEL VITELIC V58C3643204SAT DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF DM3 DM1 CLK CLK CKE MCL A8(AP) 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Top View 80 100 Pin TQFP PIN CONFIGURATION DQ29 81 50 A7 VSSQ 82 49 A6 DQ30 83 48 A5 DQ31 84 47 A4 VSS 85 46 VSS VDDQ 86 45 A9 N.C 87 44 N.C N.C 88 43 N.C N.C 89 42 N.C N.C 90 41 N.C N.C 91 40 N.C VSSQ 92 39 N.C RFU 93 38 N.C DQS 94 37 N.C VDDQ 95 36 A10 VDD 96 35 VDD DQ0 97 34 A3 DQ1 98 33 A2 VSSQ 99 32 A1 100 31 A0 20 x 14 mm2 15 16 17 18 19 20 21 22 23 24 VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 30 14 VDDQ BA1 13 DQ19 29 12 DQ18 BA0 11 VSSQ 28 10 DQ17 CS 9 DQ16 27 8 VDDQ RAS 7 DQ7 26 6 DQ6 CAS 5 VSSQ 25 4 DQ5 WE 3 2 DQ4 1 DQ3 0.65mm pin Pitch VDDQ DQ2 100 Pin TQFP Pin Names CLK, CLK Differential Clock Input DQ0–DQ7 Data Input/Output CKE Clock Enable DM0-DM3 Data Mask CS Chip Select VDD Power (3.3V ± 0.3V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for I/O’s (+2.5V) WE Write Enable VSSQ Ground for I/O’s DQS Data Strobe (Bidirectional) NC Not connected A0–A10 Address Inputs VREF Reference Voltage for Inputs BA0, BA1 Bank Select RFU Reserved for future use. V58C3643204SAT Rev. 1.4 August 2001 3 MOSEL VITELIC V58C3643204SAT Signal Pin Description Pin Type Signal Polarity Function CLK CLK Input Pulse Positive Edge The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CLK. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. DQS Input/ Output Pulse Active High Active on both edges for data input and output. Center aligned to input data Edge aligned to output data A0 - A10 Input Level — During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge. CAn depends from the SDRAM organization: 2M x 32 SDRAM CAn = CA7 (Page) In addition to the column address, A8 is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A8 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A8 is low, autoprecharge is disabled. During a Precharge command cycle, A8(=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged simultaneously regardless of state of BA0 and BA1. BA0, BA1 Input Level — Selects which bank is to be active. DQx Input/ Output Level — Data Input/Output pins operate in the same manner as on conventional DRAMs. DM0-DM3 Input Pulse Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if is high. VDD, VSS Supply Power and ground for the input buffers and the core logic. VDDQ VSSQ Supply — — Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Input Level — SSTL Reference Voltage for Inputs V58C3643204SAT Rev. 1.4 August 2001 4 MOSEL VITELIC V58C3643204SAT Auto Precharge Operation The Auto Precharge operation can be issued by having column address A8 high when a Read or Write command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. When the Auto Precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the Read or Write cycle once tRAS(min) is satisfied. Read with Auto Precharge If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency programmed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until the minimum precharge time (tRP) has been satisfied. Read with Autoprecharge Timing (CAS Latency = 2; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 T7 tRAS(min) T8 T9 tRP(min) CK, CK Command BA NOP R w/AP NOP NOP NOP NOP NOP BA DQS D0 DQ D1 D2 D3 Begin Autoprecharge Earliest Bank A reactivate V58C3643204SAT Rev. 1.4 August 2001 5 MOSEL VITELIC V58C3643204SAT DC Characteristics Recommended operating conditions Unless Otherwise Noted, TA=0 to 70°C Version Parameter Operating Current (One Bank Active) Symbol Test Condition -45 -50 -55 -60 350 340 330 330 Unit Note ICC1 Burst Lenth = 2 tRC Š tRC(min) IOL= 0mA, tCC = tCC(min) Precharge Standby Current in Power-down mode ICC2P CKE ð VIL(max), tCC = tCC(min) Precharge Standby Current in Non Power-down mode ICC2N CKE ð VIH(min), CS Š VIH(min), tCC = tCC(min) Active Standby Current power-down mode ICC3P CKE ð VIL(max), tCC = tCC(min) Active Standby Current in in Non Power-down mode ICC3N CKE Š VIH(min), CS Š VIH(min), tCC = tCC(min) 205 200 195 190 mA 60 165 160 mA 1 mA 155 150 95 mA mA Operating Current (Burst Mode) ICC4 IOL = 0mA, tCC = tCC(min), Page Burst, All Banks activated 470 450 430 410 mA 1 Refresh Current ICC5 tRC Š tRFC(min) 470 450 430 410 mA 2 Self Refresh Current ICC6 CKE ð 0.2V 4 mA Notes: 1. Measured with outputs open. 2. Refresh period is 16ms. Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN , VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1.6 W Short circuit current IOS 50 mA Storage temperature Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. V58C3643204SAT Rev. 1.4 August 2001 6 MOSEL VITELIC V58C3643204SAT Power & DC Operating Conditions (SSTL_2 In/Out) Recommended operating conditions (Voltage referenced to VSS=0V, TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Device Supply voltage VDD 3.135 3.3 3.465 V Output Supply voltage VDDQ 2.375 2.50 2.625 V Reference voltage VREF 0.49*VDDQ - 0.51*VDDQ V Termination voltage Vtt VREF-0.04 VREF V REF+0.04 V Input logic high voltage VIH VREF+0.15 - VDDQ+0.30 V Input logic low voltage VIL -0.30 - VREF-0.15 V Output logic high voltage IOH = -15.2mA VOH Vtt+0.76 - - V Output logic low voltage VOL - - Vtt-0.76 V Input leakage current IIL -5 - 5 µA Output leakage current IOL -5 - 5 µA AC Input Operating Conditions Recommended operating conditions (Voltage referenced to VSS=0V, VDD=3.3V+ 5%, VDDQ=2.5V+ 5%, TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V Input Low (Logic 0) Voltage; DQ VIL - - VREF -0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V SSTL_2 AC Test Conditions Symbol Parameter Value Units Notes 0.5*VDDQ V 1 VREF Input Reference Voltage V SWING (max) Input Signal Maximum Peak to Peak Swing 1.5 V 1, 2 SLEW Input Signal Minimum Slew Rate 1.0 V/ns 3 Notes: 1. Input waveform timing is referenced to the input signal crossing the VREF level applied to the device. 2. Compliant devices must still meet the VIH (AC) and VIL (AC) specifications under actual use conditions. 3. The 1 V/ns input signal minimum slew rate is to be maintained in the VIL max (AC) to VIL min (AC) range of the input signal swing. V58C3643204SAT Rev. 1.4 August 2001 7 MOSEL VITELIC V58C3643204SAT SSTL_2 Output Buffers ■ ■ ■ ■ The input voltage provided to the receiver depends on three parameters: VDDQ and current drive capabilities of the output buffer Termination voltage Termination resistance VDDQ ð VDD Class II SSTL_2 Output Buffer (Driver) VDDQ VTT = 0.5 *VDDQ RT=50Ω Output Buffer Receiver VREF VOUT CLOAD = 30pF VIN VSSQ Capacitance (VDD = 3.3V, TA = 25°C, f = 1MHz) Parameter Symbol Min Max Unit Input capacitance (A0~A10, BA0~BA1) CIN1 2.5 4.5 pF Input capacitance ( CK, CK, CKE, CS, RAS, CAS, WE ) CIN2 2.5 5.0 pF Data & DQS input/output capacitance (DQ 0~DQ31) COUT 2.5 5.5 pF Input capacitance (DM0 ~ DM3) CIN3 2.5 5.5 pF V58C3643204SAT Rev. 1.4 August 2001 8 MOSEL VITELIC V58C3643204SAT AC Characteristics -45 Parameter CK cycle time Symbol CL=3 tCK CL=4 -50 -55 -60 Min Max Min Max Min Max Min • 7 5 .0 7 5.5 7 6 .0 4.5 • • Max Unit 7 • ns ns CK high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQS out access time from CK tDQSCK -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns Output access time from CK tAC -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to output data edge tDQSQ - 0.5 - 0.5 - 0.5 ns Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-In setup time tWPRES 0 - 0 - 0 - ns DQS-in hold time tWPREH 0.25 - 0.25 - 0.25 - tCK DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS-In high level width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS-In low level width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 tCK Address and Control input setup time tIS 1.2 - 1.2 - 1.2 - ns Address and Control input hold time tIH 0.9 - 0.9 - 0.9 - ns DQ and DM setup time to DQS tDS 0.5 - 0.5 - 0.5 - ns DQ and DM hold time to DQS tDH 0.5 - 0.5 - 0.5 - ns Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns Output DQS valid window tQH tHP0.75ns - tHP0.75ns - tHP0.75ns - ns Row cycle time tRC 58 60 60.5 60 ns Refresh row cycle time tRFC 69 70 71.5 72 ns Row active time tRAS RAS to CAS delay tRCD 18 Row precharge time tRP Row active to Row active delay tRRD Last data in to Row precharge Last data in to Read command delay 40 100K 44 100K 48 100K ns 20 22 24 ns 12 20 16.5 18 ns 9 14 11 12 ns tWR 2 2 2 2 tCK tCDLR 2 2 2 2 tCK Col. address to Col. address delay tCCD 1 1 1 1 tCK Mode register set cycle time tMRD 2 2 2 2 tCK Power down exit time tPEDX 1tCK+tIS 1tCK+tIS 1tCK+tIS ns 70 71.5 72 ns 200 200 6 5 5 tCK 7.8 7.8 7.8 µs Self refresh exit to active command delay tXSA 69 Self refresh exit to read command delay tXSR Auto precharge write recovery + Precharge tDAL Refresh interval time tREF V58C3643204SAT Rev. 1.4 August 2001 6 9 200 tCK MOSEL VITELIC V58C3643204SAT AC Characteristics V58C3643204SAT-45 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit 250MHz (4.5ns) 4 13 15 9 4 2 4 2 tCK 222MHz (5.0ns) 3 12 14 8 4 2 4 2 tCK 183MHz (5.5ns) 3 12 14 8 4 2 4 2 tCK 166MHz (6.0ns) 3 10 12 7 3 2 3 2 tCK 143MHz (7.0ns) 3 9 11 6 3 2 3 2 tCK V58C3643204SAT-50 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit 200MHz (5.0ns) 3 12 14 8 4 2 4 2 tCK 183MHz (5.5ns) 3 12 14 8 4 2 4 2 tCK 166MHz (6.0ns) 3 10 12 7 3 2 3 2 tCK 143MHz (7.0ns) 3 9 11 6 3 2 3 2 tCK V58C3643204SAT-55 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit 183MHz (5.5ns) 3 12 14 8 4 2 4 2 tCK 166MHz (6.0ns) 3 10 12 7 3 2 3 2 tCK 143MHz (7.0ns) 3 9 11 6 3 2 3 2 tCK V58C3643204SAT-60 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit 166MHz (6.0ns) 3 10 12 7 3 2 3 2 tCK 143MHz (7.0ns) 3 9 11 6 3 2 3 2 tCK V58C3643204SAT Rev. 1.4 August 2001 10 MOSEL VITELIC V58C3643204SAT Package Diagram 100-Pin TQFP Dimensions in Millimeters 0 ~ 7∞ 17.20 ± 0.20 14.00 ± 0.10 #100 #1 23.20 ± 0.20 0.575 20.00 ± 0.10 0.825 0.30 ± 0.08 0.13 MAX 0.65 0.09~0.20 1.00 ± 0.10 1.20 MAX * 0.10 MAX 0.05 MIN 0.80 ± 0.20 V58C3643204SAT Rev. 1.4 August 2001 11 MOSEL VITELIC WORLDWIDE OFFICES V58C3643204SAT U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 © Copyright 2001, MOSEL VITELIC Inc. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC CENTRAL, NORTHEASTERN & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029 8/01 Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461