V62C2802048L(L) Ultra Low Power 256K x 8 CMOS SRAM Features Functional Description • Low-power consumption - Active: 35mA at 55ns - Stand-by: 10 µA (CMOS input/output) 2 µA CMOS input/output, L version The V62C2802048L is a low power CMOS Static RAM organized as 262,144 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, an active HIGH CE2, an active LOW OE, and Tri-state I/O’s. This device has an automatic power-down mode feature when deselected. • Single +2.2 to 2.7V Power Supply_Typical • Extented Voltage from 2.2 to 3.6V. Writing to the device is accomplished by taking Chip Enable 1 (CE1) with Write Enable (WE) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is performed by taking Chip Enable 1 (CE1) with Output Enable (OE) LOW while Write Enable (WE) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. • Equal access and cycle time • 55/70/85/100 ns access time • Easy memory expansion with CE1, CE2 and OE inputs • 1.0V data retention mode TheV62C2802048LL comes with a 1V data retention feature and Lower Standby Power. The V62C2802048L is avalable in a 32-pin 8 x 20 mm TSOP1 / STSOP 8x13.4 mm and CSP type 48-fpBGA packages. • TTL compatible, Tri-state input/output • Automatic power-down when deselected • Package available: 32L TSOP(I)/ STSOP(I) • 48 Ball CSP_BGA Logic Block Diagram 32-Pin TSOP1 / STSOP (CSP_BGA See next page) A11 A9 A8 A13 WE CE2 ROW DECODER A3 A4 A5 A6 A7 A8 A9 SENSE AMP INPUT BUFFER A0 A1 A2 Cell Array A17 A16 A14 A12 A7 A6 A5 A4 I/O1 COLUMN DECODER A10 A15 Vcc I/O8 A 11 A12 A 13 A 14 A 15 A 16 A 17 CONTROL CIRCUIT OE WE CE1 CE2 1 REV. 1.2 May 2001 V62C2802048L(L) 1 2 32 31 3 4 5 6 7 30 8 9 10 11 12 13 14 15 16 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 V62C2802048L(L) MOSEL VITELIC 1 2 3 V62C2802048L(L)B 4 5 6 1 2 3 4 5 6 A A0 A1 CS2 A3 A6 A8 B I/O5 A2 WE A4 A7 I/O1 C I/O6 NC NC A5 NC I/O2 D VSS NC NC NC NC VCC E VCC NC NC NC NC VSS F I/O7 NC NC A17 NC I/O3 G I/O8 OE CS1 A16 A15 I/O4 H A9 A10 A11 A12 A13 A14 Note: NC means no Ball. Top View Top View 48 Ball - 9x12 fpBGA (Ultra Low Power) A1 C PACKAGE OUTLINE DWG. SYMBOL UNIT:MM A 1.05+0.15 A1 0.25+0.05 b 0.35+.05 A aaa SIDE VIEW D D1 e 6 E1 4 E 5 3 2 1 A B C D E F G H b SOLDER BALL BOTTOM VIEW 2 REV. 1.2 May 2001 V62C2802048L(L) c 0.30(TYP) D 12.00+0.10 D1 5.25 E 9.00+0.10 E1 3.75 e 0.75TYP aaa 0.10 V62C2802048L(L) Absolute Maximum Ratings * Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Vt -0.5 3.6 V Power Dissipation PT − 1.0 W Storage Temperature (Plastic) Tstg -55 +150 0C Temperature Under Bias Tbias -40 +85 0 C * Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth Table CE1 CE2 WE OE Data Mode H X X X High-Z Standby X L X X High-Z Standby L H H L Data Out L H H H High-Z Active, Output Disable L H L X Data In Active, Write Active, Read * Key: X = Don’t Care, L = Low, H = High Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**) Parameter Supply Voltage Input Voltage Symbol Min Typ Max Unit VCC 2.2 2.5 2.7 V Gnd 0.0 0.0 0.0 V VIH 2.0 - VCC + 0.2 V VIL -0.5* - 0.6 V * VIL min = -1.0V for pulse width less than tRC/2. ** For Industrial Temperature 3 REV. 1.2 May 2001 V62C2802048L(L) V62C2802048L(L) DC Operating Characteristics (Vcc = 2.2~2.7V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter Sym Test Conditions -55 -70 -85 -100 Min Max Min Max Min Max Min Max Unit Input Leakage Current IILII Vcc = Max, Vin = Gnd to Vcc - 1 - 1 - 1 - 1 µA Output Leakage Current IILOI CE1 = VIH or CE2 = VIL Vcc= Max, VOUT = Gnd to Vcc - 1 - 1 - 1 - 1 µA Operating Power Supply Current ICC CE1 = VIL , CE2 = VIH VIN = VIH or VIL , IOUT = 0 mA - 3 - 3 - 3 - 3 mA ICC1 CE1 = VIL , CE2 = VIH IOUT = 0mA, Min Cycle, 100% Duty - 35 - 30 - 25 - 20 mA ICC2 CE1 = 0.2V, CE2 = Vcc - 0.2V IOUT = 0mA, - 3 - 3 - 3 - 3 mA Average Operating Current Cycle Time=1µs, 100% Duty Standby Power Supply Current (TTL Level) ISB CE1 = VIH or CE2 = VIL - 0.5 - 0.5 - 0.5 - 0.5 mA Standby Power Supply Current (CMOS Level) ISB1 CE1 > Vcc - 0.2V or CE2 < 0.2V, f = 0 VIN < 0.2V or VIN > Vcc- 0.2V - 10 - 10 - 10 - 10 µA - 2 - 2 - 2 - 2 µA Output Low Voltage VOL IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V Output High Voltage VOH IOH = -2 mA 2.0 - 2.0 - 2.0 - 2.0 - V L Capacitance (f = 1MHz, TA = 250C) Parameter* Symbol Test Condition Max Unit Input Capacitance Cin Vin = 0V 7 pF I/O Capacitance CI/O Vin = Vout = 0V 8 pF * This parameter is guaranteed by device characterization and is not production tested. AC Test Conditions Input Pulse Level 0.6V to 2.2V Input Rise and Fall Time TTL 5ns CL* Input and Output Timing Reference Level 1.4V Output Load Condition 70ns/85 ns C Load 100ns/120 ns L Figure A. = 30pf + 1TTL Load CL= 100pf + 1TTL Load 4 REV. 1.2 May 2001 V62C2802048L(L) * Including Scope and Jig Capacitance V62C2802048L(L) Read Cycle (3,9) (Vcc = 2.2~2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol -55 -70 -85 Unit -100 Note Min Max Min Max Min Max Min Max Read Cycle Time tRC 55 - 70 - 85 - 100 - ns Address Access Time tAA - 55 - 70 - 85 - 100 ns Chip Enable Access Time tACE - 55 - 70 - 85 - 100 ns Output Enable Access Time tOE - 35 - 40 - 40 - 50 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tCLZ 10 - 10 - 10 - 10 - ns 4,5 Chip Disable to Output in High-Z tCHZ - 25 - 30 - 35 - 40 ns 4,5 Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - 5 - ns 4,5 Output Disable to Output in High-Z tOHZ - 25 - 25 - 30 - 35 ns 4,5 Power-Up Time tPU 0 - 0 - 0 - 0 - ns 5 Power-Down Time tPD - 55 - 70 - 85 - 100 ns 5 Unit Note Write Cycle (3,11) (Vcc = 2.2~2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol -55 -70 -85 -100 Min Max Min Max Min Max Min Max Write Cycle Time tWC 55 - 70 - 85 - 100 - ns Chip Enable to Write End tCW 45 - 60 - 70 - 80 - ns Address Setup to Write End tAW 45 - 60 - 70 - 80 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 45 - 50 - 60 - 70 - ns Write Recovering Time tWR 0 - 0 - 0 - 0 - ns Data Valid to Write End tDW 25 - 30 - 35 - 40 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z tWZ - 25 - 30 - 35 - 40 ns 4,5 Output Active from Write End tOW 5 - 5 - 5 - 5 - ns 4,5 5 REV. 1.2 May 2001 V62C2802048L(L) V62C2802048L(L) Timing Waveform of Read Cycle 1(Address Controlled) (3,6,7,9) t RC Address tAA tOH DOUT Data Valid Timing Waveform of Read Cycle 2(CE1 Controlled)(5,6,8,9) tRC CE1 tOE OE tOHZ tCHZ tOLZ tACE DOUT Data Valid tPD tCLZ Supply Current ICC tPU 50% 50% ISB Timing Waveform of Read Cycle 3(CE2 Controlled) (3,6,8,9) tRC CE2 tOE OE tOHZ tCHZ tOLZ tACE DOUT Data Valid tPD tCLZ Supply Current ICC tPU 50% 50% 6 REV. 1.2 May 2001 V62C2802048L(L) ISB V62C2802048L(L) Timing Waveform of Write Cycle 1 (WE Controlled)(10,11) tAW tWC tWR Address tWP WE tAS tDW DIN tDH Data Valid tWZ tOW DOUT Timing Waveform of Write Cycle 2 (CE1 Controlled) (10,11) tWC tAW tWR Address tAS tCW CE1 tWP WE tWZ tDW DIN tDH Data Valid DOUT Timing Waveform of Write Cycle 3 (CE2 Controlled) (10,11) tWC tAW tWR Address tAS tCW CE2 tWP WE tWZ tDW DIN Data Valid DOUT REV. 1.2 May 2001 V62C2802048L(L) tDH 7 V62C2802048L(L) Data Retention Characteristics (L Version Only)(1) Parameter Symbol Test Condition Min Max Unit 1.0 - V VCC for Data Retention VDR CE1 > VCC - 0.2V or Data Retention Current ICCDR CE2 < + 0.2V - 1 µA Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or 0 - ns Operation Recovery Time(2) tR VIN < 0.2V tRC - ns Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C) Data Retention Mode VCC Vcc Typ VDR > 1.0V tCDR CE Vcc Typ tR VDR VIH VIH Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition, Figure A. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. This parameter is guaranteed, but is not tested. WE is HIGH for read cycle. CE1 and OE are LOW and CE2 is HIGH for read cycle. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH. All read cycle timings are referenced from the last valid address to the first transtion address. CE1 or WE must be HIGH or CE2 must be LOW during address transition. All write cycle timings are referenced from the last valid address to the first transition address. 8 REV. 1.2 May 2001 V62C2802048L(L) V62C2802048L(L) Ordering Information Device Type* Speed V62C2802048L-55T V62C2802048L-70T V62C2802048L-85T V62C2802048L-100T 55 ns 70 ns 85 ns 100 ns Package 8 x 20 mm 32-pin Plastic TSOP1 V62C2802048LL-55T V62C2802048LL-70T V62C2802048LL-85T V62C2802048LL-100T 55 ns 70 ns 85 ns 100 ns V62C2802048L(L)-55V V62C2802048L(L)-70V V62C2802048L(L)-85V V62C2802048L(L)-100V 55 ns 70 ns 85 ns 100 ns 8 x 13.4 mm 32-pin Plastic STSOP V62C2802048L(L)-55B V62C2802048L(L)-70B V62C2802048L(L)-85B V62C2802048L(L)-100B 55 ns 70 ns 85 ns 100 ns 48-fpBGA * For Industrial Temperature tested devices, an “I” designator will be added to the end of the Device number. 9 REV. 1.2 May 2001 V62C2802048L(L) MOSEL VITELIC V62C2802048L(L) WORLDWIDE OFFICES U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 302 N. 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