HY62UF16406E Series 256Kx16bit full CMOS SRAM Document Title 256K x16 bit 2.7 ~ 3.3V Super Low Power FCMOS Slow SRAM Revision History Revision No History Draft Date Remark 00 Initial Draft Dec.20.2001 Preliminary 01 Package Height Changed 1.0mm -> 0.9mm Mar.05.2002 Preliminary This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.01 / Mar.02 Hynix Semiconductor HY62UF16406E Series Preliminary DESCRIPTION FEATURES The HY62UF16406E is a high speed, super low power and 4Mbit full CMOS SRAM organized as 256K words by 16bits. The HY62UF16406E uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly well-suited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup -. 1.2V(min) data retention • Standard pin configuration -. 48-ball FBGA Voltage (V) Product No. Speed (ns) Operation Current/Icc(mA) 55/70 3 HY62UF16406E-I 2.7~3.3 Note 1. I : Industrial 2. Current value is max. PIN CONNECTION H 5 6 A2 CS2 IO9 /UB A3 A4 /CS1 IO1 IO10 IO11 A5 A6 IO2 IO3 Vss IO12 A17 A7 IO4 Vcc Vcc IO13 NC A16 IO5 Vss IO15 IO14 A14 A15 IO6 IO7 IO16 NC A12 A13 /WE IO8 NC A9 A10 A11 A8 NC FBGA ROW DECODER A1 MEMORY ARRAY 256K x 16 A17 I/O1 I/O8 DATA I/O BUFFER G 4 A1 WRITE DRIVER F 3 A0 BLOCK DECODER E 2 /OE PRE DECODER D 1 /LB ADD INPUT BUFFER C -40~85 BLOCK DIAGRAM COLUMN DECODER B Temperature (°C) SENSE AMP A Standby Current(uA) SL LL 6 10 I/O9 I/O16 /CS1 CS2 /OE /LB /UB /WE PIN DESCRIPTION Pin Name /CS1, CS2 /WE /OE /LB /UB Rev.01 / Mar.02 Pin Function Chip Select Write Enable Output Enable Lower Byte Control (I/O1~I/O8) Upper Byte Control (I/O9~I/O16) Pin Name I/O1~I/O16 A0~A17 Vcc Vss NC Pin Function Data Inputs/Outputs Address Inputs Power (2.7~3.3V) Ground No Connection 2 HY62UF16406E Series ORDERING INFORMATION Part No. HY62UF16406E-SF(I) HY62UF16406E-DF(I) Speed 55/70 55/70 Temp. I I Power SL-part LL-part Package FBGA FBGA Note 1. I : Industrial ABSOLUTE MAXIMUM RATINGS (1) Symbol VIN, VOUT Vcc TA TSTG PD TSOLDER Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating -0.3 to VCC+0.3V -0.3 to 3.6 -40 to 85 -55 to 150 1.0 260 • 10 Unit V V °C °C W °C•sec Remark HY62UF16406E-I Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. TRUTH TABLE /CS1 CS2 /WE /OE /LB /UB H X X X L X X X X X X X L H H H L H H L X X H L X L H L L H L X X H X L H L L H L L L H L X Mode I/O Pin I/O1~I/O8 I/O9~I/O16 Power Deselected Hi-Z Hi-Z Standby Output Disabled Hi-Z Hi-Z Active DOUT Hi-Z DOUT DIN Hi-Z DIN Hi-Z DOUT DOUT Hi-Z DIN DIN Read Write Active Active Note: 1. H=VIH, L=VIL, X=don't care (VIL or VIH) 2. /UB, /LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8. When /UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16. Rev.01 / Mar.02 2 HY62UF16406E Series RECOMMENDED DC OPERATING CONDITION Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.31. Typ 3.0 0 - Max. 3.3 0 Vcc+0.3 0.6 Unit V V V V Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns 2. Undershoot is sampled, not 100% tested. DC ELECTRICAL CHARACTERISTICS TA = -40°C to 85°C Sym Parameter ILI Input Leakage Current ILO Output Leakage Current Icc Operating Power Supply Current ICC1 ISB ISB1 VOL VOH Average Operating Current Standby Current (TTL Input) Standby Current (CMOS Input) Output Low Output High Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS1 = VIH or CS2=VIL or /OE = VIH or /WE = VIL or /UB = VIH , /LB = VIH /CS1 = VIL, CS2=VIH, VIN = VIH or VIL, II/O = 0mA /CS1 = VIL, CS2 = VIH, 55ns VIN = VIH or VIL, Cycle Time = Min, 70ns 100% Duty, II/O = 0mA /CS1 < 0.2V, CS2 > Vcc-0.2V, VIN < 0.2V or VIN > Vcc-0.2V, Cycle Time = 1us, 100% Duty, II/O = 0mA /CS1 = VIH or CS2 = VIL or /UB, /LB = VIH VIN = VIH or VIL /CS1 > Vcc - 0.2V or SL CS2 < Vss + 0.2V or /UB, /LB > Vcc - 0.2V VIN > Vcc - 0.2V or LL VIN < Vss + 0.2V IOL = 2.1mA IOH = -1.0mA Min -1 Typ1. - Max 1 Unit uA -1 - 1 uA 3 mA 20 mA 15 mA 2 mA 300 uA 0.2 6 uA 0.2 10 uA - 0.4 - V V 2.4 Note 1. Typical values are at Vcc = 3.0V TA = 25°C 2. Typical values are not 100% tested CAPACITANCE (Temp = 25°C, f= 1.0MHz) Symbol Parameter CIN Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE) COUT Output Capacitance (I/O) Condition VIN = 0V VI/O = 0V Max. 8 10 Unit pF pF Note : These parameters are sampled and not 100% tested Rev.01 / Mar.02 3 HY62UF16406E Series AC CHARACTERISTICS TA = -40°C to 85°C, unless otherwise specified # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol 55ns Min. Max. Parameter READ CYCLE tRC Read Cycle Time tAA Address Access Time tACS Chip Select Access Time tOE Output Enable to Output Valid tBA /LB, /UB Access Time tCLZ Chip Select to Output in Low Z tOLZ Output Enable to Output in Low Z tBLZ /LB, /UB Enable to Output in Low Z tCHZ Chip Deselection to Output in High Z tOHZ Out Disable to Output in High Z tBHZ /LB, /UB Disable to Output in High Z tOH Output Hold from Address Change WRITE CYCLE tWC Write Cycle Time tCW Chip Selection to End of Write tAW Address Valid to End of Write tBW /LB, /UB Valid to End of Write tAS Address Set-up Time tWP Write Pulse Width tWR Write Recovery Time tWHZ Write to Output in High Z tDW Data to Write Time Overlap tDH Data Hold from Write Time tOW Output Active from End of Write 70ns Min. Max. Unit 55 10 5 10 0 0 0 10 55 55 30 55 20 20 20 - 70 10 5 10 0 0 0 10 70 70 35 70 25 25 25 - ns ns ns ns ns ns ns ns ns ns ns ns 55 50 50 50 0 45 0 0 25 0 5 20 - 70 60 60 60 0 50 0 0 30 0 5 20 - ns ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS TA = -40°C to 85°C, unless otherwise specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW Others Value 0.4V to 2.2V 5ns 1.5V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load AC TEST LOADS VTM=2.8V 1029 Ohm DOUT CL(1) 1728 Ohm Note 1. Including jig and scope capacitance: Rev.01 / Mar.02 4 HY62UF16406E Series TIMING DIAGRAM READ CYCLE 1 (Note 1,4) tRC ADDR tAA tOH tACS /CS1 CS2 tCHZ(3) tBA /UB ,/ LB tBHZ(3) tOE /OE Data Out High-Z tCLZ(3) tOLZ(3) tBLZ(3) tOHZ(3) Data Valid READ CYCLE 2 (Note 1,2,4) tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid READ CYCLE 3 (Note 1,2,4) /CS1 /UB, /LB CS2 tACS tCLZ(3) Data Out tCHZ(3) Data Valid Notes: 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active Rev.01 / Mar.02 5 HY62UF16406E Series WRITE CYCLE 1 (1,4,8) (/WE Controlled) tWC ADDR tW R (2) tCW /CS1 CS2 tAW tBW /UB,/LB tWP /WE tAS Data In tDW High-Z tDH Data Valid tWHZ(3,7) tOW (5) (6) Data Out WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled) tAS (2) tAW tBW tWP tDW Data In tDH High-Z High-Z Rev.01 / Mar.02 6 HY62UF16406E Series Notes: 1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and a low /UB and/or /LB . 2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active DATA RETENTION ELECTRIC CHARACTERISTIC TA= -40°C to 85°C Symbol Parameter VDR Iccdr tCDR tR Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operating Recovery Time Test Condition /CS1 > Vcc - 0.2V or CS2 < Vss + 0.2V or /UB, /LB > Vcc - 0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V Vcc=1.5V, /CS1 > Vcc - 0.2V or CS2 < Vss + 0.2V or /UB, /LB > Vcc - 0.2V VIN > Vcc - 0.2V or VIN < Vss + 0.2V Min Typ1. Max Unit 1.2 - 3.3 V SL - 0.1 3 uA LL - 0.1 6 uA 0 - - ns tRC - - ns See Data Retention Timing Diagram Notes: 1. Typical values are under the condition of TA = 25°C. 2. Typical value are sampled and not 100% tested Rev.01 / Mar.02 7 HY62UF16406E Series DATA RETENTION TIMING DIAGRAM 1 DATA RETENTION MODE VCC 2.7V tCDR tR VIH VDR CS1>VCC-0.2V /CS1 VSS DATA RETENTION TIMING DIAGRAM 2 DATA RETENTION MODE VCC 2.7V tCDR tR CS2 VDR 0.4V VSS Rev.01 / Mar.02 CS2<0.2V 8 HY62UF16406E Series PACKAGE INFORMATION 48ball Fine Pitch Ball Grid Array Package (F) BOTTOM VIEW TOP VIEW B A A1 CORNER INDEX AREA 6 5 4 3 2 1 A A B C D C C1 E F G C1/2 H B1/2 B1 SIDE VIEW 5 E1 E2 C E SEATING PLANE A 4 r 3 D(DIAMETER) Symbol A B B1 C C1 D E E1 E2 r Rev.01 / Mar.02 Min. 5.9 6.9 0.40 0.8 0.30 - Typ. 0.75 3.75 6.0 5.25 7.0 0.45 0.9 0.55 0.35 - Max. 6.1 7.1 0.50 1.0 0.40 0.08 Note 1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION. 9 HY62UF16406E Series MARKING INFORMATION Package FBGA Marking Example H Y U F c s s t x x x x 6 4 0 6 E y w w p K O R x Index • HYUF6406E : Part Name • c : Power Consumption -D -S • ss : Low Low Power : Super Low Power : Speed - 55 - 70 : 55ns : 70ns • t : Temperature -I • y : Year (ex : 2 = year 2002, 3= year 2003) • ww : Work Week ( ex : 12 = work week 12 ) • p : Process Code • xxxxx : Lot No. • KOR : Origin Country Note - Capital Letter - Small Letter : Fixed Item : Non-fixed Item Rev.01 / Mar.02 : Industrial ( -40 ~ 85 °C ) 10