TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 D D D D D description The TMS28F512A Flash memory is a 65 536 by 8-bit (524 288-bit), programmable read-only memory that can be electrically bulk-erased and reprogrammed. It is available in 10 000 and 1 000 program / erase endurance cycle versions. FM PACKAGE ( TOP VIEW ) A12 A15 NC VPP VCC W NC Organization . . . 65 536 by 8 Bits All Inputs / Outputs TTL-Compatible VCC Tolerance ±10% Maximum Access / Minimum Cycle Time ’28F512A-10 100 ns ’28F512A-12 120 ns ’28F512A-15 150 ns ’28F512A-17 170 ns Industry-Standard Programming Algorithm 10 000 and 1 000 Program / Erase Cycles Latchup Immunity of 250 mA on all Input and Output Lines Low Power Dissipation ( VCC = 5.5 V ) – Active Write . . . 55 mW – Active Read . . . 165 mW – Electrical Erase . . . 82.5 mW – Standby . . . 0.55 mW (CMOS-Input Levels) Automotive Temperature Range – 40°C to 125°C 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 22 13 21 A14 A13 A8 A9 A11 G A10 E DQ7 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 D D D D PIN NOMENCLATURE A0 – A15 DQ0 – DQ7 E G NC VCC VPP VSS W Address Inputs Inputs (programming) / Outputs Chip Enable Output Enable No Internal Connection 5-V Power Supply 12-V Power Supply Ground Write Enable The TMS28F512A is offered in a 32-lead plastic leaded chip-carrier package with 1,25-mm (50-mil) lead spacing (FM suffix). The TMS28F512A is characterized for operation in temperature ranges of 0°C to 70°C (FML suffix), – 40°C to 85°C ( FME suffix), and – 40°C to 125°C ( FMQ suffix). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 device symbol nomenclature TMS28F512A - 12 C4 FM L Temperature Range Designator L = 0°C to 70°C E = – 40°C to 85°C Q = – 40°C to 125°C Package Designator FM = Plastic Leaded Chip Carrier Program / Erase Endurance C4 = 10 000 Cycles C3 = 1 000 Cycles Speed Designator -10 = 100 ns -12 = 120 ns -15 = 150 ns -17 = 170 ns 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 logic symbol† A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 E G W DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 22 24 31 13 0 FLASH EEPROM 65 536 × 8 A 0 65 535 15 G1 [PWR DWN] G2 1, 2 EN (READ) 1C3 (WRITE) A, 3D ∇4 A, Z4 14 15 17 18 19 20 21 † This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the N package. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 functional block diagram DQ0 – DQ7 8 VPP W Erase-Voltage Switch Input / Output Buffers State Control To Array Program / Erase Stop Timer Command Register Program-Voltage Switch STB Data Latch Chip-Enable and Output-Enable Logic E G STB A0 – A15 A d d r e s s 16 L a t c h 4 POST OFFICE BOX 1443 Column Decoder Column Gating Row Decoder 524 288-Bit Array Matrix • HOUSTON, TEXAS 77251–1443 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 operation Modes of operation are defined in Table 1. Table 1. Operation Modes FUNCTION† VPP‡ (1) E (22) G (24) A0 (12) A9 (26) W (31) DQ0 – DQ7 (13 – 15, 17 – 21) VPPL VPPL VIL VIL X X VIH VIH Data Out X Standby and Write Inhibit VPPL VIH VIL VIH X X Output Disable X X X Hi-Z Algorithm Selection Mode Algorithm-Selection VPPL VIL VIL VID VIH Read VPPH VPPH VIL VIL X VPPH VPPH VIH VIL VIL VIH X MODE Read Read Read / Write Output Disable Standby and Write Inhibit VIL VIH X Hi-Z Mfr Equivalent Code 89h Device Equivalent Code B8h X VIH VIH Data Out X X X X Hi-Z Hi-Z Write VIH X X Data In VIL † X can be VIL or VIH. ‡ VPPL ≤ VCC + 2 V; VPPH is the programming voltage specified for the device. For more details, see recommended operating conditions. read/ output disable When the outputs of two or more TMS28F512As are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of other devices. To read the output of the TMS28F512A, a low-level signal is applied to the E and G pins. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. standby and write inhibit Active ICC current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100 µA by applying a high CMOS level on E. In this mode, all outputs are in the high-impedance state. The TMS28F512A draws active current when it is deselected during programming, erasure, or program / erase verification. It continues to draw active current until the operation is terminated. algorithm-selection mode The algorithm-selection mode provides access to a binary code that identifies the correct programming and erase algorithms. This mode is activated when A9 is forced to VID. Two identifier bytes are accessed by toggling A0. All other addresses must be held low. A0 low selects the manufacturer equivalent code 89h, and A0 high selects the device equivalent code B8h, as shown in Table 2. Table 2. Algorithm-Selection Modes IDENTIFIER§ PINS A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX VIL VIH 1 0 0 0 1 0 0 1 89 Device Equivalent Code 1 0 1 § E = G = VIL, A1 – A8 = VIL, A9 = VID, A10 – A15 = VIL, VPP = VPPL. 1 1 0 0 0 B8 Manufacturer Equivalent Code programming and erasure In the erased state, all bits are at a logic one. Before erasing the device, all memory bits must be programmed to a logic zero. Afterwards, the entire chip is erased. At this point, the bits, now logic ones, can be programmed accordingly. Refer to the fastwrite- and fasterase-algorithms for further detail. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 command register The command register controls the program and erase functions of the TMS28F512A. The algorithm-selection mode can be activated using the command register in addition to the previously described method. When VPP is high, the contents of the command register and the function being performed can be changed. The command register is written to when E is low and W is pulsed low. The address is latched on the leading edge of the pulse, while the data is latched on the trailing edge. Accidental programming or erasure is minimized because two commands must be executed to invoke either operation. power supply considerations Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS to suppress circuit noise. Changes in current drain on VPP require it to have a bypass capacitor as well. Printed circuit traces for both power supplies should be appropriate to handle the current demand. command definitions See Table 3 for command definitions. Table 3. Command Definitions REQUIRED BUS CYCLES OPERATION† ADDRESS DATA OPERATION† ADDRESS DATA Read 1 Write X 00h Read RA RD Algorithm-Selection Mode 3 Write X 90h Read 0000 0001 89h B8h Set-Up-Erase / Erase 2 Write X 20h Write X 20h Erase Verify 2 Write EA A0h Read X EVD Set-Up-Program / Program 2 Write X 40h Write PA PD Program Verify 2 Write X C0h Read X PVD Reset 2 Write X FFh Write † Modes of operation are defined in Table 1 Legend: EA Address of memory location to be read during erase verify EVD Data read from location EA during erase verify PA Address of memory location to be programmed. Address is latched on the falling edge of W. PD Data to be programmed at location PA. Data is latched on the rising edge of W. PVD Data read from location PA during program verify RA Address of memory location to be read RD Data read from location RA during the read operation X FFh COMMAND FIRST BUS CYCLE SECOND BUS CYCLE read command Memory contents can be accessed while VPP is high or low. When VPP is high, writing 00h into the command register invokes the read operation. When the device is powered up, the default contents of the command register are 00h and the read operation is enabled. The read operation remains enabled until a different valid command is written to the command register. algorithm-selection-mode command The algorithm-selection mode is activated by writing 90h into the command register. The manufacturer equivalent code (89h) is identified by the value read from address location 0000h, and the device equivalent code (B8h) is identified by the value read from address location 0001h. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 set-up-erase / erase commands The erase algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the erase mode, write the set-up-erase command, 20h, into the command register. After the TMS28F512A is in the erase mode, writing a second erase command, 20h, into the command register invokes the erase operation. The erase operation begins on the rising edge of W and ends on the rising edge of the next W. The erase operation requires 10 ms to complete before the erase-verify command, A0h, can be loaded. Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase operation, the device enters an inactive state and remains inactive until another command is received. erase-verify command All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte can be verified by writing the erase-verify command, A0h, into the command register. This command causes the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on the falling edge of W. The erase-verify operation remains enabled until a command is written to the command register. To determine whether or not all the bytes have been erased, the TMS28F512A applies a margin voltage to each byte. If FFh is read from the byte, all bits in the designated byte have been erased. The erase-verify operation continues until all of the bytes have been verified. If FFh is not read from a byte, an additional erase operation needs to be executed. Figure 1 shows the combination of commands and bus operations for electrically erasing the TMS28F512A. set-up-program / program commands The programming algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the programming mode, write the set-up-program command, 40h, into the command register. The programming operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W, and data is latched internally on the rising edge of W. The programming operation begins on the rising edge of W and ends on the rising edge of the next W pulse. The program operation requires 10 µs for completion before the program-verify command, C0h, can be loaded. Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program operation, the device enters an inactive state and remains inactive until a command is received. program-verify command The TMS28F512A can be programmed sequentially or randomly because it is programmed one byte at a time. Each byte must be verified after it is programmed. The program-verify operation prepares the device to verify the most recently programmed byte. To invoke the program-verify operation, C0h must be written into the command register. The program-verify operation ends on the rising edge of W. While verifying a byte, the TMS28F512A applies an internal margin voltage to the designated byte. If the true data and programmed data match, programming continues to the next designated byte location; otherwise, the byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte programming. reset command To reset the TMS28F512A after set-up-erase command or set-up-program command operations without changing the contents in memory, write FFh into the command register two consecutive times. After executing the reset command, the device defaults to the read mode. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 Start Bus Operation Address = 00h Command Comments Initialize Address VCC = 5 V ± 10%, VPP = 12 V ± 5% Setup Standby Wait for VPP to ramp to VPPH (see Note A) X=1 Initialize pulse count Write Set-Up-Program Command Write Set-Up-Pr ogram Data = 40h Write Write Data Valid address / data Write Data Increment Address Wait = 10 µs X=X+1 Wait = 10 µs Standby Write Program-Verify Command Write Wait = 6 µs No Read Fail and Verify Byte ProgramVerify Data = C0h; ends program operation Standby Wait = 6 µs Read Read byte to verify programming; compare output to expected output X = 25? Yes Pass Interactive Mode No Last Address? Yes Write Read Command Power Down Apply VPPL Write Read Apply VPPL Standby Device Passed Device Failed NOTES: A. Refer to the recommended operating conditions for the value of VPPH. B. Refer to the recommended operating conditions for the value of VPPL. Figure 1. Programming Flowchart: Fastwrite Algorithm 8 Data = 00h; resets register for read operations POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Wait for VPP to ramp to VPPL (see Note B) TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 Fastwrite algorithm The TMS28F512A is programmed using the Texas Instruments fastwrite-algorithm previously shown in Figure 1. This algorithm programs in a nominal time of two seconds. Fasterase algorithm The TMS28F512A is erased using the Texas Instruments fasterase-algorithm shown in Figure 2. The memory array needs to be completely programmed (using the Fastwrite algorithm) before erasure begins. Erasure typically occurs in one second. parallel erasure To reduce total erase time, several devices can be erased in parallel. Since each Flash memory can erase at a different rate, every device must be verified separately after each erase pulse. After a given device has been successfully erased, the erase command should not be issued to this device again. All devices that complete erasure should be masked until the parallel erasure process is finished as shown in Figure 3. Examples of how to mask a device during parallel erase include driving the E pin high, writing the read command (00h) to the device when the others receive a set-up-erase or erase command, or disconnecting it from all electrical signals with relays or other types of switches. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 Start Preprogram All Bytes = 00h? No Bus Operation Command Comments Entire memory must = 00h before erasure Program All Bytes to 00h Use Fastwrite programming algorithm Yes Address = 00h Initialize addresses VCC = 5 V ± 10%, VPP = 12 V ± 5% Standby Wait for VPP to ramp to VPPH (see Note A) Setup X=1 Initialize pulse count Write Set-Up-Erase Command Write Set-Up-Er ase Data = 20h Write Erase Data = 20h Write Erase Command Wait = 10 ms X=X+1 Standby Wait = 10 ms Interactive Mode Write Erase-Verify Command Write Wait = 6 µs Erase-Veri fy Addr = Byte to verify; Data = A0h; ends the erase operation No Increment Address Read and Verify Byte Fail Pass No Standby Wait = 6 µs Read Read byte to verify erasure; compare output to FFh X = 1000? Yes Last Address? Yes Write Read Command Apply VPPL Apply VPPL Device Passed Device Failed Power Down Write Read Standby NOTES: A. Refer to the recommended operating conditions for the value of VPPH. B. Refer to the recommended operating conditions for the value of VPPL. Figure 2. Flash-Erase Flowchart: Fasterase Algorithm 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Data = 00h; resets register for read operations Wait for VPP to ramp to VPPL (see Note B) TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 Start Program All Devices to 00h X=1 Give Erase Command to All Devices D=1 Yes Mask Device #D Is Device #D Erased ? X=X+1 No D = n† ? Give Erase Command to All Unmasked Devices No D = D+1 Yes No Are All Devices Erased ? No X = 1000 ? Yes Yes Give Read Command to All Devices Give Read Command To All Devices All Devices Pass Finished With Errors † n = number of devices being erased. Figure 3. Parallel-Erase Flow Diagram POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V Input voltage range (see Note 2): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V Operating free-air temperature range during read / erase / program, TA FML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C FME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C FMQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40° C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to VSS. 2. The voltage on any input pin can undershoot to – 2.0 V for periods less than 20 ns. 3. The voltage on any output pin can overshoot to 7.0 V for periods less than 20 ns. recommended operating conditions MIN VCC Supply voltage VPP Supply voltage VID Voltage level on A9 for algorithm-selection mode VIH High level dc input voltage High-level VIL Low level dc input voltage Low-level TA 12 During write / read / flash erase During read only ( VPPL ) 11.4 11.5 TTL CMOS POST OFFICE BOX 1443 TYP MAX 2 TTL VCC – 0.5 – 0.5 CMOS GND – 0.2 UNIT 5 55 5.5 V VCC + 2 12.6 V 12 13 V 0 During write / read / flash erase ( VPPH) Operating free-air temperature 45 4.5 VCC + 0.5 VCC + 0.5 0.8 GND + 0.2 FML suffix 0 FME suffix – 40 85 FMQ suffix – 40 125 • HOUSTON, TEXAS 77251–1443 V V V 70 °C TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VOH High level output voltage High-level IOH = – 2.5 mA IOH = – 100 µA VOL Low level output voltage Low-level IOL = 5.8 mA IOL = 100 µA 0.45 IID A9 algorithm-selection-mode current A9 = VID max 200 II Input current (leakage) IO Output current (leakage) All except A9 A9 2.4 UNIT V VCC – 0.4 0.1 ±1 VI = 0 V to 5.5 V VI = 0 V to 13 V ± 200 V µA µA VO = 0 V to VCC VPP = VPPH, Read mode ±10 µA 200 µA IPP1 VPP supply current (read / standby) VPP = VPPL ±10 µA IPP2 VPP supply current (during program pulse) (see Note 4) VPP = VPPH 30 mA IPP3 VPP supply current (during flash erase) (see Note 4) VPP = VPPH 30 mA IPP4 VPP supply current (during program / erase-verify) (see Note 4) VPP = VPPH 5.0 mA ICCS VCC supply y current (standby) 1 mA TTL-input level CMOS-input level VCC = 5.5 V, E = VIH VCC = 5.5 V, E = VCC 100 µA 30 mA ICC1 VCC supply current (active read) VCC = 5.5 V, E = VIL, f = 6 MHz, IOUT = 0 mA ICC2 VCC average supply current (active write) (see Note 4) VCC = 5.5 V, E = VIL, Programming in progress 10 mA ICC3 VCC average supply current (flash erase) (see Note 4) VCC = 5.5 V, E = VIL, Erasure in progress 15 mA ICC4 VCC average supply current (program / erase-verify) (see Note 4) VCC = 5.5 V, E = VIL, VPP = VPPH, Program / erase-verify in progress 15 mA NOTE 4: Characterization data available. capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz† PARAMETER CI TEST CONDITIONS Input capacitance CO Output capacitance † Capacitance measurements are made on sample basis only. POST OFFICE BOX 1443 VI = 0 V, f = 1 MHz VO = 0 V, f = 1 MHz • HOUSTON, TEXAS 77251–1443 MIN MAX UNIT 6 pF 12 pF 13 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature TEST CONDITIONS ALTERNATE SYMBOL ’28F512A-10 MIN MAX ’28F512A-12 ’28F512A-15 ’28F512A-17 MIN MIN MIN MAX MAX MAX UNIT ta(A) Access time from address, A tAVQV 100 120 150 170 ns ta(E) Access time from E tELQV 100 120 150 170 ns ta(G) Access time from G tGLQV 45 50 55 60 ns tc(R) Cycle time, read tAVAV 100 120 150 170 ns td(E) Delay time, E low to low-Z output tELQX 0 0 0 0 ns td(G) Delay time, G low to low-Z output tGLQX 0 0 0 0 ns tdis(E) Chip disable time to Hi-Z output tEHQZ 0 55 0 55 0 55 0 55 ns tdis(G) Output disable time to Hi-Z output tGHQZ 0 30 0 30 0 35 0 35 ns th(D) Hold time, data valid from address, E, or G‡ tAXQX 0 0 0 0 ns trec(W) Write recovery time before read tWHGL 6 6 6 6 µs CL = 100 pF, One Series 74 TTL Load, Input tr ≤ 20 ns,, Input tf ≤ 20 ns ‡ Whichever occurs first 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 timing requirements–write/erase/program operations ALTERNATE SYMBOL tc(W) tc(W)PR Cycle time, write using W tc(W)ER th(A) Cycle time, erase operation th(E) th(WHD) Hold time, E tsu(A) tsu(D) Setup time, address tsu(E) tsu(EHVPP) Setup time, E before W tsu(VPPEL) trec(W) Setup time, VPP to E low trec(R) tw(W) Recovery time, read before W tw(WH) tr(VPP) Pulse duration, W high tf(VPP) Fall time, VPP Cycle time, programming operation Hold time, address Hold time, data valid after W high Setup time, data Setup time, E high to VPP ramp Recovery time, W before read Pulse duration, W (see Note 5) Rise time, VPP Cycle time, write using W tc(W)ER th(A) Cycle time, erase operation th(E) th(WHD) Hold time, E tsu(A) tsu(D) Setup time, address tsu(E) tsu(EHVPP) Setup time, E before W tsu(VPPEL) trec(W) Setup time, VPP to E low trec(R) tw(W) Recovery time, read before W tw(WH) tr(VPP) Pulse duration, W high Cycle time, programming operation Hold time, address Hold time, data valid after W high Setup time, data Setup time, E high to VPP ramp Recovery time, W before read Pulse duration, W (see Note 5) Rise time, VPP tf(VPP) Fall time, VPP NOTE 5: Rise / fall time ≤ 10 ns POST OFFICE BOX 1443 NOM MAX ’28F512A - 12 MIN NOM MAX UNIT tAVAV tWHWH1 tWHWH2 100 120 ns 10 10 µs tWLAX tWHEH 55 tWHDX tAVWL 9.5 10 9.5 10 ms 60 ns 0 0 ns 10 10 ns 0 0 ns tDVWH tELWL 50 50 ns 20 20 ns tEHVP tVPEL 100 100 ns 1.0 1.0 µs tWHGL tGHWL 6 6 µs 0 0 µs tWLWH tWHWL 60 60 ns 20 20 ns tVPPR tVPPF 1 1 µs 1 1 µs ALTERNATE SYMBOL tc(W) tc(W)PR ’28F512A - 10 MIN ’28F512A - 15 MIN NOM MAX ’28F512A - 17 MIN NOM MAX UNIT tAVAV tWHWH1 tWHWH2 150 170 ns 10 10 µs tWLAX tWHEH 60 70 ns 0 0 ns tWHDX tAVWL 10 10 ns 0 0 ns tDVWH tELWL 50 50 ns 20 20 ns tEHVP tVPEL 100 100 ns 1.0 1.0 µs tWHGL tGHWL 6 6 µs 0 0 µs tWLWH tWHWL tVPPR 60 60 ns 20 20 ns 1 1 µs tVPPF 1 1 µs 9.5 • HOUSTON, TEXAS 77251–1443 10 9.5 10 ms 15 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 timing requirements — alternative E-controlled writes ALTERNATE SYMBOL ’28F512A - 10 MIN ’28F512A - 12 MAX MIN MAX ’28F512A - 15 MIN MAX ’28F512A - 17 MIN MAX UNIT tc(W) Cycle time, write using E tAVAV 100 120 150 170 ns tc(E)PR Cycle time, programming operation tEHEH 10 10 10 10 µs tELAX tEHDX 75 80 80 90 ns 10 10 10 10 ns tEHWH tAVEL 0 0 0 0 ns 0 0 0 0 ns 50 50 50 50 ns 0 0 0 0 ns th(EA) th(ED) Hold time, address th(W) tsu(A) Hold time, W tsu(D) tsu(W) Setup time, data Setup time, W before E tDVEH tWLEL tsu(VPPEL) Setup time, VPP to E low tVPEL 1.0 1.0 1.0 1.0 µs trec(E)R Recovery time, write using E before read tEHGL 6 6 6 6 µs trec(E)W Recovery time, read before write using E tGHEL 0 0 0 0 µs tELEH tEHEL 70 70 70 80 ns 20 20 20 20 ns tw(E) tw(EH) Hold time, data Setup time, address Pulse duration, write using E Pulse duration, write, E high PARAMETER MEASUREMENT INFORMATION 2.08 V RL = 800 Ω Output Under Test CL = 100 pF (see Note A) LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance. 2.4 V 0.45 V 2V 0.8 V 2V 0.8 V VOLTAGE WAVEFORMS Figure 4. Load Circuit and Voltage Waveforms AC testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made at 2 V for logic high and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS as close as possible to the device pins. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 PARAMETER MEASUREMENT INFORMATION tc(R) Address Valid A0 – A15 ta(A) E ta(E) tdis(E) G trec(W) ta(G) W td(E) DQ0 – DQ7 td(G) Hi-Z tdis(G) th(D) Output Valid Hi-Z Figure 5. Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 PARAMETER MEASUREMENT INFORMATION Program Command Latch ProgramAddress Verify and Data Programming Command Power Up Set-UpProgram and Standby Command Program Verification Standby / Power Down A0 – A15 tc(W) tc(W) tc(W) tsu(A) tc(R) th(A) th(A) tsu(A) E tsu(E) tsu(E) th(E) tdis(E) tsu(E) th(E) G th(E) tc(W)PR trec(R) tw(WH) tdis(G) trec(W) W th(WHD) th(WHD) tw(W) tw(W) tsu(D) tsu(D) DQ0 – DQ7 th(WHD) tsu(D) Data In Data In = C0h Valid Data-Out tsu(VPPEL) VPPH VPPL tf(VPP) tr(VPP) Figure 6. Write-Cycle Timing 18 td(E) ta(E) 5V 0V VPP td(G) tw(W) HI-Z Data In = 40h VCC th(D) ta(G) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 PARAMETER MEASUREMENT INFORMATION Program Command Latch ProgramAddress Verify and Data Programming Command Power Up Set-UpProgram and Standby Command Program Verification Standby / Power Down A0 – A15 tc(W) tc(W) tc(W) tsu(A) th(EA) tc(R) th(EA) tsu(A) W tsu(W) tsu(W) tdis(G) tsu(W) th(W) th(W) th(W) G tc(w)B trec(E)W tdis(E) trec(E)R tw(EH) E tw(E) tsu(D) DQ0 – DQ7 th(D) th(ED) th(ED) tw(E) tsu(D) th(ED) td(G) tw(E) tsu(D) Hi-Z Data In Data In = 40h VCC ta(G) Data In = C0h td(E) ta(E) Valid Data-Out 5V 0V tsu(VPPEL) VPPH VPP VPPL tf(VPP) tr(VPP) Figure 7. Write-Cycle (Alternative E-Controlled Writes) Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 PARAMETER MEASUREMENT INFORMATION Power Up Set-UpErase and Standby Command Erase Command EraseVerify Command Erasing Erase Standby / Verification Power Down A0 – A15 tc(W) tc(W) tc(W) tc(R) th(A) tsu(A) E tsu(E) tsu(E) tsu(E) th(E) th(E) G tw(WH) trec(R) tdis(E) th(E) tc(E)B trec(W) tdis(G) W th(D) th(WHD) th(WHD) tw(W) tw(W) tsu(D) DQ0 – DQ7 tsu(D) th(WHD) ta(G) td(G) tw(W) tsu(D) Hi-Z Data In = 20h Data In = 20h Data In = A0h td(E) ta(E) Valid Data-Out 5V VCC 0V tsu(VPPEL) VPPH VPP VPPL tf(VPP) tr(VPP) Figure 8. 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