TI TMS29F010

TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
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D
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description
The TMS29F010 is a 131 072 by 8-bit
(1048 576-bit), 5-V single-supply, programmable
read-only memory device that can be electrically
erased and reprogrammed. This device is
organized as eight independent 16K-byte sectors
and is offered with access times between 70 ns
and 120 ns.
FM PACKAGE
( TOP VIEW )
A12
A15
A16
NC
VCC
W
NC
D
D
Single Power Supply
5 V ± 10%
Organization . . . 131 072 by 8 Bits
Eight Equal Sectors of 16K Bytes
– Any Combination of Sectors Can Be
Erased
– Any Combination of Sectors Can Be
Marked as Read-Only
Compatible With JEDEC EEPROM
Command Set
Fully Automated On-Chip Erase and
Byte-Program Operations
100 000 Program / Erase Cycles
Compatible With JEDEC Byte-Wide Pinouts
Low-Current Consumption
– Active Read . . . 20 mA Typical
– Active Program / Erase . . . 30 mA Typical
All Inputs/Outputs TTL-Compatible
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
A14
A13
A8
A9
A11
G
A10
E
DQ7
14 15 16 17 18 19 20
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
D
PIN NOMENCLATURE
A[0:16]
DQ[0:7]
E
G
VCC
VSS
W
NC
Address Inputs
Inputs (programming) / Outputs
Chip Enable
Output Enable
5-V Power Supply
Ground
Write Enable
No Connection
An on-chip state machine controls the program and erase operations. The embedded byte-program and
sector / chip-erase functions are fully automatic. The command set is compatible with that of JEDEC 1M-bit
EEPROMs. Data-protection of any sector combination is accomplished using a hardware sector-protection
feature.
Device operations are selected by writing JEDEC-standard commands into the command register using
standard microprocessor write timings. The command register acts as an input to an internal-state machine that
interprets the commands, controls the erase and programming operations, outputs the status of the device,
outputs data stored in the device, and outputs the device algorithm-selection code. On initial power-up
operation, the device defaults to the read mode.
The TMS29F010 is offered in a 32-pin plastic leaded chip carrier (FM suffix) using 1.27-mm (50-mil) lead pitch.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
device symbol nomenclature
TMS29F010
-10
C5
FM
L
Temperature Range Designator
L
= Commercial (0°C to 70°C)
E
= Extended (– 40°C to 85°C)
Q = Automotive (– 40°C to 125°C)
Package Designator
FM = Plastic Leaded Chip Carrier
Program / Erase Endurance
C5 = 100 000 Cycles
Speed Designator
- 70 = 70 ns
- 90 = 90 ns
- 10 = 100 ns
- 12 = 120 ns
2
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TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
block diagram
DQ0 – DQ7
VCC
VCC Detector
VSS
Input/Output Buffers
Timer
Command Register
Erase-Voltage
Generator
W
State Control
Program-Voltage
Generator
Data Latch
E
Chip-Enable
Output-Enable
Logic
G
A
d
d
r
e
s
s
A0 – A16
L
a
t
c
h
Column Decoder
Column-Gating
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
Row-Decoder
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
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3
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
memory sector architecture
1FFFFh
16K-Byte Sector 7
1C000h
1BFFFh
16K-Byte Sector 6
18000h
17FFFh
16K-Byte Sector 5
14000h
13FFFh
16K-Byte Sector 4
10000h
0FFFFh
16K-Byte Sector 3
0C000h
0BFFFh
16K-Byte Sector 2
08000h
07FFFh
16K-Byte Sector 1
04000h
03FFFh
16K-Byte Sector 0
00000h
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
4
A16
0
0
0
0
1
1
1
1
POST OFFICE BOX 1443
A15
0
0
1
1
0
0
1
1
A14
0
1
0
1
0
1
0
1
Address
00000h –
04000h –
08000h –
0C000h –
10000h –
14000h –
18000h –
1C000h –
• HOUSTON, TEXAS 77251–1443
Range
03FFFh
07FFFh
0BFFFh
0FFFFh
13FFFh
17FFFh
1BFFFh
1FFFFh
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
operation
Table 1 summarizes the operation modes.
Table 1. Operation Modes
FUNCTIONS†
MODE
E
G
W
A0
A1
A6
A9
DQ0 – DQ7
VIL
VIH
VIH
VIH
A0
A1
A6
A9
Data out
Output disable
VIL
VIL
X
X
X
X
Hi-Z
Standby and write inhibit
VIH
X
X
X
X
X
X
Hi-Z
Algorithm-selection
g
mode
VIL
VIL
VIH
VIL
X
VID
Write‡
VIL
VIH
VIL
VIH
A0
A1
A6
A9
Data in
Sector-protect§
VIL
VIL
VID
VIL
VIL
VIH
X
X
X
Sector-protect verify§
VIL
VIH
VIL
VID
VID
Data out
Sector-unprotect§
(see Note 1)
VID
VID
VIL
X
X
VIL
VID
X
Sector-unprotect verify§
VIL
VIL
VIL
VIH
VIL
See
Note 2
VIH
See
Note 2
VIH
See
Note 2
VID
See
Note 2
Data out
Erase operations
VIH
See
Note 2
Read
VIL
Manufacturer-equivalent code
01h
Device-equivalent code 20h
X
See Note 2
† X can be VIL or VIH.
‡ See Table 3 for valid address and data during write (byte program).
§ Operation at VCC = 5.0 V and TA = 25°C.
NOTES: 1. Address pins A7, A12 = VIH.
2. See Figure 6 through Figure 9.
read mode
To read the output of the TMS29F010, a low-level logic signal is applied to the E and G pins. When two or more
TMS29F010 devices are connected in parallel, the output of any one device can be read without interference.
The E pin is power control and is used for device selection. The G pin is output control and is used to gate the
data output onto the bus from the selected device.
The address-access time (tAVQV) is the delay from stable address to valid output data. The chip-enable access
time (tELQV) is the delay from E = VIL and stable addresses to valid output data. The output-enable access time
(tGLQV) is the delay from G = VIL to valid output data when E = VIL and addresses are stable for at least the
duration of tAVQV – tGLQV.
standby mode
The ICC supply current is reduced by applying a logic-high level on E to enter the standby mode. In the standby
mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on E reduces the
current to 100 µA maximum. Applying a TTL logic-high level on E reduces the current to 1 mA maximum.
If the TMS29F010 is deselected during erasure or programming, the device continues to draw active current
until the operation is complete.
output disable
When either G = VIH or E = VIH, output from the device is disabled and the output pins (DQ0 – DQ7) are placed
in the high-impedance state.
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TMS29F010
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SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
algorithm-selection mode
The algorithm-selection mode provides access to a binary code that matches the device with its proper
programming- and erase-command operations. This mode is activated when VID (11.5 V to 12.5 V) is placed
on address pin A9. Address pin A1 must be logic-low. Two bytes of code are accessed by toggling address pin
A0 from VIL to VIH. All other address pins can be logic-low or logic-high.
The algorithm-selection code can also be read by using the command register. This is useful when VID is not
available to be placed on address pin A9. Table 2 shows the binary algorithm-selection codes for the
TMS29F010.
Table 2. Algorithm-Selection Codes†
ALGORITHM SELECTION
Byte 0
Byte 1
† A1 = VIL, E = G = VIL
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
0
0
0
0
0
0
0
0
1
01h
1
0
0
1
0
0
0
0
0
20h
erasure and programming
Erasure and programming of the TMS29F010 are accomplished by writing a sequence of commands using
standard microprocessor-write timings. The commands are written to a command register and input to the
command-state machine (CSM). The CSM interprets the command entered and initiates program and erase
operations as instructed. The CSM acts as the interface between the write-state machine (WSM) and the
external chip operations. The WSM controls all voltage generation, pulse generation, preconditioning, and
verification of the memory contents. Program and sector/chip-erase functions are fully automatic. Once the end
of a program or erase operation is reached, the device internally resets to the read mode. If VCC drops below
the low-voltage-detect level (VLKO), any operation in progress is aborted and the device resets to the read mode.
If a byte-program or chip-erase operation is in progress, additional program/erase commands are ignored until
the operation ends.
command definitions
Device operating modes are selected by writing specific address and data sequences into the command
register. Table 3 defines the valid command sequences. Writing incorrect address and data values or writing
them in the incorrect sequence causes the device to reset to the read mode. The command register does not
occupy an addressable memory location. The register stores the command sequence, along with the address
and data needed by the memory array. Commands are written by setting E = VIL and G = VIH, and bringing W
from VIH to VIL. Addresses are latched on the falling edge of W and data is latched on the rising edge of W.
Holding W = VIL and toggling E is an alternative method. See the byte-program and chip/sector-erase sections
for a more complete description.
6
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TMS29F010
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command definitions (continued)
Table 3. Command Definitions†
COMMAND
Read‡
BUS
CYCLES
1ST CYCLE
ADDR DATA
2ND CYCLE
ADDR DATA
3RD CYCLE
ADDR DATA
4TH CYCLE
ADDR DATA
5TH CYCLE
ADDR DATA
6TH CYCLE
ADDR DATA
1
RA
2
XXXXh F0h
RA
4
5555h AAh
2AAAh 55h
5555h F0h
RA
RD
Algorithm selection
4
5555h AAh
2AAAh 55h
5555h 90h
RA
RD
Byte program
4
5555h AAh
2AAAh 55h
5555h A0h
PA
PD
Chip erase
6
5555h AAh
2AAAh 55h
5555h 80h
5555h AAh
2AAAh 55h
5555h 10h
Sector erase
6
5555h AAh
2AAAh 55h
5555h 80h
5555h AAh
2AAAh 55h
SA 30h
Reset/Read§
RD
RD
RA = Address of the location to be read
PA = Address of the location to be programmed
SA = Address of the sector to be erased
Addresses A14, A15, and A16 select one of eight sectors
RD = Data to be read at the selected address location
PD = Data to be programmed at the selected address location
† Address pins A15 and A16 = VIL or VIH for all bus-cycle addresses except for program address (PA), sector address (SA), and read address
(RA).
‡ No command cycles are required when the device is in read mode.
§ The reset command is required to return to the read mode when the device is in the algorithm-selection mode or if DQ5 goes high.
reset/read command
The read mode is activated by writing either of the two reset command sequences into the command register.
The device remains in this mode until another valid command sequence is input into the command register.
Memory data is available in the read mode and can be read with standard microprocessor read-cycle timing.
On power up, the device defaults to the read mode; therefore, a reset command sequence is not required and
memory data is available.
algorithm-selection command
The algorithm-selection command allows access to a binary code that matches the device with the proper
programming- and erase-command operations. After writing the three-bus-cycle command sequence, the first
byte of the algorithm-selection code (01h) can be read from address XX00h. The second byte of the code (20h)
can be read from address XX01h (see Table 2). This mode remains in effect until another valid command
sequence is written to the device.
Sector protection can be determined by using the algorithm-selection command. After issuing the three
bus-cycle command sequence, the sector-protection status can be read on DQ0. Set address pins A0 = VIL and
A1 = VIH, and then the sector address pins A14, A15, and A16 select the sector to be checked. The remaining
address pins can be VIL or VIH. If the sector that is selected is protected, DQ0 outputs a 1 state, and, if the sector
selected is not protected, DQ0 outputs a 0 state. This mode remains in effect until another valid command
sequence is written to the device.
byte-program command
Byte programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the
program-setup state, and the fourth bus cycle loads the address location and the data to be programmed into
the device. The addresses are latched on the falling edge of W and the data is latched on the rising edge of W
in the fourth bus cycle. The rising edge of W starts the byte-program operation. The embedded
byte-programming function automatically provides needed voltage and timing to program and to verify the cell
margin. Any further commands written to the device during the program operation are ignored.
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TMS29F010
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byte-program command (continued)
Programming can be performed at any address location in any order, resulting in logic 0s being programmed
into the device. Attempting to program a logic 1 into a bit that has been previously programmed to a logic 0
causes the internal pulse counter to exceed the pulse-count limit. This sets the exceed-timing-limit indicator
(DQ5) to a logic-high state. Only an erase operation can change bits from logic 0s to logic 1s. When erased,
all bits become logic 1. Figure 3 shows a flow chart of the typical byte-programming operation.
The status of the device during the automatic programming operation can be monitored for completion using
the data-polling feature or the toggle-bit feature. See the operation-status section for a full description.
chip-erase command
Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup
state, and the next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip-erase command.
This command sequence is required to ensure that the memory contents are not erased accidentally. The rising
edge of W starts the chip-erase operation. Any further commands written to the device during the chip-erase
operation are ignored.
The embedded chip-erase function automatically provides voltage and timing needed to program and verify all
the memory cells prior to electrical erase and then erases and verifies the cell margin automatically. The user
is not required to program the memory cells prior to erase. The status of the device during the automatic
chip-erase operation can be monitored for completion using the data-polling feature or the toggle-bit feature.
See the operation status section for a full description. Figure 6 shows a flow chart for the typical chip-erase
operation.
sector-erase command
Sector erase is a six-bus-cycle command sequence. The first three bus cycles cause the device to go into the
erase-setup state, and the next two bus cycles unlock the erase mode. The sixth bus cycle loads the
sector-erase command and the sector-address location to be erased. Any address location within the desired
sector can be used. The addresses are latched on the falling edge of W and the sector-erase command (30h)
is latched on the rising edge of W in the sixth bus cycle. After a delay of 80 µs from the rising edge of W, the
sector-erase operation begins on the selected sector(s).
Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For
each additional sector selected for erase, another bus cycle is issued. The bus cycle loads the next
sector-address location and the sector-erase command. The time between the end of the previous bus cycle
and the start of the next bus cycle must be less than 80 µs—otherwise, the new sector location is not loaded.
A time delay of 80 µs from the rising edge of the last W cycle starts the sector-erase operation. If there is a falling
edge of W within the 80-µs time delay, the timer is reset.
One to eight sector-address locations can be loaded in any order. The state of the delay timer can be monitored
using the sector-erase-delay indicator (DQ3). If DQ3 is logic low, the time delay has not expired. See the
operation-status section for a full description.
Any command other than sector-erase (30h) written to the device during the sector-erase operation causes the
device to exit the sector-erase mode; meanwhile, the contents of the sector(s) selected for erase are no longer
valid. To complete the sector-erase operation, the sector-erase command sequence must be repeated.
The embedded sector-erase function automatically provides needed voltage and timing to program and to verify
all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically.
Programming the memory cells prior to erase is not required. The status of the device during the automatic
sector-erase operation can be monitored for completion by using the data-polling feature or the toggle-bit
feature. See the operation-status section for a full description. Figure 8 shows a flow chart of the typical
sector-erase operation.
8
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TMS29F010
131072 BY 8-BIT
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operation status
status bit definitions
During operation of the embedded program and erase functions, the status of the device can be determined
by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle-bit (DQ6) require multiple
successive reads to observe a change in the state of the designated output. Table 4 defines the values of the
status flags.
Table 4. Operation Status Flags†
Device Operation‡
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Byte-programming in progress
DQ7
T
0
X
0
X
X
X
Byte-programming exceed time limit
DQ7
T
1
X
0
X
X
X
Byte-programming complete
D
D
D
D
D
D
D
D
Sector / chip-erase in progress
0
T
0
X
1
X
X
X
Sector / chip-erase exceed time limit
0
T
1
X
1
X
X
X
Sector / chip-erase complete
1
1
1
1
† T= toggle, D = data, X = data undefined, DQ7 = complement of data written to DQ7
‡ DQ4, DQ2, DQ1, DQ0 are reserved for future use.
1
1
1
1
data-polling (DQ7)
The data-polling status function outputs the complement of the data latched into the DQ7 data register while
the write-state machine (WSM) is engaged in a program or erase operation. Data bit DQ7 changes from
complement to true to indicate the end of an operation. Data polling is available only during the
byte-programming, chip-erase, sector-erase, and sector-erase timing delay. Data polling is valid after the rising
edge of W in the last bus cycle of the command sequence loaded into the command register. Figure 10 shows
a flow chart of the data-polling operation.
During a byte-program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at
the selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the
program data register. During erase operations, reading DQ7 outputs a logic 0, and upon completion, reading
DQ7 outputs a logic 1. Also, data polling must be performed at a sector address that is within a sector being
erased; otherwise, the status is not valid. When using data polling, the address must remain stable throughout
the operation.
During a data-polling read, while G is low, DQ7 can change asynchronously with the other DQs. Depending on
the read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. The data on
DQ0–DQ7 is valid with a subsequent read of the device. See Figure 11 for the data-polling timing diagram.
toggle-bit (DQ6)
The toggle-bit status function outputs data on DQ6 that toggles between logic 1 and logic 0 while the WSM is
engaged in a program or erase operation. When toggle-bit DQ6 stops toggling after two consecutive reads to
the same address, the operation is complete. The toggle bit is available only during the byte-programming,
chip-erase, sector-erase, and sector-erase timing delay. Toggle bit data is valid after the rising edge of W in the
last bus cycle of the command sequence loaded into the command register. Figure 12 shows a flow chart for
the toggle-bit status-read algorithm. Depending on the read timing, DQ6 can stop toggling while other DQ pins
are still invalid. The data on DQ0–DQ7 is valid with a subsequent read of the device. Figure 13 shows the
toggle-bit timing diagram.
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TMS29F010
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exceed-time-limit (DQ5)
The program and erase operations use an internal pulse counter to limit the number of pulses applied. If the
pulse count limit is exceeded, DQ5 is set to a logic 1, indicating that the program or erase operation has failed.
DQ7 will not change from complemented data to true data and DQ6 will not stop toggling when read. To continue
operation, the device must be reset.
The exceed-time-limit condition occurs when attempting to program a logic 1 into a bit that has been
programmed previously to a logic 0. Only an erase operation can change bits from logic 0 to logic 1. After reset,
the device is functional and can be erased and reprogrammed.
sector-load-timer (DQ3)
The sector-load-timer status bit, DQ3, is used to determine if the time to load additional sector addresses has
expired. After completion of a sector-erase command sequence, DQ3 remains at a logic 0 for 80 µs. This
indicates that another sector-erase command sequence can be issued. DQ3 set at a logic 1 indicates that the
delay has expired and attempts to issue additional sector-erase commands are ignored. See the sector-erase
command section for a description.
The data-polling bit and toggle bit are valid during the 80-µs time delay and can be used to determine if a valid
sector-erase command has been issued. To ensure additional sector-erase commands have been accepted,
the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic
low on both reads, then the additional sector-erase command was accepted.
data protection
hardware-sector protect feature
This feature disables both programming and erase operations on any combination of one to eight sectors.
Commands to program or erase a protected sector do not change the data contained in the sector. The
data-polling and toggle bits operate for 2 µs to 100 µs and then return to valid data. This feature is enabled using
high-voltage VID (11.5 V to 12.5 V) on address pin A9 and control pin G, and VIL on control pin E. Figure 14 shows
a flow chart of the sector-protect operation.
The device is delivered with all sectors unprotected; however, sector-unprotect mode is available to unprotect
protected sectors. Figure 16 is a flow chart of the sector-unprotect operation.
sector-protect operation
The sector-protect mode is activated when VCC = 5.0 V (and operation at TA = 25°C), W = VIH, E = VIL, and
address pin A9 and control pin G are forced to VID. The sector-select address pins A14, A15, and A16 are used
to select the sector to be protected. Address pins A0–A8, A10–A13, and I/O pins DQ0 – DQ7 must be stable and
can be VIL or VIH. Once the addresses are stable, W is pulsed low for 100 µs. The operation begins on the falling
edge of W and terminates on the rising edge of W. Figure 15 shows a timing diagram of the sector-protect
operation.
sector-protect verify
Verification of sector protection is activated when VCC = 5.0 V (and operation at TA = 25°C), W = VIH, G = VIL,
E = VIL, and address pin A9 = VID. Address pins A0 and A6 are set to VIL, and A1 is set to VIH. The sector-address
pins A14, A15, and A16 select the sector to be verified. The other address pins can be VIL or VIH. If the sector
selected is protected, the DQs output 01h, and if the sector selected is not protected, the DQs output 00h.
10
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TMS29F010
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SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
sector unprotect operation
Prior to the sector-unprotect operation, all sectors should be protected using the sector-protect mode. Sector
unprotect is activated when VCC = 5.0 V (and operation at TA = 25°C), W = VIH, and address pin A9 and control
pins G and E are forced to VID. Address pin A6 = VIL, and pins A7 and A12 are set to VIH. The sector-select
address pins A14, A15, and A16 can be VIL or VIH. All eight sectors are unprotected in parallel, and once the
inputs are stable, W is pulsed low for 10 ms. The unprotect operation begins on the falling edge of W and
terminates on the rising edge of W. Figure 17 shows a timing diagram of the sector-unprotect operation.
sector-unprotect verify
Verification of sector-unprotect is accomplished when VCC = 5.0 V (and operation at TA = 25°C), W = VIH,
G = VIL, E = VIL, and address pin A9 = VID, and then select the sector to be verified. Address pins A1 and A6
are set to VIH while pin A0 is set to VIL. The other address pins can be VIH or VIL. If the sector that is selected
is protected, the DQs output 01h and if the sector is not protected, the DQs output 00h.
low VCC write lockout
During power up and power down, write operations are locked out for VCC less than VLKO. If VCC < VLKO, the
command input is disabled and the device is reset to the read mode. On power up, if E = VIL, W = VIL, and
G = VIH, the device does not accept commands on the rising edge of W. The device automatically powers up
in the read mode.
glitching
Pulses of less than 5 ns (typical) on G, W, or E do not issue a write cycle.
power supply considerations
Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS to suppress circuit noise.
Printed circuit traces to VCC should be appropriate to handle the current demand and minimize inductance.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
absolute maximum ratings over operating ambient temperature range (unless otherwise noted)†
Voltage range with respect to ground:
Supply voltage range, VCC (see Note 3) . . . . . . . . . . . . . . . . . . . . . . –2.0 V to + 7.0 V
All pins except A9, E, G (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to + 7.0 V
A9, E, G (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to + 14.0 V
Ambient temperature range during read / erase / program, TA
Commercial (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Extended (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Automotive (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 3. Minimum dc voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for
periods of up to 20 ns. Maximum dc voltage on input and I/O pins is VCC + 0.5 V. During voltage transitions, input and I/O pins may
overshoot to VCC + 2.0 V for periods up to 20 ns.
4. Minimum dc input voltage on A9, E, and G pins is –0.5 V. During voltage transitions, A9, E, and G may undershoot VSS to –2.0 V
for periods of up to 20 ns. Maximum dc input voltage on A9, E, and G pins is +12.5 V, which may overshoot to +14.0 V for periods
up to 20 ns.
recommended operating conditions
VCC
Supply voltage
Commercial (L)
TA
12
Ambient temperature during read / erase / program
POST OFFICE BOX 1443
MIN
NOM
MAX
4.5
5
5.5
0
70
Extended (E)
– 40
85
Automotive (Q)
– 40
125
• HOUSTON, TEXAS 77251–1443
UNIT
V
°C
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
electrical dc characteristics over recommended ranges of supply voltage and ambient
temperature
PARAMETER
TEST CONDITIONS
VIH
High level dc input voltage
High-level
VIL
Low level dc input voltage
Low-level
VID
Algorithm-selection and sector-protect/unprotect
input voltage
VLKO
Low VCC lock-out voltage (see Note 5)
High-level dc output voltage
Low-level dc output voltage
g
(see Note 6)
II
IO
Input current (leakage)
IID
ICC1
High-voltage load current
ICC2
ICC3
CMOS
CMOS
TTL
CMOS
Output current (leakage)
VCC active current (see Note 7)
VCC active current (see Note 8)
VCC supply current (standby)
0.7*VCC
–0.5
TTL
CMOS
VOL
2
CMOS
TTL
VOH
MIN
TTL
TTL-input level
VCC = 5.0 V
MAX
UNIT
VCC + 0.5
VCC + 0.5
V
0.8
–0.5
0.8
11.5
12.5
V
V
3.2
V
VCC = VCC MIN†
VCC = VCC MIN
IOH = – 2.5 mA
IOH = – 100 µA
VCC = VCC MIN
VCC = VCC MIN
IOH = – 2.5 mA
IOL = 5.8 mA
VCC = VCC MIN
VCC = VCC MAX
IOL = 5.8 mA
VI =VSS to VCC
VCC = VCC MAX
VCC = VCC MAX
VO = VSS to VCC
A9 = 12.5 V
50
µA
E = VIL,
G = VIH
30
mA
E = VIL,
G = VIH
50
mA
VCC = VCC MAX
VCC = VCC MAX
E = VIH
1
mA
100
µA
CMOS input level
† See the recommended operating conditions table
NOTES: 5. Typical value at nominal condition (TA = 25°C)
6. 12-mA IOL also available
7. ICC current in the read mode, switching at 6 MHz, IOUT = 0 mA
8. ICC current while erase or program operation is in progress
2.4
V
VCC – 0.4
0.85*VCC
0.45
V
0.45
E = VCC ± 0.5 V
±1
µA
±1
µA
capacitance over recommended ranges of supply voltage and ambient temperature
PARAMETER
TEST CONDITIONS
Ci1
Input capacitance (All inputs except A9, E, G)
Ci2
Input capacitance (A9, E, G)
VI = 0 V,
VI = 0 V,
Co
Output capacitance
POST OFFICE BOX 1443
MIN
MAX
UNIT
7.5
pF
f = 1 MHz
9
pF
VO = 0 V, f = 1 MHz
12
pF
• HOUSTON, TEXAS 77251–1443
f = 1 MHz
13
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
switching characteristics over recommended ranges of supply voltage and ambient temperature,
read-only operation† (see Figure 2, Figure 11, Figure 13, Figure 15, and Figure 17)
ALTERNATE
SYMBOL
PARAMETER
’29F010-70
’29F010-90
’29F010-10
’29F010-12
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
tAVQV
tELQV
Access time, address
tGLQV
tAVAV
Access time, G
tEHQZ
Disable time, E to high impedance
tdis(E)
20
20
20
30
ns
tGHQZ
Disable time, G to high
impedance
tdis(G)
20
20
20
30
ns
tAXQX
Hold time, output from address, E
or G change
tWHGL1
Hold time, G read
tWHGL2
Hold time, G toggle and data
polling
Access time, E
Cycle time, read
ta(A)
ta(E)
70
90
100
120
ns
70
90
100
120
ns
ta(G)
tc(R)
30
35
45
50
ns
70
th(D)
90
POST OFFICE BOX 1443
120
ns
0
0
0
0
ns
0
0
0
0
ns
10
10
10
10
ns
† See Figure 1 for AC test output load circuit and voltage waveforms.
14
100
• HOUSTON, TEXAS 77251–1443
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
timing requirements controlled by W (see Figure 4, Figure 7, Figure 9, Figure 11, Figure 13,
Figure 15, and Figure 17)
ALTERNATE
SYMBOL
tAVAV
tWHWH1
Cycle time, write
tWHWH2
tWHWH3
Cycle time, sector-erase operation
tWLAX
tWHDX
Hold time, address
tWHEH
tWHWL
tWLWH1
tWLWH2
Pulse duration, W low
tWLWH3
tGHWL
Pulse duration, W low (see Note 10)
tAVWL
tDVWH
Cycle time, programming operation
tc(W)
tc(W)PR
’29F010-70
MIN
TYP
’29F010-90
MAX
70
MIN
MAX
90
18
Cycle time, chip-erase operation
TYP
ns
µs
18
1
15
2
60
UNIT
1
15
2
60
s
s
45
45
ns
Hold time, data valid after W high
th(A)
th(D)
0
0
ns
Hold time, E
th(E)
0
0
ns
tw(WH)
tw(WL)
20
20
ns
35
45
ns
100
100
µs
Pulse duration, W high
Pulse duration, W low (see Note 9)
10
10
ms
0
0
ns
Setup time, address
trec(R)
tsu(A)
0
0
ns
Setup time, data
tsu(D)
Recovery time, read-before-write
30
45
ns
tAVGH
Setup time, A0 and A6 low and A1 high to G high
(see Note 9)
0
0
ns
tAVGEH
Setup time, A0 low and A1 and A6 high to G and E
high (see Note 10)
0
0
ns
0
0
ns
tELWL
tGHWH
Setup time, E
tVCEL
tEHVWL
Setup time, VCC
tGHVWL
tWHAH
tsu(E)
Setup time, G
0
0
ns
50
50
µs
Setup time, E VID to W (see Note 10)
4
4
µs
Setup time, G VID to W (see Notes 9 and 10)
4
4
µs
Setup time, W high to A6 going high (see Note 10)
0
0
ns
4
4
µs
tHVT
Transition time, VID (see Notes 9 and 10)
NOTES: 9. Sector-protect timing (see Figure 15)
10. Sector-unprotect timing (see Figure 17)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
timing requirements controlled by W (see Figure 4, Figure 7, Figure 9, Figure 11, Figure 13,
Figure 15, and Figure 17) (continued)
ALTERNATE
SYMBOL
tAVAV
tWHWH1
Cycle time, write
tWHWH2
tWHWH3
Cycle time, sector-erase operation
tWLAX
tWHDX
Hold time, address
tWHEH
tWHWL
tWLWH1
tWLWH2
Pulse duration, W low
tWLWH3
tGHWL
Pulse duration, W low (see Note 10)
tAVWL
tDVWH
Cycle time, programming operation
tc(W)
tc(W)PR
’29F010-10
MIN
TYP
’29F010-12
MAX
100
MIN
MAX
120
18
Cycle time, chip-erase operation
TYP
ns
µs
18
1
15
2
60
UNIT
1
15
2
60
s
s
45
50
ns
Hold time, data valid after W high
th(A)
th(D)
0
0
ns
Hold time, E
th(E)
0
0
ns
tw(WH)
tw(WL)
20
20
ns
45
50
ns
100
100
µs
Pulse duration, W high
Pulse duration, W low (see Note 9)
10
10
ms
0
0
ns
Setup time, address
trec(R)
tsu(A)
0
0
ns
Setup time, data
tsu(D)
Recovery time, read-before-write
45
50
ns
tAVGH
Setup time, A0 and A6 low and A1 high to G high
(see Note 9)
0
0
ns
tAVGEH
Setup time, A0 low and A1 and A6 high to G and E
high (see Note 10)
0
0
ns
0
0
ns
tELWL
tGHWH
Setup time, E
tVCEL
tEHVWL
Setup time, VCC
tGHVWL
tWHAH
tsu(E)
Setup time, G
0
0
ns
50
50
µs
Setup time, E VID to W (see Note 10)
4
4
µs
Setup time, G VID to W (see Notes 9 and 10)
4
4
µs
Setup time, W high to A6 going high (see Note 10)
0
0
ns
4
4
µs
tHVT
Transition time, VID (see Notes 9 and 10)
NOTES: 9. Sector-protect timing (see Figure 15)
10. Sector-unprotect timing (see Figure 17)
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
timing requirements controlled by E (see Figure 5)
ALTERNATE
SYMBOL
tc(W)
’29F010-70
MIN
TYP
’29F010-90
MAX
70
MIN
TYP
MAX
90
UNIT
tAVAV
tEHEH1
Cycle time, write
tEHEH2
tEHEH3
Cycle time, sector-erase operation (see Note 11)
1
15
1
15
s
Cycle time, chip-erase operation (see Note 12)
2
60
2
60
s
tELAX
tEHDX
Hold time, address
tEHWH
tELEH
Hold time, W
tEHEL
tGHEL
Pulse duration, E high
tAVEL
tDVEH
Setup time, address
Cycle time, programming operation
Hold time, data
Pulse duration, E low
Recovery time, read-before-write
Setup time, data
18
th(A)
th(D)
th(W)
45
45
ns
0
0
ns
0
0
ns
tw(EL)
tw(EH)
trec(R)
35
45
ns
20
20
ns
0
0
ns
tsu(A)
tsu(D)
0
0
ns
30
45
ns
0
0
ns
tWLEL
Setup time, W
tsu(W)
NOTES: 11. Timing diagram of E-controlled sector-erase operation not enclosed.
12. Timing diagram of E-controlled chip-erase operation not enclosed.
tAVAV
tEHEH1
Cycle time, write
tEHEH2
tEHEH3
Cycle time, sector-erase operation (see Note 11)
tELAX
tEHDX
Hold time, address
tEHWH
tELEH
Hold time, W
tEHEL
tGHEL
Pulse duration, E high
tAVEL
tDVEH
Setup time, address
’29F010-10
ALTERNATE
SYMBOL
MIN
tc(W)
100
TYP
Cycle time, programming operation
Pulse duration, E low
MAX
120
ns
µs
18
1
15
2
60
UNIT
1
15
2
60
s
s
50
ns
0
0
ns
th(W)
tw(EL)
0
0
ns
45
50
ns
20
20
ns
0
0
ns
tWLEL
Setup time, W
NOTES: 11. Timing diagram of E-controlled sector-erase operation not enclosed.
12. Timing diagram of E-controlled chip-erase operation not enclosed.
POST OFFICE BOX 1443
TYP
45
tsu(A)
tsu(D)
tsu(W)
Setup time, data
MIN
th(A)
th(D)
tw(EH)
trec(R)
Recovery time, read-before-write
’29F010-12
MAX
18
Cycle time, chip-erase operation (see Note 12)
Hold time, data
ns
µs
18
0
0
ns
45
50
ns
0
0
ns
• HOUSTON, TEXAS 77251–1443
17
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
0.5 mA
IOL
Output
Under
Test
CL
(see Note A, Note B, and Note C)
1.50 V
– 0.5 mA
2.4 V
2V
0.8 V
0.45 V
2V
0.8 V
VOLTAGE WAVEFORMS FOR -90, -10, -12
Conditions:
VIH = 2.4 V
VIL = 0.45 V
CL = 100 pF
IOH
3.0 V
1.5 V
VOLTAGE WAVEFORMS FOR -70
Conditions:
Measurements taken at: 2.0 V for logic high
0.8 V for logic low
Input rise and fall = <20 ns
1.5 V
0.0 V
VIH = 3.0 V
VIL = 0.0 V
CL = 30 pF
Measurements taken at: 1.5 V for logic high
1.5 V for logic low
Input rise and fall = <5 ns
NOTES: A. CL includes probe and fixture capacitance.
B. The ac testing inputs for -70 voltage waveforms are driven at 3 V for logic high and 0 V for logic low. Timing measurements for -70
voltage waveforms are made at 1.5 V for logic high and 1.5 V for logic low on both inputs and outputs. The ac testing inputs for -90,
-10, and -12 voltage waveforms are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements for -90, -10, and
-12 voltage waveforms are made at 2 V for logic high and 0.8 V for logic low on both inputs and outputs.
C. Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS, as closely as possible to the device pins.
Figure 1. AC Test Output Load Circuit and Voltage Waveforms
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
read operation
tAVAV
Valid Addresses
Addresses
tAVQV
E
tEHQZ
tELQV
G
tGHQZ
tGLQV
W
tAXQX
tWHGL1
Valid Data
DQ0 – DQ7
Figure 2. AC Waveform for Read Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
write operation
Start
Write Bus Cycle
5555H / AAH
Write Bus Cycle
2AAAH / 55H
Write Bus Cycle
5555H / A0H
Write Bus Cycle
Program Address / Program Data
Poll Device Status
Operation
Complete
?
Yes
No
Next Address
Last
Address
?
Yes
End
Figure 3. Byte-Program Algorithm
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
No
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
write operation (continued)
tAVAV
5555H
Addresses
2AAAH
5555H
PA
PA
tWLAX
tAVWL
E
tELWL
tWHEH
G
tWHDX
tGHWL
tWHWL
tWLWH1
W
tWHWH1
tDVWH
DQ0 – DQ7
AAH
55H
A0H
PD
DQ7
DOUT
NOTES: A. PA = Address of the location to be programmed
B. PD = Data to be programmed
C. DQ7 = Complement of data written to DQ7
Figure 4. AC Waveform for Byte-Program (W-Controlled) Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
write operation (continued)
tAVAV
5555H
Addresses
2AAAH
5555H
PA
PA
tAVEL
tELAX
tELEH
E
tEHEL
tGHEL
G
tDVEH
tEHEH1
tWLEL
tEHWH
W
tEHDX
DQ0 – DQ7
AAH
55H
A0H
PD
DQ7
NOTES: A. PA = Address of the location to be programmed
B. PD = Data to be programmed
C. DQ7 = Complement of data written to DQ7
Figure 5. AC Waveform for Byte-Program (Alternate E-Controlled) Operation
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
DOUT
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
chip-erase operation
Start
Write Bus Cycle
5555H / AAH
Write Bus Cycle
2AAAH / 55H
Write Bus Cycle
5555H / 80H
Write Bus Cycle
5555H / AAH
Write Bus Cycle
2AAAH / 55H
Write Bus Cycle
5555H / 10H
Poll Device Status
Operation
Complete
?
No
Yes
End
Figure 6. Chip-Erase Algorithm
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
chip-erase operation (continued)
tAVAV
Addresses
5555H
2AAAH
5555H
5555H
2AAAH
5555H
VA
tAVWL
tWLAX
E
tELWL
tWHEH
G
tGHWL
tWHWL
tWLWH1
W
tDVWH
tWHWH3
tWHDX
DQ0 – DQ7
AAH
55H
80H
AAH
55H
tVCEL
VCC
NOTE A: VA = any valid address
Figure 7. AC Waveform for Chip-Erase Operation
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
10H
DQ7=0
DOUT=FFH
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
sector-erase operation
Start
Write Bus Cycle
5555H / AAH
Write Bus Cycle
2AAAH / 55H
Write Bus Cycle
5555H / 80H
Write Bus Cycle
5555H / AAH
Write Bus Cycle
2AAAH / 55H
Write Bus Cycle
Sector Address / 30H
No
DQ3 = 0
?
Yes
Load
Additional
Sectors
?
Yes
No
Poll Device Status
No
Operation
Complete
?
Yes
End
Figure 8. Sector-Erase Algorithm
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
sector-erase operation (continued)
tAVAV
Addresses
5555H
2AAAH
5555H
5555H
2AAAH
SA
SA
tAVWL
tWLAX
E
tELWL
tWHEH
G
tGHWL
tWHWL
tWLWH1
W
tDVWH
tWHWH2
tWHDX
DQ0 – DQ7
AAH
55H
80H
AAH
55H
30H
tVCEL
VCC
NOTE A: SA = Sector address to be erased
Figure 9. AC Waveform for Sector-Erase Operation
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
DQ7=0
DOUT=FFH
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
data-polling operation
Start
Read DQ0 – DQ7
Addr = VA
DQ7 =
Data
?
Yes
No
No
DQ5 = 1
?
Yes
Read DQ0 – DQ7
Addr = VA
DQ7 =
Data
?
Yes
No
Fail
Pass
NOTES: A. DQ7 is checked again after DQ5 is checked, even if DQ5 = 1.
B. VA = Program address for byte-programming
= Selected sector address for sector-erase
= Any valid address for chip-erase
Figure 10. Data-Polling Algorithm
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
data-polling operation (continued)
AIN
Addresses
AIN
AIN
tAVQV
tAVQV
tELQV
tAXQX
tELQV
E
tGLQV
tGLQV
G
tGHQZ
tWHGL2
W
tWHWH1, 2, or 3
DQ
NOTES: A.
B.
C.
D.
E.
DIN
DQ7
DQ7
DQ7
DIN
= Last command data written to the device
DQ7
= Complement of data written to DQ7
DOUT = Valid data output
AIN
= Valid address for byte-program, sector-erase, or chip-erase operation
The data-polling operation is valid for both W- and E-controlled byte-program, sector-erase, and chip-erase
operations.
Figure 11. AC Waveform for Data-Polling Operation
28
DOUT
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
toggle-bit operation
Start
Read DQ0 – DQ7
Addr = VA
Read DQ0 – DQ7
Addr = VA
DQ6 =
Toggle
?
No
Yes
No
DQ5 = 1
?
YES
Read DQ0 – DQ7
DQ6 =
Toggle
?
No
Yes
Fail
Pass
NOTE A: DQ6 is checked again after DQ5 is checked, even if DQ5 = 1.
Figure 12. Toggle-Bit Algorithm
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29
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
toggle-bit operation (continued)
AIN
Addresses
tAVQV
tELQV
tELQV
E
tGLQV
tGLQV
G
tGHWH
tWHGL2
W
tWHWH1, 2, OR 3
DQ
NOTES: A.
B.
C.
D.
E.
DIN
DQ6 =
Toggle
DQ6 =
Toggle
DQ6 =
Toggle
DQ6 = Stop
Toggle
DIN
= Last command data written to the device
DQ6
= Toggle bit output
DOUT = Valid data output
AIN
= Valid address for byte-program, sector-erase, or chip-erase operation
The toggle-bit operation is valid for both W- and E-controlled byte-program, sector-erase, and chip-erase operations.
Figure 13. AC Waveform for Toggle-Bit Operation
30
DOUT
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TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
sector-protect operation
Start
Select Sector Address
A16, A15, A14
X=1
G and A9 = VID
E = VIL
Apply One 100-µs
Pulse
G, A0, and A6 = VIL
W and A1 = VIH
X = X+1
Read Data
No
X = 25
?
No
Data = 01H
?
Yes
Yes
Sector Protect
Failed
Protect
Additional
Sectors
?
Yes
No
A9 = VIH or VIL
Write Reset Command
End
Figure 14. Sector-Protect Algorithm
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31
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
sector-protect operation (continued)
Sector Address
A16 – A14
VID
A9
tHVT
A6
A1
A0
tAVGH
E
VID
G
tGHVWL
tHVT
tHVT
tWLWH2
W
tGLQV
DQ
DOUT
NOTE A: DOUT = 00H if selected sector is not protected,
01H if the sector is protected
Figure 15. AC Waveform for Sector-Protect Operation
32
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TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
sector-unprotect operation
Start
Protect All Sectors
X=1
E, G, A9 = VID
A6 = VIL, A7 and A12 = VIH
Apply One
10-ms Pulse
E, G, A0 = VIL
W, A1, and A6 = VIH
Select Sector Address
A16, A15, A14
X = X+1
Read Data
No
No
X = 1000
?
Next Sector
Address
Data = 00H
?
Yes
Yes
Sector unprotect
Failed
Last
Sector
?
No
Yes
A9 = VIH or VIL
Write Reset Command
End
Figure 16. Sector-Unprotect Algorithm
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33
TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
sector-unprotect operation (continued)
A16 –
A14
Sector Address
A12
tAVQV
VID
A9
tHVT
A7
tWHAH
A6
A1
tAVGEH
A0
VID
E
tHVT
tEHVWL
VID
G
tWLWH3
tHVT
tHVT
tGHVWL
W
tGLQV
DOUT
DQ
NOTE A: DOUT = 00H if selected sector is not protected,
01H if the sector is protected
Figure 17. AC Waveform for Sector-Unprotect Operation
34
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TMS29F010
131072 BY 8-BIT
FLASH MEMORY
SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998
MECHANICAL DATA
FM (R-PQCC-J32)
PLASTIC J-LEADED CHIP CARRIER
Seating Plane
0.004 (0,10)
0.140 (3,56)
0.132 (3,35)
0.495 (12,57)
4
0.485 (12,32)
0.129 (3,28)
0.123 (3,12)
0.453 (11,51)
0.447 (11,35)
0.049 (1,24)
0.043 (1,09)
1
0.008 (0,20) NOM
30
29
5
0.020 (0,51)
0.015 (0,38)
0.595 (15,11)
0.585 (14,86)
0.553 (14,05)
0.547 (13,89)
0.030 (0,76)
TYP
21
13
14
20
0.050 (1,27)
4040201-4 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-016
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35
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