TI SN74ABT8543

SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
D
D
D
D
D
D
SN54ABT8543 . . . JT PACKAGE
SN74ABT8543 . . . DL OR DW PACKAGE
(TOP VIEW)
Members of the Texas Instruments
SCOPE  Family of Testability Products
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
Functionally Equivalent to ’F543 and
’ABT543 in the Normal-Function Mode
SCOPE  Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
– Parallel-Signature Analysis at Inputs
With Masking Option
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Even-Parity Opcodes
Two Boundary-Scan Cells Per I/O for
Greater Flexibility
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DL) Packages, Ceramic Chip
Carriers (FK), and Standard Ceramic
DIPs (JT)
LEAB
CEAB
OEAB
A1
A2
A3
GND
A4
A5
A6
A7
A8
TDO
TMS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
LEBA
CEBA
OEBA
B1
B2
B3
B4
VCC
B5
B6
B7
B8
TDI
TCK
SN54ABT8543 . . . FK PACKAGE
(TOP VIEW)
B1
B2
B3
B4
V CC
B5
B6
D
OEBA
CEBA
LEBA
LEAB
CEAB
OEAB
A1
description
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
B7
B8
TDI
TCK
TMS
TDO
A8
A2
A3
GND
A4
A5
A6
A7
The ’ABT8543 scan test devices with octal
registered bus transceivers are members of the
Texas
Instruments
SCOPE
testability
integrated-circuit family. This family of devices
supports IEEE Standard 1149.1-1990 boundary
scan to facilitate testing of complex circuit-board
assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port
(TAP) interface.
4 3 2 1 28 27 26
5
In the normal mode, these devices are functionally equivalent to the ’F543 and ’ABT543 octal registered bus
transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at
the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does not
affect the functional operation of the SCOPE octal registered bus transceivers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
description (continued)
Data flow in each direction is controlled by latch-enable (LEAB and LEBA), chip-enable (CEAB and CEBA), and
output-enable (OEAB and OEBA) inputs. For A-to-B data flow, the device operates in the transparent mode
when LEAB and CEAB are both low. When either LEAB or CEAB is high, the A data is latched. The B outputs
are active when OEAB and CEAB are both low. When either OEAB or CEAB is high, the B outputs are in the
high-impedance state. Control for B-to-A data flow is similar to that for A-to-B, but uses LEBA, CEBA, and OEBA.
In the test mode, the normal operation of the SCOPE registered bus transceiver is inhibited and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO),
test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions
such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from
data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT8543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT8543 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE†
(normal mode, each register)
INPUTS
LEAB
A
OUTPUT
B
CEAB
OEAB
L
L
L
L
L
L
L
L
H
L
L
H
X
H
B0‡
L
H
X
X
Z
H
X
X
X
Z
† A-to-B data flow is shown. B-to-A data flow is similar but
uses CEBA, OEBA, and LEBA.
‡ Output level before the indicated steady-state input
conditions were established
2
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SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
functional block diagram
Boundary-Scan Register
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
26
27
28
3
2
1
C1
1D
25
A1 4
B1
C1
1D
One of Eight Channels
Bypass Register
Boundary-Control
Register
VCC
TDI
16
13
TDO
Instruction Register
VCC
TMS
TCK
14
15
TAP
Controller
Pin numbers shown are for the DL, DW, and JT packages.
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• DALLAS, TEXAS 75265
3
SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
Terminal Functions
TERMINAL
NAME
A1–A8
Normal-function A-bus I/O ports. See function table for normal-mode logic.
B1–B8
Normal-function B-bus I/O ports. See function table for normal-mode logic.
CEAB, CEBA
GND
4
DESCRIPTION
Normal-function chip-enable inputs. See function table for normal-mode logic.
Ground
LEAB, LEBA
Normal-function latch-enable inputs. See function table for normal-mode logic.
OEAB, OEBA
Normal-function output-enable inputs. See function table for normal-mode logic.
TCK
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK, and outputs change on the falling edge of TCK.
TDI
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
TDO
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.
TMS
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected.
VCC
Supply voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test-data registers: a 40-bit boundary-scan register, an
11-bit boundary-control register, and a 1-bit bypass register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = H
TMS = H
Run-Test/Idle
TMS = H
Select-DR-Scan
Select-IR-Scan
TMS = L
TMS = L
TMS = L
TMS = H
TMS = H
Capture-DR
Capture-IR
TMS = L
TMS = L
Shift-DR
Shift-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
TMS = H
Exit1-DR
Exit1-IR
TMS = L
TMS = L
Pause-DR
Pause-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = L
Exit2-DR
TMS = L
Exit2-IR
TMS = H
Update-DR
TMS = H
TMS = L
TMS = H
Update-IR
TMS = H
TMS = L
Figure 1. TAP-Controller State Diagram
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SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
state diagram description
The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’ABT8543, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. Each bit in the boundary-scan register is reset to logic 0. The boundary-control register is reset to
the binary value 00000000010, which selects the PSA test operation with no input masking.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle.
The test operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
6
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SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.
On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the
high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, then such update
occurs on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state.
For the ’ABT8543, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.
On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the
high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
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SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
register overview
With the exception of the bypass register, any test register can be thought of as a serial-shift register with a
shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the
appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register
can be parallel loaded from a source specified by the current instruction. During the appropriate shift state
(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted
in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from
the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the three data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 3 lists the instructions supported by the ’ABT8543. The even-parity feature specified for SCOPE devices
is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for
SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated,
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2.
TDI
Bit 7
Parity
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
TDO
Figure 2. Instruction Register Order of Scan
data register description
boundary-scan register
The boundary-scan register (BSR) is 40 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin, two BSCs for each normal-function I/O pin (one for input data and one for output data),
and one BSC for each of the internally decoded output-enable signals (OEA and OEB). The BSR is used to store
test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device
output pins, and/or to capture data that appears internally at the outputs of the normal on-chip logic and/or
externally at the device input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in Test-Logic-Reset, the value of each BSC is reset to logic 0.
When external data is to be captured, the BSCs for signals OEA and OEB capture logic values determined by
OEAB CEAB. When data is to
OEBA CEBA, and OEB
the following positive-logic equations: OEA
be applied externally, these BSCs control the drive state (active or high-impedance) of their respective outputs.
+
)
+
)
The BSR order of scan is from TDI through bits 39–0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
8
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SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
39
OEB
31
A8-I
23
A8-O
15
B8-I
7
B8-O
38
OEA
30
A7-I
22
A7-O
14
B7-I
6
B7-O
37
OEAB
29
A6-I
21
A6-O
13
B6-I
5
B6-O
36
OEBA
28
A5-I
20
A5-O
12
B5-I
4
B5-O
35
LEAB
27
A4-I
19
A4-O
11
B4-I
3
B4-O
34
LEBA
26
A3-I
18
A3-O
10
B3-I
2
B3-O
33
CEAB
25
A2-I
17
A2-O
9
B2-I
1
B2-O
CEBA
24
A1-I
16
A1-O
8
B1-I
0
B1-O
32
boundary-control register
The boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction to
implement additional test operations not included in the basic SCOPE instruction set. Such operations include
PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations that are
decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 00000000010, which selects the PSA test operation with no input masking.
The BCR order of scan is from TDI through bits 10–0 to TDO. Table 2 shows the BCR bits and their associated
test control signals.
Table 2. Boundary-Control Register Configuration
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
10
MASK8
6
MASK4
2
OPCODE2
9
MASK7
5
MASK3
1
OPCODE1
8
MASK6
4
MASK2
0
OPCODE0
7
MASK5
3
MASK1
––
––
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
thereby reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 3.
TDI
Bit 0
TDO
Figure 3. Bypass Register Order of Scan
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SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
instruction-register opcode description
The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of
each instruction.
Table 3. Instruction-Register Opcodes
BINARY CODE†
BIT 7 → BIT 0
MSB → LSB
SCOPE OPCODE
DESCRIPTION
SELECTED DATA
REGISTER
EXTEST/INTEST
BYPASS‡
Boundary scan
Boundary scan
Test
10000001
Bypass scan
Bypass
Normal
10000010
SAMPLE/PRELOAD
Sample boundary
Boundary scan
Normal
00000011
Boundary scan
Boundary scan
Test
10000100
INTEST/EXTEST
BYPASS‡
Bypass scan
Bypass
Normal
00000101
BYPASS‡
Bypass scan
Bypass
Normal
00000110
HIGHZ
Control boundary to high impedance
Bypass
Modified test
10000111
CLAMP
BYPASS‡
Control boundary to 1/0
Bypass
Test
10001000
Bypass scan
Bypass
Normal
00001001
RUNT
Boundary run test
Bypass
Test
00001010
READBN
Boundary read
Boundary scan
Normal
10001011
READBT
Boundary read
Boundary scan
Test
00001100
CELLTST
Boundary self test
Boundary scan
Normal
10001101
TOPHIP
Boundary toggle outputs
Bypass
Test
10001110
SCANCN
Boundary-control register scan
Boundary control
Normal
00001111
SCANCT
Boundary-control register scan
Boundary control
Test
All others
BYPASS
Bypass scan
Bypass
Normal
00000000
MODE
† Bit 7 is used to maintain even parity in the 8-bit instruction.
‡ The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’ABT8543.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned
into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into
the output BSCs is applied to the device output pins. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.
10
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control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device
input pins remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device
output pins. The device operates in the test mode.
boundary run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device output pins on each
falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the
inputs of the normal on-chip logic. Data appearing at the device input pins is not captured in the input BSCs.
The device operates in the test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to
be executed.
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boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2 → BIT 0
MSB → LSB
DESCRIPTION
X00
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/16-bit mode (PRPG)
X10
Parallel-signature analysis/16-bit mode (PSA)
011
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/8-bit mode (PSA/COUNT)
In general, while the control input BSCs (bits 39–32) are not included in the sample, toggle, PSA, PRPG, or
COUNT algorithms, the output-enable BSCs (bits 39–38 of the BSR) do control the drive state (active or high
impedance) of the selected device output pins. These BCR instructions are valid only when the device is
operating in one direction of data flow (that is, OEA ≠ OEB). Otherwise, the bypass instruction is operated.
PSA input masking
Bits 10–3 of the BCR specify device input pins to be masked from PSA operations. Bit 10 selects masking for
device input pin A8 during A-to-B data flow or for device input pin B8 during B-to-A data flow. Bit 3 selects
masking for device input pins A1 or B1 during A-to-B or B-to-A data flow, respectively. Bits intermediate to 10
and 3 mask corresponding device input pins, in order, from most significant to least significant, as indicated in
Table 3. When the mask bit that corresponds to a particular device input has a logic 1 value, the device input
pin is masked from any PSA operation, i.e., the state of the device input pin is ignored and has no effect on the
generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding device input is not
masked from the PSA operation.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input pins is captured in the shift-register elements of the selected BSCs
on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied
to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs is
toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output
pins on each falling edge of TCK.
12
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pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs
of the normal on-chip logic. Figures 4 and 5 show the 16-bit linear-feedback shift-register algorithms through
which the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
=
Figure 4. 16-Bit PRPG Configuration (OEA = 0, OEB = 1)
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
=
Figure 5. 16-Bit PRPG Configuration (OEA=1, OEB= 0)
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parallel-signature analysis (PSA)
MASKX
Data appearing at the selected device input pins is compressed into a 16-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow
latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow
latches of the selected output BSCs remains constant and is applied to the device outputs. Figures 6 and 7 show
the 16-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed
value should be scanned into the BSR before performing this operation.
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
=
=
MASKX
Figure 6. 16-Bit PSA Configuration (OEA = 0, OEB = 1)
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
=
=
Figure 7. 16-Bit PSA Configuration (OEA = 1, OEB = 0)
14
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simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 8-bit pseudo-random pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. Figures 8 and 9 show the 8-bit linear-feedback shift-register algorithms through
which the signature and patterns are generated. An initial seed value should be scanned into the BSR before
performing this operation. A seed value of all zeroes does not produce additional patterns.
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
MASKX
A8-I
=
=
Figure 8. 8-Bit PSA/PRPG Configuration (OEA = 0, OEB = 1)
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
MASKX
B8-I
=
=
Figure 9. 8-Bit PSA/PRPG Configuration (OEA = 1, OEB = 0)
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simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 8-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. The shift-register elements of the opposite output BSCs count carries out of the
selected output BSCs, extending the count to 16 bits. Figures 10 and 11 show the 8-bit linear-feedback
shift-register algorithms through which the signature is generated. An initial seed value should be scanned into
the BSR before performing this operation.
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
MASKX
A8-I
=
MSB
LSB
=
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
B2-I
B1-I
Figure 10. 8-Bit PSA/COUNT Configuration (OEA = 0, OEB = 1)
B7-I
B6-I
B5-I
B4-I
B3-I
MASKX
B8-I
=
MSB
LSB
=
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
Figure 11. 8-Bit PSA/COUNT Configuration (OEA = 1, OEB = 0)
16
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A1-O
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timing description
All test operations of the ’ABT8543 are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs
is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling
edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1) by changing the value
of TMS on the falling edge of TCK and then applying a rising edge to TCK.
A simple timing example is shown in Figure 12. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states, as necessary, to perform one instruction-register
scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and
TDO is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5
details the operation of the test circuitry during each TCK cycle.
Table 5. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
1
Test-Logic-Reset
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
2
Run-Test/Idle
3
Select-DR-Scan
4
Select-IR-Scan
5
Capture-IR
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
6
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
Shift-IR
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next
TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
14
Exit1-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
15
Update-IR
16
Select-DR-Scan
17
Capture-DR
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
18
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
19–20
Shift-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
21
Exit1-DR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
22
Update-DR
23
Select-DR-Scan
7–13
24
Select-IR-Scan
25
Test-Logic-Reset
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
In general, the selected data register is updated with the new data on the falling edge of TCK.
Test operation completed
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Test-Logic-Reset
Select-IR-Scan
Update-DR
Exit1-DR
Capture-DR
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Select-DR-Scan
ÎÎ
ÎÎ
Select-DR-Scan
Shift-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
TAP
Controller
State
Test-Logic-Reset
TDO
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Update-IR
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TDI
Exit1-IR
TMS
Shift-DR
TCK
3-State (TDO) or Don’t Care (TDI)
Figure 12. Timing Example
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI: except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT8543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT8543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 0.7 W
DW package . . . . . . . . . . . . . . . . . . 1.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
18
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recommended operating conditions (see Note 3)
SN54ABT8543
SN74ABT8543
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–24
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
85
°C
High-level input voltage
2
2
0.8
Input voltage
0
TA
Operating free-air temperature
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
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–55
125
V
0.8
0
–40
V
VCC
–32
V
V
mA
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
II
A or B ports
IIH
IIL
TDI, TMS
TDI, TMS
IOZH‡
IOZL‡
Ioff
IOZPU
IOZPD
ICEX
IO§
ICC
Outputs high
A or B ports
TA = 25°C
TYP†
MAX
Ci
Control inputs
Cio
A or B ports
MIN
–1.2
MAX
SN74ABT8543
MIN
–1.2
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
UNIT
V
V
2
0.55
VCC = 5.5 V, VI = VCC or GND
±1
±1
±1
VCC = 5.5 V, VI = VCC or GND
VCC = 5.5 V,
VI = VCC
±100
±100
±100
10
10
10
µA
–160
µA
50
µA
IOL = 64 mA
–40
–160
0.55
VCC = 5.5 V,
VCC = 5.5 V,
VI = GND
VO = 2.7 V
VCC = 5.5 V,
VCC = 0,
VO = 0.5 V
VI or VO ≤ 4.5 V
VCC = 0 to 2 V,
VCC = 2 V to 0,
VO = 0.5 V or 2.7 V
VO = 0.5 V or 2.7 V
VCC = 5.5 V,
VCC = 5.5 V,
VO = 5.5 V
VO = 2.5 V
–100
–180
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
Outputs high
0.9
2
2
2
Outputs low
30
38
38
38
Outputs disabled
0.9
2
2
2
1.5
1.5
1.5
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
–40
–160
50
50
–50
–50
–40
±100
–50
POST OFFICE BOX 655303
V
µA
µ
–50
µA
±100
µA
±50
±50
±50
µA
±50
±50
±50
µA
50
50
50
µA
–180
mA
–50
–180
–50
mA
mA
3
pF
10
pF
Co
TDO
VO = 2.5 V or 0.5 V
8
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
20
MAX
–1.2
2.5
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
∆ICC¶
SN54ABT8543
0.55
0.55*
VCC = 4
4.5
5V
CE, LE,
OE, TCK
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timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 13)
SN54ABT8543
MIN
MAX
SN74ABT8543
MIN
MAX
UNIT
tw
tsu
Pulse duration
LEAB or LEBA high or low
3
3
ns
Setup time
A before LEAB↑ or B before LEBA↑
3.5
3
ns
th
Hold time
A after LEAB↑ or B after LEBA↑
1.5
0.5
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 13)
SN54ABT8543
SN74ABT8543
MIN
MAX
MIN
MAX
50
0
50
fclock
tw
Clock frequency
TCK
0
Pulse duration
TCK high or low
5
5
tsu
Setup time
A or B or CE or LE or OE before TCK↑
TDI before TCK↑
TMS before TCK↑
A or B or CE or LE or OE after TCK↑
th
td
tr
Hold time
Delay time
6
5
6.5
6
6
6
UNIT
MHz
ns
ns
0.5
0
TDI after TCK↑
0
0
TMS after TCK↑
0
0
50*
50
ns
1*
1
µs
Power up to TCK↑
Rise time
VCC power up
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 13)
SN54ABT8543
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LEAB or LEBA
B or A
tPZH
tPZL
CEAB or CEBA
B or A
tPZH
tPZL
OEAB or OEBA
B or A
tPHZ
tPLZ
CEAB or CEBA
B or A
tPHZ
tPLZ
OEAB or OEBA
B or A
VCC = 5 V,
TA = 25°C
MIN
TYP
MAX
MIN
MAX
2
3.7
4.7
2
5.5
1.5
3.5
4.4
1.5
5.8
2
4.7
5.6
2
8.1
1.5
4.1
5
1.5
7.3
2
4.2
5.2
2
7.5
2
4.7
6.1
2
8.4
2
4.4
5.4
2
6.7
2
5.2
7.4
2
7.6
2.5
5.8
6.8
2.5
9.1
2.5
5.3
6.3
2.5
8.7
2
5.9
6.9
2
8.3
2
5.2
6.2
2
7.8
UNIT
ns
ns
ns
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 13)
SN74ABT8543
PARAMETER
22
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LEAB or LEBA
B or A
tPZH
tPZL
CEAB or CEBA
B or A
tPZH
tPZL
OEAB or OEBA
B or A
tPHZ
tPLZ
CEAB or CEBA
B or A
tPHZ
tPLZ
OEAB or OEBA
B or A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
MAX
2
3.7
4.5
2
5.2
1.5
3.5
4.4
1.5
5.5
2
4.7
5.6
2
7.8
1.5
4.1
5
1.5
6.9
2
4.2
5.2
2
7.2
2
4.7
5.7
2
8.3
2
4.4
5.4
2
6.5
2
5.2
6.2
2
7.5
2.5
5.8
6.8
2.5
8.8
2.5
5.3
6.3
2.5
8
2
5.9
6.9
2
7.9
2
5.2
6.2
2
7.4
UNIT
ns
ns
ns
ns
ns
ns
SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 13)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
TCK
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
POST OFFICE BOX 655303
VCC = 5 V,
TA = 25°C
MIN
TYP
50
90
SN54ABT8543
MAX
MIN
MAX
50
SN74ABT8543
MIN
50
MHz
3.5
8
9.5
3.5
12.7
3.5
12
3
7.7
9
3
12
3
11.5
2.5
4.3
5.5
2.5
7
2.5
6.5
2.5
4.2
5.5
2.5
7
2.5
6.5
4.5
8.2
9.5
4.5
12.5
4.5
12
4.5
9
10.5
4.1
13.5
4.5
13
2.5
4.3
5.5
2.5
7
2.5
6.5
2.5
4.9
6
2.5
7.5
2.5
7
3.5
8.4
10.5
3.5
14
3.5
13.5
3
8
10.5
3
13.5
3
13
3
5.9
7
3
9
3
8.5
3
5
6.5
3
8
3
7.5
• DALLAS, TEXAS 75265
UNIT
MAX
ns
ns
ns
ns
ns
ns
23
SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
3V
1.5 V
Timing Input
0V
tw
tsu
3V
Input
1.5 V
1.5 V
3V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
1.5 V
0V
1.5 V
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
0V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
VOH
Output
3V
Output
Control
tPHL
tPLH
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
th
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 13. Load Circuit and Voltage Waveforms
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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