TI SN74ABTH182504APM

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
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Members of the Texas Instruments
SCOPE  Family of Testability Products
Members of the Texas Instruments
Widebus Family
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Bus Hold on Data Inputs Eliminates the
Need for External Pullup Resistors
B-Port Outputs of ’ABTH182504A Devices
Have Equivalent 25-Ω Series Resistors, So
No External Resistors Are Required
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
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One Boundary-Scan Cell Per I/O
Architecture Improves Scan Efficiency
SCOPE  Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
Packaged in 64-Pin Plastic Thin Quad Flat
(PM) Packages Using 0.5-mm
Center-to-Center Spacings and 68-Pin
Ceramic Quad Flat (HV) Packages Using
25-mil Center-to-Center Spacings
9
A4
A5
A6
GND
A7
A8
A9
A10
NC
VCC
A11
A12
A13
GND
A14
A15
A16
A1
GND
OEBA
LEBA
TDO
VCC
NC
TMS
CLKBA
CLKENBA
B1
GND
B2
B3
B4
A3
A2
SN54ABTH18504A, SN54ABTH182504A . . . HV PACKAGE
(TOP VIEW)
8 7
6
5 4 3
2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
B5
B6
B7
GND
B8
B9
B10
VCC
NC
B11
B12
B13
B14
GND
B15
B16
B17
VCC
TCK
LEAB
OEAB
GND
B20
B19
B18
A17
A18
A19
GND
A20
CLKENAB
CLKAB
TDI
NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE, Widebus, UBT, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
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1
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
A3
A2
A1
GND
OEBA
LEBA
TDO
V CC
TMS
CLKBA
CLKENBA
B1
GND
B2
B3
B4
SN74ABTH18504A, SN74ABTH182504A . . . PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
A4
A5
A6
GND
A7
A8
A9
A10
VCC
A11
A12
A13
GND
A14
A15
A16
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
B5
B6
B7
GND
B8
B9
B10
VCC
B11
B12
B13
B14
GND
B15
B16
B17
A17
A18
A19
GND
A20
CLKENAB
CLKAB
TDI
VCC
TCK
LEAB
OEAB
GND
B20
B19
B18
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
description
The ’ABTH18504A and ’ABTH182504A scan test devices with 20-bit universal bus transceivers are members
of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE
Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to
the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the
TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the
boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the
SCOPE universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while
CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and
CLKENAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs
are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to
A-to-B data flow, but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
description (continued)
Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin
architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A
PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count
addressing scheme is useful.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The B-port outputs of ’ABTH182504A, which are designed to source or sink up to 12 mA, include 25-Ω series
resistors to reduce overshoot and undershoot.
The SN54ABTH18504A and SN54ABTH182504A are characterized for operation over the full military
temperature range of –55°C to 125°C. The SN74ABTH18504A and SN74ABTH182504A are characterized for
operation from –40°C to 85°C.
FUNCTION TABLE†
(normal mode, each register)
INPUTS
OUTPUT
B
OEAB
LEAB
CLKENAB
CLKAB
A
L
L
L
L
X
L
L
L
↑
L
L
L
L
↑
H
H
L
L
H
X
X
L
H
X
X
L
B0‡
L
L
H
X
X
H
H
H
X
X
X
X
B0‡
L
Z
† A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEBA, CLKENBA, and CLKBA.
‡ Output level before the indicated steady-state input conditions were
established
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
functional block diagram
Boundary-Scan Register
CLKENAB
LEAB
CLKAB
OEAB
CLKENBA
LEBA
CLKBA
OEBA
A1
22
27
23
VCC
28
54
59
55
VCC
60
C1
C1
1D
1D
53
62
C1
1D
B1
C1
1D
1 of 20 Channels
Bypass Register
Boundary-Control
Register
Identification
Register
VCC
TDI
58
Instruction
Register
24
VCC
TMS
TCK
56
26
TAP
Controller
Pin numbers shown are for the PM package.
4
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TDO
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
Terminal Functions
TERMINAL NAME
DESCRIPTION
A1–A20
Normal-function A-bus I/O ports. See function table for normal-mode logic.
B1–B20
Normal-function B-bus I/O ports. See function table for normal-mode logic.
CLKAB, CLKBA
CLKENAB, CLKENBA
GND
Normal-function clock inputs. See function table for normal-mode logic.
Normal-function clock enables. See function table for normal-mode logic.
Ground
LEAB, LEBA
Normal-function latch enables. See function table for normal-mode logic.
OEAB, OEBA
Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal
forces the terminal to a high level if left unconnected.
TCK
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are
synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
TDI
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting
data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left
unconnected.
TDO
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting
data through the instruction register or selected data register.
TMS
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through
its TAP controller states. An internal pullup forces TMS to a high level if left unconnected.
VCC
Supply voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard
1149.1-1990. All test instructions, test data, and test control signals are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit
boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = H
TMS = H
Run-Test/Idle
TMS = H
Select-DR-Scan
Select-IR-Scan
TMS = L
TMS = L
TMS = L
TMS = H
TMS = H
Capture-DR
Capture-IR
TMS = L
TMS = L
Shift-DR
Shift-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
TMS = H
Exit1-DR
Exit1-IR
TMS = L
TMS = L
Pause-DR
Pause-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = L
Exit2-DR
TMS = L
Exit2-IR
TMS = H
Update-DR
TMS = H
TMS = L
Figure 1. TAP-Controller State Diagram
6
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TMS = H
Update-IR
TMS = H
TMS = L
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
state diagram description
The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected
or if a board defect causes it to be open circuited.
For the ’ABTH18504A and ’ABTH182504A, the instruction register is reset to the binary value 10000001, which
selects the IDCODE instruction. Bits 47–46 in the boundary-scan register are reset to logic 1, ensuring that
these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked
the outputs would be at high-impedance state). Reset values of other bits in the boundary-scan register should
be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the
PSA test operation.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
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7
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
Shift-DR (continued)
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state can suspend and resume data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such update occurs
on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the ’ABTH18504A and
’ABTH182504A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle, in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the
first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state can suspend and resume instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
8
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SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
register overview
With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 3 lists the instructions supported by the ’ABTH18504A and ’ABTH182504A. The even-parity feature
specified for SCOPE devices is supported in these devices. Bit 7 of the instruction opcode is the parity bit.
Any instructions that are defined for SCOPE devices but are not supported by these devices default to
BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.
TDI
Bit 7
Parity
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
TDO
Figure 2. Instruction Register Order of Scan
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SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
data register description
boundary-scan register
The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and
output data). The BSR is used 1) to store test data that is to be applied externally to the device output pins,
and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at
the device input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in Test-Logic-Reset, BSCs 47–46 are reset to logic 1, ensuring that these cells, which control A-port and B-port
outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at high-impedance state).
Reset values of other BSCs should be considered indeterminate.
The BSR order of scan is from TDI through bits 47–0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
Table 1. Boundary-Scan Register Configuration
10
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
47
OEAB
39
A20-I/O
19
B20-I/O
46
OEBA
38
A19-I/O
18
B19-I/O
45
CLKAB
37
A18-I/O
17
B18-I/O
44
CLKBA
36
A17-I/O
16
B17-I/O
43
CLKENAB
35
A16-I/O
15
B16-I/O
42
CLKENBA
34
A15-I/O
14
B15-I/O
41
LEAB
33
A14-I/O
13
B14-I/O
40
LEBA
32
A13-I/O
12
B13-I/O
––
––
31
A12-I/O
11
B12-I/O
––
––
30
A11-I/O
10
B11-I/O
––
––
29
A10-I/O
9
B10-I/O
––
––
28
A9-I/O
8
B9-I/O
––
––
27
A8-I/O
7
B8-I/O
––
––
26
A7-I/O
6
B7-I/O
––
––
25
A6-I/O
5
B6-I/O
––
––
24
A5-I/O
4
B5-I/O
––
––
23
A4-I/O
3
B4-I/O
––
––
22
A3-I/O
2
B3-I/O
––
––
21
A2-I/O
1
B2-I/O
––
––
20
A1-I/O
0
B1-I/O
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SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
boundary-control register
The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run
(RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set.
Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that
are decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.
TDI
Bit 2
(MSB)
Bit 1
Bit 0
(LSB)
TDO
Figure 3. Boundary-Control Register Order of Scan
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.
TDI
Bit 0
TDO
Figure 4. Bypass Register Order of Scan
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device-identification register
The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,
part number, and version of this device.
For the ’ABTH18504A , the binary value 00000000000000101000000000101111 (0002802F, hex) is captured
(during Capture-DR state) in the IDR to identify this device as Texas Instruments SN54/74ABTH18504A.
For the ’ABTH182504A , the binary value 00000000000000101100000000101111 (0002C02F, hex) is captured
(during Capture-DR state) in the IDR to identify this device as Texas Instruments SN54/74ABTH182504A.
The IDR order of scan is from TDI through bits 31–0 to TDO. Table 2 shows the IDR bits and their significance.
Table 2. Device-Identification Register Configuration
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
31
VERSION3
27
PARTNUMBER15
11
30
VERSION2
26
PARTNUMBER14
10
MANUFACTURER10†
MANUFACTURER09†
29
VERSION1
25
PARTNUMBER13
9
28
VERSION0
24
PARTNUMBER12
8
––
––
23
PARTNUMBER11
7
––
––
22
PARTNUMBER10
6
––
––
21
PARTNUMBER09
5
––
––
20
PARTNUMBER08
4
––
––
19
PARTNUMBER07
3
––
––
18
PARTNUMBER06
2
––
––
17
PARTNUMBER05
1
––
––
16
PARTNUMBER04
0
MANUFACTURER00†
LOGIC1†
––
––
15
PARTNUMBER03
––
––
––
––
14
PARTNUMBER02
––
––
––
––
13
PARTNUMBER01
––
––
––
––
12
PARTNUMBER00
––
MANUFACTURER08†
MANUFACTURER07†
MANUFACTURER06†
MANUFACTURER05†
MANUFACTURER04†
MANUFACTURER03†
MANUFACTURER02†
MANUFACTURER01†
––
† Note that for TI products, bits 11–0 of the device-identification register always contain the binary value 000000101111
(02F, hex).
12
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SCBS165C – AUGUST 1993 – REVISED JULY 1996
instruction-register opcode description
The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of
each instruction.
Table 3. Instruction-Register Opcodes
BINARY CODE†
BIT 7 → BIT 0
MSB → LSB
SCOPE OPCODE
DESCRIPTION
SELECTED
DATA REGISTER
MODE
00000000
EXTEST
Boundary scan
Boundary scan
Test
10000001
IDCODE
Identification read
Device identification
Normal
10000010
SAMPLE/PRELOAD
BYPASS‡
Sample boundary
Boundary scan
Normal
Bypass scan
Bypass
Normal
Bypass scan
Bypass
Normal
00000101
BYPASS‡
BYPASS‡
Bypass scan
Bypass
Normal
00000110
HIGHZ
Control boundary to high impedance
Bypass
Modified test
10000111
CLAMP
BYPASS‡
Control boundary to 1/0
Bypass
Test
10001000
Bypass scan
Bypass
Normal
00001001
RUNT
Boundary run test
Bypass
Test
00001010
READBN
Boundary read
Boundary scan
Normal
10001011
READBT
Boundary read
Boundary scan
Test
00001100
CELLTST
Boundary self test
Boundary scan
Normal
10001101
TOPHIP
Boundary toggle outputs
Bypass
Test
10001110
SCANCN
Boundary-control register scan
Boundary control
Normal
00001111
SCANCT
Boundary-control register scan
Boundary control
Test
All others
BYPASS
Bypass scan
Bypass
Normal
00000011
10000100
† Bit 7 is used to maintain even parity in the 8-bit instruction.
‡ The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’ABTH18504A or ’ABTH182504A.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST instruction. The BSR is selected in the
scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has
been scanned into the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at
the device pins, except for output-enables, is passed through the BSCs to the normal on-chip logic. For I/O pins,
the operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 47–46
of the BSR). When a given output enable is active (logic 0), the associated I/O pins operate in the output mode.
Otherwise, the I/O pins operate in the input mode. The device operates in the test mode.
identification read
This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the
scan path. The device operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured
in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs
associated with I/O pins in the output mode. The device operates in the normal mode.
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bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device
input pins remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O
BSCs for pins in the output mode is applied to the device I/O pins. The device operates in the test mode.
boundary-run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising
edge of TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device I/O pins on
each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data appearing at
the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a RUNT operation to specify which test operation is to be executed.
14
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boundary-control register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2 → BIT 0
MSB → LSB
DESCRIPTION
X00
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/40-bit mode (PRPG)
X10
Parallel-signature analysis /40-bit mode (PSA)
011
Simultaneous PSA and PRPG /20-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up /20-bit mode (PSA/COUNT)
While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 47–46 of the BSR) control the drive state (active or high impedance) of the selected
device output pins. These BCR instructions are valid only when the device is operating in one direction of data
flow (that is, OEAB ≠ OEBA). Otherwise, the bypass instruction is operated.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.
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pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each
falling edge of TCK. Figures 5 and 6 show the 40-bit linear-feedback shift-register algorithms through which the
patterns are generated. An initial seed value should be scanned into the BSR before performing this operation.
A seed value of all zeroes does not produce additional patterns.
A20-I/O
A19-I/O
A18-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
B20-I/O
B19-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
=
Figure 5. 40-Bit PRPG Configuration (OEAB = 0, OEBA = 1)
16
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B20-I/O
B19-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
A20-I/O
A19-I/O
A18-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
=
Figure 6. 40-Bit PRPG Configuration (OEAB = 1, OEBA = 0)
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parallel-signature analysis (PSA)
Data appearing at the selected device input-mode I/O pins is compressed into a 40-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the
selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8
show the 40-bit linear-feedback shift-register algorithms through which the signature is generated. An initial
seed value should be scanned into the BSR before performing this operation.
=
A20-I/O
A19-I/O
A18-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
B20-I/O
B19-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
=
Figure 7. 40-Bit PSA Configuration (OEAB = 0, OEBA = 1)
18
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=
B20-I/O
B19-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
A20-I/O
A19-I/O
A18-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
=
Figure 8. 40-Bit PSA Configuration (OEAB = 1, OEBA = 0)
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simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input-mode I/O pins is compressed into a 20-bit parallel signature in the
shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, a 20-bit
pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on each
rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling
edge of TCK. Figures 9 and 10 show the 20-bit linear-feedback shift-register algorithms through which the
signature and patterns are generated. An initial seed value should be scanned into the BSR before performing
this operation. A seed value of all zeroes does not produce additional patterns.
A20-I/O
A19-I/O
A18-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
B20-I/O
B19-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
=
=
Figure 9. 20-Bit PSA/PRPG Configuration (OEAB = 0, OEBA = 1)
20
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B20-I/O
B19-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
A20-I/O
A19-I/O
A18-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
=
=
Figure 10. 20-Bit PSA/PRPG Configuration (OEAB = 1, OEBA = 0)
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simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input-mode I/O pins is compressed into a 20-bit parallel signature in the
shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, a 20-bit
binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on each
rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling
edge of TCK. Figures 11 and 12 show the 20-bit linear-feedback shift-register algorithms through which the
signature is generated. An initial seed value should be scanned into the BSR before performing this operation.
A20-I/O
A19-I/O
A18-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
B19-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
MSB
B20-I/O
LSB
=
=
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
Figure 11. 20-Bit PSA/COUNT Configuration (OEAB = 0, OEBA = 1)
22
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B2-I/O
B1-I/O
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B20-I/O
B19-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
A19-I/O
A18-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
MSB
A20-I/O
LSB
=
=
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
Figure 12. 20-Bit PSA/COUNT Configuration (OEAB = 1, OEBA = 0)
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timing description
All test operations of the ’ABTH18504A and ’ABTH182504A are synchronous to the TCK signal. Data on the
TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and
normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as
shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge
to TCK.
A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states, to perform one instruction-register scan and one
data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO is used
to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 details the
operation of the test circuitry during each TCK cycle.
Table 5. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
1
Test-Logic-Reset
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
2
Run-Test/Idle
3
Select-DR-Scan
4
Select-IR-Scan
5
Capture-IR
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
6
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
Shift-IR
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next
TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
14
Exit1-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
15
Update-IR
16
Select-DR-Scan
17
Capture-DR
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
18
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
19–20
Shift-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
21
Exit1-DR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
22
Update-DR
23
Select-DR-Scan
7–13
24
24
Select-IR-Scan
25
Test-Logic-Reset
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
In general, the selected data register is updated with the new data on the falling edge of TCK.
Test operation completed
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Update-DR
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Exit1-DR
Capture-DR
Update-IR
Select-DR-Scan
ÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
TAP
Controller
State
Select-DR-Scan
TDO
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Run-Test/Idle
TDI
Test-Logic-Reset
TMS
Shift-DR
TCK
3-State (TDO) or Don’t Care (TDI)
Figure 13. Timing Example
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI: except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABTH18504A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN54ABTH182504A (A port or TDO) . . . . . . . . . . . . . . . . . 96 mA
SN54ABTH182504A (B port) . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
SN74ABTH18504A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
SN74ABTH182504A (A port or TDO) . . . . . . . . . . . . . . . . 128 mA
SN74ABTH182504A (B port) . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous current through VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 mA
Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):PM package . . . . . . . . . . . . . . . . . . . . 1 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
POST OFFICE BOX 655303
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25
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
recommended operating conditions
SN54ABTH18504A
SN74ABTH18504A
MIN
MAX
MIN
MAX
4.5
5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–24
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
TA
Operating free-air temperature
85
°C
High-level input voltage
2
0.8
Input voltage
0
–55
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
26
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
V
0.8
0
–40
V
VCC
–32
V
V
mA
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
II
IIH
IIL
II(hold)‡
VCC = 4
4.5
5V
–1.2
MAX
SN74ABTH18504A
MIN
–1.2
3
3
3
2
2
IOH = – 32 mA
IOL = 48 mA
2*
OE, TDI, TMS
VCC = 5.5 V,
VI = GND
VI = 0.8 V
VI = 2 V
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE = 2 V
UNIT
V
V
2
0.55
IOL = 64 mA
OE, TDI, TMS
MAX
–1.2
IOH = –3 mA
IOH = –24 mA
VCC = 5.5 V, VI = VCC or GND
VCC = 5.5 V,
VI = VCC
0.55
0.55*
–40
0.55
V
±1
±1
±1
±20
±20
±20
10
10
10
µA
µA
–40
–150
75
220
–150
500
–40
–150
75
500
–75
– 180
–500
–75
–500
µA
µ
µA
10
10
10
µA
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE = 2 V
–10
–10
–10
µA
TDO
VCC = 0 to 2.1 V,
VO = 2.7 V or 0.5 V, OE = 0.8 V
±50
±50
µA
TDO
VCC = 2.1 V to 0,
VO = 2.7 V or 0.5 V, OE = 0.8 V
±50
±50
µA
±100
µA
50
µA
–200
mA
TDO
IOZL
TDO
IOZPU
IOZPD
Outputs high
VCC = 0, VI or VO ≤ 4.5 V
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V,
Outputs high
ICC
MIN
2.5
A or B ports
IOZH
Ioff
ICEX
IO§
SN54ABTH18504A
2.5
VCC = 0 to 5.5 V,
VI = VCC or GND
5V
VCC = 4
4.5
TA = 25°C
TYP† MAX
2.5
CLK, CLKEN,
LE, TCK
A or B ports
MIN
Outputs low
Outputs
disabled
VCC = 5.5 V,
IO = 0,
VI = VCC or
GND
VO = 2.5 V
±100
50
–50
A or B ports
orts
–110
–200
1.6
2.2
2.2
2.2
19
27
27
27
0.9
2
2
2
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
∆ICC¶
Ci
Control inputs
Cio
A or B ports
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
50
1.5
–50
–200
–50
1.5
1.5
mA
mA
5
pF
10
pF
Co
TDO
VO = 2.5 V or 0.5 V
8
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameter II(hold) includes the off-state output leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
SN54ABTH18504A
fclock
tw
Clock frequency
Pulse duration
CLKAB or CLKBA
CLKAB or CLKBA high or low
LEAB or LEBA
CLK high or low
A before CLKAB↑ or B before CLKBA↑
tsu
Setup time
CLK high
A before LEAB↓ or B before LEBA↓
CLK low
CLKEN before CLK↑
A after CLKAB↑ or B after CLKBA↑
th
Hold time
A after LEAB↓ or B after LEBA↓
CLK high or low
CLKEN after CLK↑
MIN
MAX
0
100
SN74ABTH18504A
MIN
MAX
0
100
4.5
4.5
3.5
3.5
3.5
3.5
3.5
3.5
2
2
4
4
0.5
0.5
4
4
0.5
0.5
UNIT
MHz
ns
ns
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
SN54ABTH18504A
fclock
tw
tsu
MAX
50
0
50
TCK
0
TCK high or low
8
8
A, B, CLK, LE, or OE before TCK↑
6
6
4.5
4.5
3
3
1.5
1.5
Setup time
TDI before TCK↑
Hold time
TDI after TCK↑
UNIT
MHz
ns
ns
ns
1
1
TMS after TCK↑
1.5
1.5
Delay time
Power up to TCK↑
50
50
ns
Rise time
VCC power up
1
1
µs
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
28
MIN
Pulse duration
A, B, CLK, LE, or OE after TCK↑
td
tr
MAX
Clock frequency
TMS before TCK↑
th
SN74ABTH18504A
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
CLKAB or
CLKBA
tPLH
tPHL
A or B
B or A
tPLH
tPHL
CLKAB or
CLKBA
B or A
tPLH
tPHL
LEAB or LEBA
B or A
tPZH
tPZL
OEAB or OEBA
B or A
tPHZ
tPLZ
OEAB or OEBA
B or A
VCC = 5 V,
TA = 25°C
SN54ABTH18504A
MAX
MIN
MAX
SN74ABTH18504A
MIN
TYP
100
130
1.5
3.1
5
1.5
6
1.5
5.5
1.5
3.6
5
1.5
6
1.5
5.5
1.5
3.7
5
1.5
6
1.5
5.5
1.5
3.8
5
1.5
6
1.5
5.5
1.5
3.9
5.5
1.5
6.5
1.5
6
1.5
3.6
5.5
1.5
6.5
1.5
6
1.5
4.6
5.8
1.5
7.5
1.5
7
1.5
4.8
5.8
1.5
7.5
1.5
7
3
7.1
8.4
3
9.9
3
9.6
2
5
6.3
2
8.9
2
7.2
100
MIN
UNIT
MAX
100
MHz
ns
ns
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
TCK
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
VCC = 5 V,
TA = 25°C
MIN
TYP
SN54ABTH18504A
MAX
MIN
SN74ABTH18504A
MAX
MIN
50
UNIT
MAX
50
90
2.5
7.4
11
2.5
14.5
2.5
50
13.1
MHz
2.5
7.6
10.8
2.5
14
2.5
12.4
2
3.8
5.1
2
7
2
5.6
2
4
5.1
2
7
2
5.6
4
8
11.5
4
14.5
4
13.4
4
8
11.8
4
15
4
13.6
2
3.9
5.7
2
7.5
2
6.6
2
4.2
6.2
2
8
2
6.9
4
10.8
13
4
18
4
15
3
9.1
13.3
3
17.5
3
15
3
5.3
6.8
3
8
3
7.2
2.5
4.2
5.5
2.5
8
2.5
6.3
ns
ns
ns
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
recommended operating conditions
SN54ABTH182504A
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
High-level input voltage
High level output current
High-level
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
MIN
MAX
4.5
5.5
4.5
5.5
2
0.8
0
A port, TDO
B port
VCC
–24
0
0.8
V
V
A port, TDO
48
64
B port
12
12
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
–40
V
VCC
–32
–12
–55
UNIT
V
–12
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
30
MAX
2
Input voltage
IOH
SN74ABTH182504A
MIN
mA
mA
10
ns/V
85
°C
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
port TDO
A port,
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOH
B port
VCC = 4.5 V,
VCC = 5 V,
5V
VCC = 4
4.5
A port,
port TDO
VCC = 4
4.5
5V
B port
VCC = 4
4.5
5V
II
A or B ports
IIH
IIL
OE, TDI, TMS
OE, TDI, TMS
TA = 25°C
TYP† MAX
SN54ABTH182504A
MIN
–1.2
SN74ABTH182504A
MAX
MIN
–1.2
MAX
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOH = –1 mA
2*
2
3.35
3.3
3.35
IOH = –1 mA
IOH = –3 mA
3.85
3.8
3.85
3.1
3
3.1
IOH = –12 mA
IOL = 48 mA
2.6*
UNIT
V
V
2.6
0.55
0.55
IOL = 64 mA
IOL = 8 mA
0.55*
IOL = 12 mA
VCC = 0 to 5.5 V,
VI = VCC or GND
0.8*
±1
±1
±1
VCC = 5.5 V,
VI = VCC or GND
±20
±20
±20
10
10
10
µA
µA
VOL
CLK, CLKEN,
LE, TCK
MIN
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC
VI = GND
VI = 0.8 V
VI = 2 V
0.55
0.8
0.8
0.65
V
0.8
µA
–40
–40
–150
75
220
–150
500
–40
–150
75
500
–75
–180
–500
–75
–500
µA
II(hold)‡
A or B ports
VCC = 4
4.5
5V
IOZH
TDO
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE = 2 V
10
10
10
µA
IOZL
TDO
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE = 2 V
–10
–10
–10
µA
IOZPU
TDO
VCC = 0 to 2.1 V,
VO = 2.7 V or 0.5 V,
OE = 0.8 V
±50
±50
µA
IOZPD
TDO
VCC = 2.1 V to 0,
VO = 2.7 V or 0.5 V,
OE = 0.8 V
±50
±50
µA
Ioff
ICEX
±100
µA
Outputs high
50
µA
IO§
A port, TDO
B port
Outputs high
ICC
Outputs low
Outputs
disabled
VCC = 0, VI or VO ≤ 4.5 V
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
IO = 0,
VI = VCC or
GND
VO = 2.5 V
VO = 2.5 V
±100
50
50
–50
–110
–200
–50
–200
–50
–200
–25
–55
–100
–25
–100
–25
–100
1.4
2.2
2.2
2.2
25
30
30
30
0.9
2
2
2
A or B ports
orts
mA
mA
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameter II(hold) includes the off-state output leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
∆ICC‡
Ci
Control inputs
Cio
A or B ports
TEST CONDITIONS
MIN
TA = 25°C
TYP† MAX
SN54ABTH182504A
1.5
1.5
VCC= 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
MIN
MAX
SN74ABTH182504A
MIN
MAX
1.5
UNIT
mA
5
pF
10
pF
Co
TDO
8
† All typical values are at VCC = 5 V.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
SN54ABTH182504A
fclock
Clock frequency
tw
Pulse duration
CLKAB or CLKBA
CLKAB or CLKBA high or low
LEAB or LEBA
CLK high or low
A before CLKAB↑ or B before CLKBA↑
tsu
Setup time
A before LEAB↓ or
B before LEBA↓
CLK high
CLK low
CLKEN before CLK↑
A after CLKAB↑ or B after CLKBA↑
th
Hold time
A after LEAB↓ or B after LEBA↓
CLK high or low
CLKEN after CLK↑
SN74ABTH182504A
MIN
MAX
MIN
MAX
0
100
0
100
4.5
4.5
3.5
3.5
3.5
3.5
3.5
3.5
2
2
4
4
0.5
0.5
4
4
0.5
0.5
UNIT
MHz
ns
ns
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
SN54ABTH182504A
fclock
tw
tsu
MAX
50
0
50
0
Pulse duration
TCK high or low
8
8
A, B, CLK, LE, or OE before TCK↑
6
6
4.5
4.5
Setup time
TDI before TCK↑
Hold time
3
3
1.5
1.5
UNIT
MHz
ns
ns
ns
1
1
TMS after TCK↑
1.5
1.5
Delay time
Power up to TCK↑
50
50
ns
Rise time
VCC power up
1
1
µs
TDI after TCK↑
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
32
MIN
TCK
A, B, CLK, LE, or OE after TCK↑
td
tr
MAX
Clock frequency
TMS before TCK↑
th
SN74ABTH182504A
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
CLKAB or
CLKBA
tPLH
tPHL
A
B
tPLH
tPHL
B
A
tPLH
tPHL
CLKAB
B
tPLH
tPHL
CLKBA
A
tPLH
tPHL
LEAB
B
tPLH
tPHL
LEBA
A
tPZH
tPZL
OEAB or OEBA
B or A
tPHZ
tPLZ
OEAB or OEBA
B or A
VCC = 5 V,
TA = 25°C
SN54ABTH182504A
MAX
MIN
MAX
SN74ABTH182504A
MIN
TYP
100
130
1.5
3.5
5
1.5
6
1.5
5.5
1.5
4.1
5.6
1.5
6.4
1.5
6.2
1.5
3.2
5
1.5
6
1.5
5.5
1.5
3.4
5
1.5
6
1.5
5.5
1.5
3.9
5.4
1.5
6.2
1.5
6.1
1.5
4.2
5.8
1.5
6.4
1.5
6.2
1.5
4
5
1.5
6
1.5
5.5
1.5
4.2
5
1.5
6
1.5
5.5
1.5
4.1
5.6
1.5
6.5
1.5
6.3
1.5
4.1
5.6
1.5
6.5
1.5
6.2
1.5
4.1
5.5
1.5
6.5
1.5
6
1.5
3.9
5.5
1.5
6.5
1.5
6
1.5
4.5
5.8
1.5
7.5
1.5
7
1.5
4.5
5.8
1.5
7.5
1.5
7
3
5.5
8.4
3
9.9
3
9.6
2
4.6
6.3
2
8.9
2
7.2
100
MIN
UNIT
MAX
100
MHz
ns
ns
ns
ns
ns
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
TCK
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
VCC = 5 V,
TA = 25°C
MIN
TYP
SN54ABTH182504A
MAX
MIN
SN74ABTH182504A
MAX
MIN
50
UNIT
MAX
50
90
2.5
6.8
11
2.5
14.5
2.5
50
13.1
MHz
2.5
7.2
10.8
2.5
14
2.5
12.4
2
3.6
5.1
2
7
2
5.6
2
3.8
5.1
2
7
2
5.6
4
7.8
11.5
4
14.5
4
13.4
4
7.8
11.8
4
15
4
13.6
2
3.7
5.7
2
7.5
2
6.6
2
3.9
6.2
2
8
2
6.9
4
8.6
13
4
18
4
15
3
7.9
13.3
3
17.5
3
15
3
5.2
6.8
3
8
3
7.2
2.5
4
5.5
2.5
8
2.5
6.3
ns
ns
ns
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
1.5 V
Timing Input
0V
tw
tsu
3V
Input
1.5 V
1.5 V
3V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
1.5 V
0V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
0V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
VOH
1.5 V
3V
Output
Control
tPHL
tPLH
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
th
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 14. Load Circuit and Voltage Waveforms
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
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Copyright  1998, Texas Instruments Incorporated