SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
D Qualified for Military Applications
D ESD Protection Exceeds 2000 V Per
100 nF
SENSE 1
SENSE 2
5
V DD
2
1
20 19
NC
NC
3
NC
4
18 NC
SENSE2
5
17 MR
NC
6
16 NC
SENSE3
7
15 RESET
NC
8
14 NC
NC
10 11 12 13
RESET
9
NC − No internal connection
VDD
SMJ320C6201B
RESET
RESET
TPS3307-18
•
w
w
Military
applications
using
DSPs,
Microcontrollers or Microprocessors
Industrial Equipment
Programmable Controls
GND
SENSE 3
620 kΩ
6
4
VDD
MR
RESET
RESET
1.8 V
VDD
470 kΩ
3
NC
Figure 1 lists some of the typical applications for
the TPS3307 family, and a schematic diagram for
a processor-based system application. This
application uses TI part numbers TPS3307−18
and SMJ320C6201B.
3.3 V
7
FK PACKAGE
(TOP VIEW)
typical applications
2.5 V
8
2
SENSE1
D
D
D
D
D
1
GND
D
SENSE1
SENSE2
SENSE3
GND
NC
D
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Triple Supervisory Circuits for DSP and
Processor-Based Systems
Power-On Reset Generator with Fixed
Delay Time of 200 ms, No External
Capacitor Needed
Temperature-Compensated Voltage
Reference
Maximum Supply Current of 40 µA
Supply Voltage Range . . . 2 V to 6 V
Defined RESET Output from VDD ≥ 1.1 V
CDIP-8 and LCCC-20 Packages
Temperature Range . . . −55°C to 125°C
NC
D
JG PACKAGE
(TOP VIEW)
GND
Figure 1. Applications Using the TPS3307-18
description
The TPS3307-18 is a micropower supply voltage supervisor designed for circuit initialization primarily in
automotive DSP and processor-based systems, which require more than one supply voltage.
The TPS3307-18 is designed for monitoring three independent supply voltages: 3.3 V/1.8 V/adj,. The adjustable
SENSE input allows the monitoring of any supply voltage >1.25 V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
#&! #% -../ %% #"" " ""&
!%" ("*" "&' %% (" #&!/ #&!
#", &" ""%+ %!&" ", %% #""'
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1
SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
description (continued)
The various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in the
following supply voltage monitoring table.
SUPPLY VOLTAGE MONITORING
NOMINAL SUPERVISED VOLTAGE
DEVICE
TPS3307-18
THRESHOLD VOLTAGE (TYP)
SENSE1
SENSE2
SENSE3
SENSE1
SENSE2
3.3 V
1.8 V
User defined
2.93 V
1.68 V
SENSE3
1.25 V†
† The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements.
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remain
below the threshold voltage VIT+.
An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset.
The delay time, td typ = 200 ms, starts after all SENSEn inputs have risen above the threshold voltage VIT+. When
the voltage at any SENSE input drops below the threshold voltage VIT–, the RESET output becomes active (low)
again.
The TPS3307-18 incorporates a manual reset input, MR. A low level at MR causes RESET to become active.
In addition to the active-low RESET output, the TPS3307-18 includes an active-high RESET output.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE‡
TA
−55°C to 125°C
TOP-SIDE
MARKING
Ceramic Dual In Line (JG)
TPS3307-18MJGB
TPS3307-18MJGB
Leadless Ceramic Chip Carrier (FK)
TPS3307-18MFKB
TPS3307-18MFKB
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION/TRUTH TABLES
MR
SENSE1>VIT1
X
SENSE2>VIT2
X
SENSE3>VIT3
X
RESET
RESET
L
L
H
H
0
0
0
L
H
H
0
0
1
L
H
H
0
1
0
L
H
H
0
1
1
L
H
H
1
0
0
L
H
H
1
0
1
L
H
H
1
1
0
L
H
H
1
1
1
H
L
X = Don’t care
2
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SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
functional block diagram
VDD
TPS3307
14 kΩ
MR
R1
+
_
SENSE 1
R2
R3
SENSE 2
R4
+
_
RESET
RESET
Logic + Timer
RESET
GND
Reference
Voltage
of 1.25 V
_
Oscillator
+
SENSE 3
timing diagram
SENSEn
V(nom)
VIT−
t
MR
1
0
t
RESET
1
t
0
td
td
td
RESET Because of SENSE Below VIT
RESET Because of MR
RESET Because of SENSE Below VIT−
RESET Because of SENSE Below VIT−
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3
SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000 h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
JG
1W
6.25 mW/°C
719 mW
625 mW
375 mW
FK
1.39 W
11.58 mW/°C
869 mW
695 mW
232 mW
recommended operating conditions at specified temperature range
MIN
MAX
UNIT
Supply voltage, VDD
2
6
V
Input voltage at MR and SENSE3, VI
0
V
Input voltage at SENSE1 and SENSE2, VI
0
VDD+0.3
(VDD+0.3)VIT/1.25V
High-level input voltage at MR, VIH
0.7xVDD
Low-level input voltage at MR, VIL
Input transition rise and fall rate at MR, ∆t/∆V
Operating free-air temperature range, TA
4
−55
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V
V
0.3×VDD
50
V
ns/V
125
°C
SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
High-level output voltage
Low-level output voltage
Power-up reset voltage (see Note 2)
Vhys
Negative-going input threshold voltage
(see Note 3)
VSENSE2
VDD– 0.2V
VDD– 0.4V
VDD = 6 V,
VDD = 2 V to 6 V,
IOH = −3 mA
IOL = 20 µA
VDD– 0.4V
VDD = 3.3 V,
VDD = 6 V,
IOL = 2 mA
IOL = 3 mA
VDD ≥ 1.1 V,
IOL = 20 µA
VIT− = 1.25 V
VIT− = 1.68 V
VIT− = 2.93 V
MR
IH
High-level input current
IL
Low-level input current
IDD
Ci
Supply current
VDD = 2 V to 6 V
VSENSE1
Hysteresis at VSENSEn input
TYP
IOH = −20 µA
IOH = −2 mA
VSENSE3
VIT−
MIN
VDD = 2 V to 6 V,
VDD = 3.3 V,
VDD = 6 V
VSENSE1 = VDD = 6 V
SENSE2
VSENSE2 = VDD = 6 V
SENSE3
VSENSE3 = VDD
MR
MR = 0 V,
SENSEn
VSENSE1,2,3 = 0 V
UNIT
V
0.2
0.4
V
0.4
0.4
V
1.22
1.25
1.29
V
1.64
1.68
1.73
2.86
2.93
3.02
2
10
30
2
15
40
3
30
60
−130
−180
5
8
6
9
−430
−600
MR = 0.7 × VDD,
SENSE1
MAX
−25
VDD = 6 V
−1
25
1
40
V
mV
µA
nA
µA
A
µΑ
Input capacitance
VI = 0 V to VDD
10
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals.
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5
SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
timing requirements at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
tw
Pulse width
SENSEn
MR
TEST CONDITIONS
VSENSEnL = VIT− −0.2 V,
VIH = 0.7 × VDD,
VSENSEnH = VIT+ +0.2 V
VIL = 0.3 × VDD
MIN
TYP
MAX
UNIT
6
10
µs
100
150
ns
switching characteristics at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
td
Delay time
tPHL
Propagation (delay) time,
high-to-low level output
MR to RESET
MR to RESET
tPLH
Propagation (delay) time,
low-to-high level output
MR to RESET
MR to RESET
tPHL
Propagation (delay) time,
high-to-low level output
SENSEn to RESET
tPLH
Propagation (delay) time,
low-to-high level output
SENSEn to RESET
6
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI(SENSEn) ≥ VIT+ + 0.2 V,
MR ≥ 0.7 × VDD, See timing diagram
140
200
280
ms
200
600
ns
1
5
µss
VI(SENSEn) ≥ VIT+ +0.2 V,
VIH = 0.7 × VDD, VIL = 0.3 × VDD
VIH = VIT+ +0.2 V, VIL = VIT− −0.2 V,
MR ≥ 0.7 × VDD
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SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
NORMALIZED SENSE THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
18
1.005
VDD = 2 V
MR = Open
1.004
16
14
1.003
12
I DD − Supply Current − µ A
Normalized Input Threshold Voltage − VIT(TA), VIT(25 °C)
TYPICAL CHARACTERISTICS
1.002
1.001
1
0.999
0.998
0.997
TPS3307−33
10
8
6
4
2
0
−2
−4
SENSEn = VDD
MR = Open
TA = 25°C
−6
0.996
0.995
−40
−15
10
60
35
−8
−10
−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
85
TA − Free-Air Temperature − °C
VDD − Supply Voltage − V
Figure 3
Figure 2
INPUT CURRENT
vs
INPUT VOLTAGE AT MR
MINIMUM PULSE DURATION AT SENSE
vs
THRESHOLD OVERDRIVE
100
tw − Minimum Pulse Duration at Vsense − µ s
0
10
VDD = 6 V
TA = 25°C
I I − Input Current − µ A
−100
−200
−300
−400
−500
−600
−700
−800
−900
−1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
VDD = 6 V
MR = Open
9
8
7
6
5
4
3
2
1
0
0
100 200 300 400 500 600 700 800 900 1000
VI − Input Voltage at MR − V
SENSE − Threshold Overdrive − mV
Figure 4
Figure 5
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7
SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.5
6.5
VDD = 6 V
MR = Open
6
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
VDD = 2 V
MR = Open
2
1.5
−40°C
1
85°C
0.5
5.5
5
4.5
4
−40°C
3.5
3
85°C
2.5
2
1.5
1
0.5
0
0
0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 −4.5 −5 −5.5 −6
0
−5 −10 −15 −20 −25 −30 −35 −40 −45 −50
IOH − High-Level Output Current − mA
IOH − High-Level Output Current − mA
Figure 6
Figure 7
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
6.5
VDD = 2 V
MR = Open
2
1.5
1
VDD = 6 V
MR = Open
6
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
2.5
85°C
0.5
−40°C
5.5
5
4.5
4
3.5
3
85°C
2.5
2
1.5
−40°C
1
0.5
0
0
0.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
IOL − Low-Level Output Current − mA
1
6
0
0
5
Figure 8
8
10 15 20 25 30 35 40 45 50 55 60
IOL − Low-Level Output Current − mA
Figure 9
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SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
25
5
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003
MECHANICAL INFORMATION
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.063 (1,60)
0.015 (0,38)
0.100 (2,54)
0°−15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
10
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
Falls within MIL-STD-1835 GDIP1-T8
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-9959101Q2A
ACTIVE
LCCC
FK
20
1
None
5962-9959101QPA
ACTIVE
CDIP
JG
8
1
None
POST-PLATE Level-NC-NC-NC
TPS3307-18MFKB
ACTIVE
LCCC
FK
20
1
None
TPS3307-18MJG
ACTIVE
CDIP
JG
8
1
None
A42 SNPB
Level-NC-NC-NC
TPS3307-18MJGB
ACTIVE
CDIP
JG
8
1
None
A42 SNPB
Level-NC-NC-NC
A42 SNPB
Level-NC-NC-NC
POST-PLATE Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
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MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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