DATA SHEET MOS INTEGRATED CIRCUIT MC-4516CD641ES, 4516CD641PS 16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM) Description The MC-4516CD641ES and MC-4516CD641PS are 16,777,216 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on which 8 pieces of 128M SDRAM: µPD45128163 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features • 16,777,216 words by 64 bits organization • Clock frequency and access time from CLK Part number /CAS latency Clock frequency (MAX.) Access time from CLK (MAX.) CL = 3 125 MHz 6 ns CL = 2 100 MHz 6 ns CL = 3 100 MHz 6 ns CL = 2 77 MHz 7 ns CL = 3 125 MHz 6 ns CL = 2 100 MHz 6 ns CL = 3 100 MHz 6 ns CL = 2 77 MHz 7 ns MC-4516CD641ES-A80 MC-4516CD641ES-A10 ★ ★ MC-4516CD641PS-A80 MC-4516CD641PS-A10 • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Quad internal banks controlled by BA0, BA1 (Bank Select) • Programmable burst-length (1, 2, 4, 8 and Full Page) • Programmable wrap sequence (Sequential / Interleave) • Programmable /CAS latency (2, 3) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • Single 3.3 V ±0.3 V power supply • LVTTL compatible • 4,096 refresh cycles/64 ms • Burst termination by Burst Stop command and Precharge command • 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm) • Unbuffered type • Serial PD The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14014EJ5V0DS00 (5th edition) Date Published February 2000 NS CP(K) Printed in Japan The mark • shows major revised points. © 1999 MC-4516CD641ES, 4516CD641PS Ordering Information Part number Clock frequency Package Mounted devices MHz (MAX.) MC-4516CD641ES-A80 MC-4516CD641ES-A10 125 MHz 100 MHz 144-pin Small Outline DIMM 8 pieces of µPD45128163G5 (Rev. E) (Socket Type) (10.16mm (400) TSOP(II)) Edge connector: Gold plated 31.75 mm height ★ MC-4516CD641PS-A80 8 pieces of µPD45128163G5 (Rev. P) 125 MHz (10.16mm (400) TSOP(II)) ★ MC-4516CD641PS-A10 2 100 MHz Data Sheet M14014EJ5V0DS00 MC-4516CD641ES, 4516CD641PS Pin Configuration 144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Vss DQ 32 DQ 33 DQ 34 DQ 35 Vcc DQ 36 DQ 37 DQ 38 DQ 39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ 40 DQ 41 DQ 42 DQ 43 Vcc DQ 44 DQ 45 DQ 46 DQ 47 Vss NC NC Vss DQ 0 DQ 1 DQ 2 DQ 3 VCC DQ 4 DQ 5 DQ 6 DQ 7 Vss DQMB0 DQMB1 VCC A0 A1 A2 Vss DQ 8 DQ 9 DQ 10 DQ 11 VCC DQ 12 DQ 13 DQ 14 DQ 15 Vss NC NC CLK0 CKE0 Vcc Vcc /RAS /CAS /WE CKE1 /CS0 NC /CS1 NC NC CLK1 Vss Vss NC NC NC NC VCC Vcc DQ 16 DQ 48 DQ 17 DQ 49 DQ 18 DQ 50 DQ 19 DQ 51 Vss Vss DQ 20 DQ 52 DQ 21 DQ 53 DQ 22 DQ 54 DQ 23 DQ 55 Vcc Vcc A6 A7 A8 BA0 (A13) Vss Vss A9 BA1 (A12) A10 A11 Vcc Vcc DQMB2 DQMB6 DQMB3 DQMB7 Vss Vss DQ 24 DQ 56 DQ 25 DQ 57 DQ 58 DQ 26 DQ 59 DQ 27 VCC Vcc DQ 60 DQ 28 DQ 61 DQ 29 DQ 62 DQ 30 DQ 63 DQ 31 Vss Vss SCL SDA VCC Vcc 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Data Sheet M14014EJ5V0DS00 /xxx indicates active low signal. A0 - A11 : Address Inputs [Row: A0 - A11, Column: A0 - A8] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0 - DQ63 : Data Inputs/Outputs CLK0, CLK1 : Clock Input CKE0, CKE1 : Clock Enable Input /CS0, /CS1 : Chip Select Input /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQMB0 - DQMB7 : DQ Mask Enable SDA : Serial Data I/O for PD SCL : Clock Input for PD VCC : Power Supply VSS : Ground NC : No Connection 3 MC-4516CD641ES, 4516CD641PS Block Diagram CKE1 CKE0 /CS1 /CS0 UDQM /CS CKE DQ 7 LDQM /CS CKE DQ 8 DQMB1 DQ 8 DQ 1 DQ 6 DQ 9 DQ 2 DQ 5 DQ 3 UDQM /CS CKE DQ 7 LDQM /CS CKE DQ 9 DQ 6 DQ 9 DQ 10 DQ 10 DQ 5 DQ 10 DQ 4 DQ 11 DQ 11 DQ 4 DQ 11 DQ 4 DQ 3 DQ 12 DQ 12 DQ 3 DQ 12 DQ 5 DQ 2 DQ 13 DQ 13 DQ 2 DQ 13 DQ 6 DQ 1 DQ 14 DQ 14 DQ 1 DQ 7 DQ 0 DQ 15 DQ 0 DQMB0 DQ 0 D0 D4 DQ 15 DQ 14 D2 DQ 15 D6 LDQM DQ 0 DQMB5 DQ 40 DQ 15 UDQM DQ 0 DQ 1 DQ 41 DQ 14 DQ 1 DQ 13 DQ 2 DQ 42 DQ 13 DQ 2 DQ 35 DQ 12 DQ 3 DQ 43 DQ 12 DQ 3 DQ 36 DQ 11 DQ 4 DQ 44 DQ 11 DQ 4 DQ 37 DQ 10 DQ 5 DQ 45 DQ 10 DQ 5 DQ 38 DQ 9 DQ 6 DQ 46 DQ 9 DQ 6 DQ 39 DQ 8 DQ 7 DQ 47 DQ 8 DQ 7 UDQM /CS CKE LDQM /CS CKE LDQM /CS CKE DQ 8 DQMB3 DQ 24 UDQM /CS CKE DQ 7 DQ 7 DQ 8 DQ 17 DQ 6 DQ 9 DQ 25 DQ 6 DQ 9 DQ 18 DQ 5 DQ 10 DQ 26 DQ 5 DQ 10 DQ 19 DQ 4 DQ 11 DQ 27 DQ 4 DQ 11 DQ 20 DQ 3 DQ 12 DQ 28 DQ 3 DQ 12 DQ 21 DQ 2 DQ 13 DQ 29 DQ 2 DQ 13 DQ 22 DQ 1 DQ 14 DQ 30 DQ 1 DQ 23 DQ 0 DQ 31 DQ 0 DQMB4 DQ 32 LDQM UDQM DQ 15 DQ 33 DQ 14 DQ 34 DQMB2 DQ 16 D1 D5 DQ 15 LDQM UDQM DQ 48 DQ 15 DQ 49 DQ 14 DQ 50 DQ 14 D3 DQ 15 LDQM UDQM DQ 0 DQMB7 DQ 56 DQ 15 DQ 0 DQ 1 DQ 57 DQ 14 DQ 1 DQ 13 DQ 2 DQ 58 DQ 13 DQ 2 DQ 51 DQ 12 DQ 3 DQ 59 DQ 12 DQ 3 DQ 52 DQ 11 DQ 4 DQ 60 DQ 11 DQ 4 DQ 53 DQ 10 DQ 5 DQ 61 DQ 10 DQ 5 DQ 54 DQ 9 DQ 6 DQ 62 DQ 9 DQ 6 DQ 55 DQ 8 DQ 7 DQ 63 DQ 8 DQ 7 DQMB6 SERIAL PD VCC D0 - D7 C SCL SDA A0 A1 VSS A0 - A11 D0 - D7 A2 CLK0 A0 - A11 : D0 - D7 BA0 A13 : D0 - D7 BA1 A12 : D0 - D7 CLK : D0 - D3 CLK1 CLK : D4 - D7 /RAS /RAS : D0 - D7 /CAS /CAS : D0 - D7 /WE /WE : D0 - D7 Remarks 1. D0 - D7: µPD45128163 (2M words x 16 bits x 4 banks) 2. The value of all resistors is 10 Ω. 4 DQ 8 Data Sheet M14014EJ5V0DS00 D7 MC-4516CD641ES, 4516CD641PS Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Voltage on power supply pin relative to GND VCC –0.5 to +4.6 V Voltage on input pin relative to GND VT –0.5 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 8 W Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg –55 to +125 °C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 3.3 3.6 V Supply voltage VCC 3.0 High level input voltage VIH 2.0 VCC + 0.3 V Low level input voltage VIL –0.3 + 0.8 V Operating ambient temperature TA 0 70 °C MAX. Unit pF Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Data input/output capacitance Symbol Test condition MIN. CI1 A0 - A11, BA0(A13), BA1(A12), /RAS, /CAS, /WE 30 60 CI2 CLK0, CLK1 23 37 CI3 CKE0, CKE1 18 30 CI4 /CS0, /CS1 18 30 CI5 DQMB0 - DQMB7 7 14 CI/O DQ0 - DQ63 9 18 Data Sheet M14014EJ5V0DS00 TYP. pF 5 MC-4516CD641ES, 4516CD641PS DC Characteristics (Recommended Operating Conditions unless otherwise noted) Parameter Operating current Symbol ICC1 Test condition Burst length = 1, tRC ≥ tRC(MIN.) MIN. /CAS latency = 2 /CAS latency = 3 Precharge standby current in ★ power down mode Precharge standby current in ICC2P ICC2PS ICC2N ICC2NS power down mode Active standby current in ICC3P ICC3PS ICC3N ICC3NS 560 mA 1 -A10 560 -A80 560 -A10 560 8 CKE ≤ VIL(MAX.), tCK = ∞ 8 CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.), 160 CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable. 64 CKE ≤ VIL(MAX.), tCK = 15 ns 40 CKE ≤ VIL(MAX.), tCK = ∞ 32 CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.), 240 ICC4 CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable. tCK ≥ tCK(MIN.), IO = 0 mA /CAS latency = 2 /CAS latency = 3 ICC5 tRC ≥ tRC(MIN.) /CAS latency = 2 /CAS latency = 3 ★ -A80 CKE ≤ VIL(MAX.), tCK = 15 ns (Burst mode) ★ CBR (Auto) refresh current Notes mA mA mA mA Input signals are changed one time during 30 ns. non power down mode Operating current Unit Input signals are changed one time during 30 ns. non power down mode Active standby current in MAX. Self refresh current ICC6 CKE ≤ 0.2 V Input leakage current II(L) VI = 0 to 3.6 V, All other pins not under test = 0 V Output leakage current IO(L) High level output voltage Low level output voltage 160 -A80 700 -A10 560 -A80 820 -A10 680 -A80 1,040 -A10 1,040 -A80 1,040 -A10 1,040 mA 2 mA 3 16 mA –8 +8 µA DOUT is disabled, VO = 0 to 3.6 V –3 +3 µA VOH IO = – 4.0 mA 2.4 VOL IO = + 4.0 mA V 0.4 V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.). 6 Data Sheet M14014EJ5V0DS00 MC-4516CD641ES, 4516CD641PS AC Characteristics (Recommended Operating Conditions unless otherwise noted) ★ Test Conditions Parameter AC high level input voltage / low level input voltage Value Unit 2.4 / 0.4 V 1.4 V 1 ns 1.4 V Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level tCK tCH CLK tCL 2.4 V 1.4 V 0.4 V tSETUP tHOLD Input 2.4 V 1.4 V 0.4 V tAC tOH Output Data Sheet M14014EJ5V0DS00 7 MC-4516CD641ES, 4516CD641PS Synchronous Characteristics Parameter Clock cycle time Access time from CLK Symbol -A80 -A10 Unit MIN. MAX. MIN. MAX. /CAS latency = 3 tCK3 8 (125 MHz) 10 (100 MHz) ns /CAS latency = 2 tCK2 10 (100 MHz) 13 (77 MHz) ns /CAS latency = 3 tAC3 6 6 ns 1 /CAS latency = 2 tAC2 6 7 ns 1 CLK high level width tCH 3 3 ns CLK low level width tCL 3 3 ns Data-out hold time tOH 3 3 ns Data-out low-impedance time tLZ 0 0 ns /CAS latency = 3 tHZ3 3 6 3 6 ns /CAS latency = 2 tHZ2 3 6 3 7 ns Data-in setup time tDS 2 2 ns Data-in hold time tDH 1 1 ns Address setup time tAS 2 2 ns Address hold time tAH 1 1 ns CKE setup time tCKS 2 2 ns CKE hold time tCKH 1 1 ns CKE setup time (Power down exit) tCKSP 2 2 ns Command (/CS0, /CS1, /RAS, /CAS, /WE, DQMB0 - DQMB7) setup time tCMS 2 2 ns Command (/CS0, /CS1, /RAS, /CAS, /WE, DQMB0 - DQMB7) hold time tCMH 1 1 ns Data-out high-impedance time Note 1. Output load Z = 50 Ω Output 50 pF Remark These specifications are applied to the monolithic device. 8 Note Data Sheet M14014EJ5V0DS00 1 MC-4516CD641ES, 4516CD641PS Asynchronous Characteristics Parameter Symbol -A80 MIN. Unit -A10 MAX. MIN. MAX. ACT to REF/ACT command period (Operation) tRC 70 70 ns REF to REF/ACT command period (Refresh) tRC1 70 78 ns ACT to PRE command period tRAS 48 PRE to ACT command period tRP 20 20 ns Delay time ACT to READ/WRITE command tRCD 20 20 ns ACT(one) to ACT(another) command period tRRD 16 20 ns Data-in to PRE command period tDPL 8 10 ns 120,000 50 120,000 ns Data-in to ACT(REF) command /CAS latency = 3 tDAL3 1CLK+20 1CLK+20 ns period (Auto precharge) /CAS latency = 2 tDAL2 1CLK+20 1CLK+20 ns tRSC 2 2 CLK tT 0.5 Mode register set cycle time Transition time Refresh time (4,096 refresh cycles) tREF Data Sheet M14014EJ5V0DS00 30 64 1 Note 30 ns 64 ms 9 MC-4516CD641ES, 4516CD641PS Serial PD (1/2) Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 0 Defines the number of bytes written into serial PD memory 80H 1 0 0 0 0 0 0 0 128 bytes 1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes 2 Fundamental memory type 04H 0 0 0 0 0 1 0 0 SDRAM 3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows 4 Number of columns 09H 0 0 0 0 1 0 0 1 9 columns 5 Number of banks 02H 0 0 0 0 0 0 1 0 2 banks 6 Data width 40H 0 1 0 0 0 0 0 0 64 bits 7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0 8 Voltage interface 01H 0 0 0 0 0 0 0 1 LVTTL 9 CL = 3 Cycle time -A80 80H 1 0 0 0 0 0 0 0 8 ns -A10 A0H 1 0 1 0 0 0 0 0 10 ns -A80 60H 0 1 1 0 0 0 0 0 6 ns -A10 10 CL =3 Access time 60H 0 1 1 0 0 0 0 0 6 ns 11 DIMM configuration type 00H 0 0 0 0 0 0 0 0 None 12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal 13 SDRAM width 10H 0 0 0 1 0 0 0 0 ×16 14 Error checking SDRAM width 00H 0 0 0 0 0 0 0 0 None 15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock 16 Burst length supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F 17 Number of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks 18 /CAS latency supported 06H 0 0 0 0 0 1 1 0 2, 3 19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0 20 /WE latency supported 01H 0 0 0 0 0 0 0 1 0 21 SDRAM module attributes 00H 0 0 0 0 0 0 0 0 22 SDRAM device attributes : General 0EH 0 0 0 0 1 1 1 0 23 CL = 2 Cycle time 24 CL = 2 Access time -A80 A0H 1 0 1 0 0 0 0 0 10 ns -A10 D0H 1 1 0 1 0 0 0 0 13 ns -A80 60H 0 1 1 0 0 0 0 0 6 ns 7 ns -A10 70H 0 1 1 1 0 0 0 0 00H 0 0 0 0 0 0 0 0 -A80 14H 0 0 0 1 0 1 0 0 20 ns -A10 14H 0 0 0 1 0 1 0 0 20 ns -A80 10H 0 0 0 1 0 0 0 0 16 ns -A10 14H 0 0 0 1 0 1 0 0 20 ns -A80 14H 0 0 0 1 0 1 0 0 20 ns -A10 14H 0 0 0 1 0 1 0 0 20 ns -A80 30H 0 0 1 1 0 0 0 0 48 ns -A10 32H 0 0 1 1 0 0 1 0 50 ns 10H 0 0 0 1 0 0 0 0 64M bytes 25-26 27 28 tRRD(MIN.) 29 tRCD(MIN.) 30 tRAS(MIN.) 31 10 tRP(MIN.) Module bank density Data Sheet M14014EJ5V0DS00 MC-4516CD641ES, 4516CD641PS (2/2) Byte No. 32 33 34 35 Function Described 63 64-71 72 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 20H 0 0 1 0 0 0 0 0 2 ns signal setup time -A10 20H 0 0 1 0 0 0 0 0 2 ns Command and address -A80 10H 0 0 0 1 0 0 0 0 1 ns signal hold time -A10 10H 0 0 0 1 0 0 0 0 1 ns Data signal input setup time -A80 20H 0 0 1 0 0 0 0 0 2 ns -A10 20H 0 0 1 0 0 0 0 0 2 ns -A80 10H 0 0 0 1 0 0 0 0 1 ns -A10 10H 0 0 0 1 0 0 0 0 1 ns 00H 0 0 0 0 0 0 0 0 -A80 12H 0 0 0 1 0 0 1 0 1.2 A -A10 12H 0 0 0 1 0 0 1 0 1.2 A Checksum -A80 E8H 1 1 1 0 1 0 0 0 for bytes 0 - 62 -A10 4EH 0 1 1 0 1 1 1 0 -A80 64H 0 1 1 0 0 1 0 0 100 MHz -A10 64H 0 1 1 0 0 1 0 0 100 MHz Intel specification /CAS -A80 C7H 1 1 0 0 0 1 1 1 latency support -A10 C5H 1 1 0 0 0 1 0 1 Data signal input hold time SPD revision Manufacture’s JEDEC ID code Manufacturing location Manufacture’s P/N 91-92 Revision code 93-94 Manufacturing date 95-98 Assembly serial number 99-125 Mfg specific 127 Bit 6 -A80 73-90 126 Bit 7 Command and address 36-61 62 Hex Intel specification frequency Timing Chart Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E). Data Sheet M14014EJ5V0DS00 11 MC-4516CD641ES, 4516CD641PS ★ Package Drawings [MC-4516CD641ES] 144-PIN DUAL IN-LINE MODULE (SOCKET TYPE) A (AREA B) M1 (AREA B) Y N Z R Q M L M2 (AREA A) S A H U1 U2 T (OPTIONAL HOLES) C I B E D A1 (AREA A) F ITEM detail of A part W D2 D1 X V MILLIMETERS A 67.6 A1 67.6±0.15 B 23.2 C 29.0 D 4.6 D1 1.5±0.10 D2 4.0 E F 32.8 3.7 H 0.8 (T.P.) I L 3.3 20.0 M M1 31.75±0.15 9.75 M2 22.0 N 3.8 MAX. Q R2.0 R 4.00±0.10 S φ 1.8 T U1 1.0±0.1 3.2 MIN. U2 4.0 MIN. V W 0.25 MAX. 0.6±0.05 X Y 2.55 MIN. 2.0 MIN. Z 2.0 MIN. M144S-80A14 12 Data Sheet M14014EJ5V0DS00 MC-4516CD641ES, 4516CD641PS [MC-4516CD641PS] 144-PIN DUAL IN-LINE MODULE (SOCKET TYPE) A (AREA B) M1 (AREA B) Y N Z R Q M L M2 (AREA A) S A H U1 U2 T (OPTIONAL HOLES) C I B E D A1 (AREA A) F ITEM detail of A part W D2 D1 X V MILLIMETERS A 67.6 A1 67.6±0.15 B 23.2 C 29.0 D 4.6 D1 1.5±0.10 D2 4.0 E F 32.8 3.7 H 0.8 (T.P.) I L 3.3 20.0 M M1 31.75±0.15 9.75 M2 22.0 N 3.8 MAX. Q R2.0 R 4.00±0.10 S φ 1.8 T U1 1.0±0.1 3.2 MIN. U2 4.0 MIN. V W 0.25 MAX. 0.6±0.05 X Y 2.55 MIN. 2.0 MIN. Z 2.0 MIN. M144S-80A16 Data Sheet M14014EJ5V0DS00 13 MC-4516CD641ES, 4516CD641PS [MEMO] 14 Data Sheet M14014EJ5V0DS00 MC-4516CD641ES, 4516CD641PS NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14014EJ5V0DS00 15 MC-4516CD641ES, 4516CD641PS CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8