DATA SHEET MOS INTEGRATED CIRCUIT MC-45V8AB642KS 8M-WORD BY 64-BIT VirtualChannel DYNAMIC RAM MODULE (SO DIMM) TM Description The MC-45V8AB642KS is a 8,388,608 words by 64 bits VirtualChannel dynamic RAM module (small outline DIMM) on which 4 pieces of 128M VirtualChannel DRAM : µPD45V128161 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features • 8,388,608 words by 64 bits organization • Clock frequency and access time from CLK Part number Read Clock Access time latency frequency from CLK Maximum supply current mA Operating MHz (MAX.) ns (MAX.) Prefetch Restore Refresh Channel Auto Self 920 8 read / write (Burst) MC-45V8AB642KS-A75 2 133 5.4 600 300 • Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Dual internal banks controlled by BA0 (Bank Select) • Programmable wrap sequence (interleave) • Read latency (2) • Prefetch read latency (4) • Auto precharge and without auto precharge • Auto refresh and self refresh • Single 3.3 V ± 0.3 V power supply • Interface: LVTTL • Refresh cycle: 4K cycles/64 ms • 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm) • Unbuffered type • Serial PD • Programmable burst length (4) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0028N11 (Ver. 1.1) (Previous No. M15239EJ1V0DS00) Date Published April 2001 CP (K) Printed in Japan This Product became EOL in January, 2003. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. MC-45V8AB642KS Ordering Information Clock Part number frequency MHz (MAX.) MC-45V8AB642KS-A75 133 Read latency 2 Prefetch read Package Mounted devices latency 4 144-pin Small Outline DIMM 4 pieces of µPD45V128161G5 (Socket Type) (10.16 mm (400) TSOP (II)) Edge connector : Gold plated 25.4 mm height 2 E0028N11 MC-45V8AB642KS Pin Configuration 144-pin Small Outline Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal. Vss DQ 32 DQ 33 DQ 34 DQ 35 Vcc DQ 36 DQ 37 DQ 38 DQ 39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ 40 DQ 41 DQ 42 DQ 43 Vcc DQ 44 DQ 45 DQ 46 DQ 47 Vss NC NC Vss DQ 0 DQ 1 DQ 2 DQ 3 VCC DQ 4 DQ 5 DQ 6 DQ 7 Vss DQMB0 DQMB1 VCC A0 A1 A2 Vss DQ 8 DQ 9 DQ 10 DQ 11 VCC DQ 12 DQ 13 DQ 14 DQ 15 Vss NC NC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 CLK0 CKE0 Vcc Vcc /RAS /CAS /WE NC /CS0 NC NC NC NC CLK1 Vss Vss NC NC NC NC VCC Vcc DQ 16 DQ 48 DQ 17 DQ 49 DQ 18 DQ 50 DQ 19 DQ 51 Vss Vss DQ 20 DQ 52 DQ 21 DQ 53 DQ 22 DQ 54 DQ 23 DQ 55 Vcc Vcc A6 A7 A8 BA0 (A13) Vss Vss A9 A12 A10 A11 Vcc Vcc DQMB2 DQMB6 DQMB3 DQMB7 Vss Vss DQ 24 DQ 56 DQ 25 DQ 57 DQ 26 DQ 58 DQ 27 DQ 59 VCC Vcc DQ 28 DQ 60 DQ 29 DQ 61 DQ 30 DQ 62 DQ 31 DQ 63 Vss Vss SDA SCL VCC Vcc 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 A0 - A12 : Address Inputs [Row: A0 - A12, Column: A0 - A6] BA0 (A13) : VirtualChannel DRAM Bank Select DQ0 - DQ63 : Data Inputs/Outputs CLK0, CLK1 : Clock Input CKE0 : Clock Enable Input /CS0 : Chip Select Input /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQMB0 - DQMB7 : DQ Mask Enable SDA : Serial Data I/O for PD SCL : Clock Input for PD 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 VCC : Power Supply VSS : Ground NC : No Connection E0028N11 3 MC-45V8AB642KS Block Diagram /WE /CS0 LDQM DQMB0 DQ 0 /CS /WE LDQM DQMB4 DQ 32 DQ 0 DQ 1 DQ 1 DQ 33 DQ 1 DQ 2 DQ 2 DQ 34 DQ 2 DQ 3 DQ 3 DQ 35 DQ 3 DQ 4 DQ 4 DQ 36 DQ 4 DQ 5 DQ 5 DQ 37 DQ 5 DQ 6 DQ 6 DQ 38 DQ 6 DQ 7 DQ 7 DQ 39 DQ 7 UDQM DQ 0 D0 UDQM DQMB1 DQ 8 DQ 15 DQMB5 DQ 40 DQ 9 DQ 14 DQ 41 DQ 14 DQ 10 DQ 13 DQ 42 DQ 13 DQ 11 DQ 12 DQ 43 DQ 12 DQ 12 DQ 11 DQ 44 DQ 11 DQ 13 DQ 10 DQ 45 DQ 10 DQ 14 DQ 9 DQ 46 DQ 9 DQ 15 DQ 8 DQ 47 DQ 8 LDQM /CS /WE LDQM DQMB6 DQ 48 DQ 7 DQ 17 DQ 6 DQ 49 DQ 6 DQ 18 DQ 5 DQ 50 DQ 5 DQ 19 DQ 4 DQ 51 DQ 4 DQ 20 DQ 3 DQ 52 DQ 3 DQ 2 DQ 53 DQ 2 DQ 1 DQ 54 DQ 1 DQ 55 DQ 0 DQ 23 DQ 7 DQ 22 D1 DQ 0 UDQM DQMB3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 8 DQ 8 DQ 9 DQ 57 DQ 9 DQ 10 DQ 58 DQ 10 DQ 11 DQ 59 DQ 11 DQ 12 DQ 60 DQ 12 DQ 61 DQ 13 DQ 62 DQ 14 DQ 63 DQ 15 DQ 13 DQ 30 DQ 14 DQ 31 DQ 15 SERIAL PD D3 UDQM DQMB7 DQ 56 DQ 29 /WE /CS DQ 28 D2 DQ 15 DQMB2 DQ 16 DQ 21 /WE /CS VCC D0 - D3 C SCL VSS SDA A0 A1 A2 10 Ω CLK0 CLK : D0 - D3 BA0 Remark A0 - A12 : D0 - D3 /CAS A13 : D0 - D3 CKE0 D0 - D3: µPD45V128161 (4M words × 16 bits × 2 banks) CLK1 10 pF /RAS A0 - A12 D0 - D3 /RAS : D0 - D3 /CAS : D0 - D3 CKE : D0 - D3 4 E0028N11 MC-45V8AB642KS Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Voltage on power supply pin relative to GND VCC –0.5 to +4.6 V Voltage on input pin relative to GND VT –0.5 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 4 W Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Supply voltage High level input voltage Low level input voltage Symbol Condition MIN. TYP. MAX. Unit VCC 3.0 3.3 3.6 V VIH 2.0 VCC + 0.3 V VIL −0.3 +0.8 V TA 0 70 °C Operating ambient temperature Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Test condition MIN. CI1 A0 - A12, BA0 (A13), /RAS, /CAS, /WE CI2 CLK0 CI3 CKE0 CI4 /CS0 CI5 DQMB0 - DQMB7 CI/O DQ0 - DQ63 TYP. MAX. Unit 15 30 pF 23 37 15 26 15 26 5 10 5 12 Data input/output capacitance Symbol Parameter pF E0028N11 5 MC-45V8AB642KS DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition Operating current (Prefetch ICC1P mode at one bank active) Grade tRC ≥ tRC (MIN.) MIN. MAX. Unit Notes -A75 600 mA 1 -A75 600 mA 1 4.8 mA Prefetch is executed one time during tRC. Operating current (Restore ICC1R tRC ≥ tRC (MIN.) ICC2P CKE ≤ VIL (MAX.), tCK = 15 ns mode at one bank active) Precharge standby current in power down mode Precharge standby current ICC2PS CKE ≤ VIL (MAX.), tCK = ∞ ICC2N in non power down mode Active standby current in power down mode Active standby current in 4.8 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 80 ICC2NS CKE ≥ VIH (MIN.), tCK = ∞ , Input signals are stable. ICC3P ICC3N 24 24 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 120 ICC3NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable. ICC4 tCK ≥ tCK (MIN.), IO = 0 mA ICC5 tRCF ≥ tRCF Self refresh current ICC6 CKE ≤ 0.2 V Input leakage current II (L) VI = 0 to 3.6 V, All other pins not under test = 0 V (MIN.) 80 -A75 300 mA 2 -A75 920 mA 3 -A75 Low level output voltage mA Background : precharge standby Auto Refresh current High level output voltage mA Input signals are changed one time during 30 ns. (Burst mode) Output leakage current 40 CKE ≤ VIL (MAX.), tCK = 15 ns ICC3PS CKE ≤ VIL (MAX.), tCK = ∞ non power down mode Operating current mA Input signals are changed one time during 30 ns. 8 mA –4 +4 µA +1.5 µA IO (L) DOUT is disabled, VO = 0 to 3.6 V –1.5 VOH IO = – 4.0 mA 2.4 VOL IO = + 4.0 mA V 0.4 V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). 6 E0028N11 MC-45V8AB642KS AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions • AC measurements assume tT = 1 ns. • Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. • If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.). • An access time is measured at 1.4 V. tCK tCK tCL tCH tCL CLK tCKH tCKS CKE tS Command Address DQM (Input) tH Valid tDS Valid tAC Hi-Z tDH Valid tAC tLZ Data (Output) tDS Data (Input) tDH tOH Valid tHZ Hi-Z Valid E0028N11 7 MC-45V8AB642KS AC characteristics Parameter Symbol -A75 Unit MIN. MAX. tCK2 7.5 − ns Access time from CLK tAC2 − 5.4 ns CLK high level width tCH 2.5 − ns CLK low level width t CL 2.5 − ns Data-out hold time tOH 2.7 − ns Data-out low-impedance time tLZ 0 − ns Data-out high-impedance time tHZ2 2.5 5.4 ns Data-in setup time tDS 1.5 − ns Data-in hold time tDH 0.8 − ns Address, Command, DQM setup time tS 1.5 − ns tH 0.8 − ns tCKS 1.5 − ns − ns Clock cycle time Address, Command, DQM hold time CKE setup time CKE hold time tCKH 0.8 CKE setup time (Power down exit) tCKSP 1.5 − ns tT 0.5 30 ns Refresh time (4,096 refresh cycle) tREF − 64 ms Mode register set cycle time tRSC 2 − CLK Transition time 1 1 Note 1. Output load. Note Z = 50 Ω Output 50 pF 8 E0028N11 MC-45V8AB642KS AC characteristics (Background to Background operation) Parameter Symbol -A 75 Unit Notes MIN. MAX. tRC 67.5 − ns REF to REF/ ACT Command period tRCF 67.5 − ns ACT to PRE Command period tRAS 52.5 120,000 ns PRE to ACT / REF Command period tRP 20 − ns ACT to PFC/PFCA Command delay time tAPD 15 − ns ACT to PFR Command delay time (Prefetch Read Operation) tAPRD ACT to ACT/REF Command period 15 − ns PFC to PRE Command delay time t PPL 22.5 − ns PFCA / PFR to ACT/REF Command delay time tPAL 45 − ns tRAD 7.5 30 ns tRPD 37.5 − ns tPPD 22.5 − ns RST / RSTA to ACT(R) Note1 Command delay time 2 ACT(R) Note1 to PFC/PFCA/PFR Command delay time PFC to PFC / PFCA Command delay time tRRD 15 − ns ACT(R) to ACT(R) Command delay time tRRDR 30 − ns PFC /PFCA to RST /RSTA Command delay time tPRD 22.5 − ns ACT to ACT/ACT(R) or ACT(R) to ACT Command delay time Notes 1. ACT (R) command is ACT command after RST command. 2. The another background operation and same channel foreground operation are illegal while tRAD period. E0028N11 9 MC-45V8AB642KS AC characteristics (Foreground to Foreground operation) Parameter Symbol READ/WRITE to READ/WRITE Command delay time -A 75 Unit MIN. MAX. 7.5 − tCCD Note ns AC characteristics (Background to Foreground operation) (after same channel Prefetch/Restore) Parameter Symbol -A 75 Unit MIN. MAX. PFC/PFCA to READ/WRITE Command delay time tPCD 15 − ns ACT(R) to READ/WRITE Command delay time tRCD 30 − ns Note 1 Note 1. ACT (R) command is ACT command after RST command. 10 E0028N11 MC-45V8AB642KS Serial PD Byte No. 0 (1/2) Function Described Defines the number of bytes written Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 80H 1 0 0 0 0 0 0 0 128 bytes 08H 0 0 0 0 1 0 0 0 256 bytes into serial PD memory 1 Total number of bytes of serial PD memory Fundamental memory type 08H 0 0 0 0 1 0 0 0 VC DRAM 3 Number of row addresses 0DH 0 0 0 0 1 1 0 1 13 rows 4 Number of column addresses 07H 0 0 0 0 0 1 1 1 7 columns 5 Number of banks 01H 0 0 0 0 0 0 0 1 1 bank 6 Data width 40H 0 1 0 0 0 0 0 0 64 bits 7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0 8 Voltage interface standard 01H 0 0 0 0 0 0 0 1 LVTTL 9 Read latency (/CAS latency) = 2 -A75 75H 0 1 1 1 0 1 0 1 7.5 ns 2 cycle time 10 Read latency (/CAS latency) = 2 -A75 54H 0 1 0 1 0 1 0 0 5.4 ns access time DIMM configuration type 00H 0 0 0 0 0 0 0 0 None 12 Refresh rate / type 80H 1 0 0 0 0 0 0 0 Normal 13 VC DRAM width 10H 0 0 0 1 0 0 0 0 ×16 14 Error checking DRAM width 00H 0 0 0 0 0 0 0 0 None 15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock 16 Burst length supported 04H 0 0 0 0 0 1 0 0 4 17 Number of banks on each VC DRAM 02H 0 0 0 0 0 0 1 0 2 banks 18 Read latency (/CAS latency) supported 02H 0 0 0 0 0 0 1 0 2 19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0 20 /WE latency supported 01H 0 0 0 0 0 0 0 1 0 21 VC DRAM module attributes 00H 0 0 0 0 0 0 0 0 22 VC DRAM device attributes : general 0EH 0 0 0 0 1 1 1 0 00H 0 0 0 0 0 0 0 0 23-26 11 27 tRP (MIN.) -A75 14H 0 0 0 1 0 1 0 0 20 ns 28 tRRD (MIN.) -A75 0FH 0 0 0 0 1 1 1 1 15 ns 29 tAPD (MIN.) -A75 0FH 0 0 0 0 1 1 1 1 15 ns 30 tRAS (MIN.) -A75 34H 0 0 1 1 0 1 0 0 52.5 ns E0028N11 11 MC-45V8AB642KS (2/2) Byte No. Function Described 31 Module bank density 32 Address and command signal Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 10H 0 0 0 1 0 0 0 0 64M bytes -A75 15H 0 0 0 1 0 1 0 1 1.5 ns -A75 08H 0 0 0 0 1 0 0 0 0.8 ns input setup time 33 Address and command signal input hold time Data signal input setup time -A75 15H 0 0 0 1 0 1 0 1 1.5 ns 35 Data signal input hold time -A75 08H 0 0 0 0 1 0 0 0 0.8 ns 36 Prefetch read latency -A75 04H 0 0 0 0 0 1 0 0 4 clocks 37 tPCD (MIN.) -A75 0FH 0 0 0 0 1 1 1 1 15 ns 38 Number of segment addresses 02H 0 0 0 0 0 0 1 0 2 bits 39 Number of channels 04H 0 0 0 0 0 1 0 0 16 40 Depth of channels 07H 0 0 0 0 0 1 1 1 128 bits 2.0 34 41-61 62 SPD revision 63 Checksum for bytes 0 - 62 64-71 72 -A75 02H 0 0 0 0 0 0 1 0 2AH 0 0 1 0 1 0 1 0 Manufacture’s JEDEC ID code Manufacturing location Manufacture’s P/N 91-92 Revision code 93-94 Manufacturing date 95-98 Assembly serial number 99-125 Mfg specific Timing Charts 73-90 Please refer to the µPD45V128421, 45V128821, 45V128161 Data sheet (E0025N). 12 E0028N11 MC-45V8AB642KS Package Drawing 144-PIN DUAL IN-LINE MODULE (SOCKET TYPE) A (AREA B) Y M1 (AREA B) R M2 (AREA A) N Q M L S A H (OPTIONAL HOLES) I U1 U2 C T E B D A1 (AREA A) F MILLIMETERS 67.6 A1 67.6±0.15 B 23.2 C 29.0 D 4.6 detail of A part ITEM A W D2 D1 X V D1 1.5±0.10 D2 4.0 E F 32.8 3.7 H 0.8 (T.P.) I 3.3 L M 20.0 25.4±0.15 M1 M2 3.8 MAX. N 3.4 22.0 R2.0 R S 4.0±0.10 φ 1.8 T 1.0±0.1 U1 U2 3.2 MIN. 4.0 MIN. V 0.25 MAX. W 0.6±0.05 X 2.55 MIN. Y 2.0 MIN. E0028N11 Q 13 MC-45V8AB642KS Edition / Date Page This edition Description Previous edition Type of − − Location edition NEC Corporation (M15239E) 1st edition / − − Dec.2000 Elpida Memory, Inc. (E0028N) 1st edition / Jan. 2001 − − − Republished by Elpida Memory, Inc. 14 E0028N11 MC-45V8AB642KS NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. E0028N11 15 MC-45V8AB642KS The names of the companies, products, and logos described herein are the trademarks or registered trademarks of each company. CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. • The information in this document is current as of April, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. • Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above). M8E 00. 4