NEC UPC1853

DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC1853
MATRIX SURROUND IC WITH I2C BUS
The µPC1853 is a phase shift matrix surround IC. Only 2 speakers on the front side implement wide sound
expansion, and by adding rear speakers, rich three-dimensional sound can obtained.
The µPC1853 can perform all controls (mode switching, volume control and so on) through the I2C bus.
FEATURES
• Any control is possible through the I2C bus.
• Surround effect can be realized by only 2 speakers on the front side.
• On-chip tone (bass and treble) control circuit.
• Level-adjustable output pin for heavy bass sound.
• Level-adjustable output pin for AV amplifier.
• µPC1853-01 :
On-chip low boost circuit.
• µPC1853-02 :
On-chip L-channel volume and R-channel volume control circuits.
On-chip volume and balance control circuits.
APPLICATION
• TV, audio
ORDERING INFORMATION
Part Number
Package
µPC1853CT-01
30-pin plastic shrink DIP (400 mil)
µPC1853CT-02
"
The information in this document is subject to change without notice.
Document No. S10552EJ2V0DS00 (2nd edition)
(Previous No. ID-3126)
Date Published October 1995 P
Printed in Japan
©
1995
µPC1853
SYSTEM BLOCK DIAGRAM
• TV
Tuner
Color, intensity
and deflecting
Signal processor
PIF & SIF
RGB
output
CRT
Vertical
output
µPC1852
µPC1853
µPC1310
µPC1316C
Surround
processor
Power amplifier
L
US MTS
processor
R
µPD17002
µPD17052
µPD17053
Digital
tuning
controller
µPC2800A Remote control
reception
µPC2801A
amplifier
PIN photo diode
2
SDA
SCL
680 pF
0.082 µF
MFO
29
2200 pF 0.022 µF
1000 pF
12 V
–
0.022 µF
0.1 µF
FC1FC2 FC3 FC4 VCC
MFI
LF1
30
28
2 3 4 5
15
22 µF
0.1 µF
OFC +
25
LF2
6
6800 pF
LTC
LBC
10
9
Volume, balance
control/Mute
Tone control/
Low boost
–
Lin
+
Volume control
/Mute
26
22 µF
14 L1 OUT
17 L2 OUT
DA
18
LPF
–
+
PS1PS2PS3 PS4
–
+
Effect
control
LPF
Offset
absorption
DA
Volume
Matrix
Phase shifter
–
19
Rin
+
BAL-C
+
DA
–
3.3 µF
DA
Balance
DA
VOL-C
+
Bass
1
2 VCC
BLOCK DIAGRAM
(1) µPC1853-01
820 kΩ
–
3.3 µF
Treble
DA
27
22 µF
Volume control
/Mute
Tone control/
Low boost
1
2 VCC
Volume, balance
control/Mute
Volume control
/Mute
I2C bus interface
L + R volume
control/Mute
16 R2 OUT
13
R1 OUT
11 Rear OUT
DA
DA
3
24
1
2 VCC+
22 µF
–
22 21 20 23
ADS SDA SCL GND
1
GND
8
RBC
0.1 µF
7
RTC
6800 pF
µPC1853
12 L+R OUT
(2) µPC1853-02
4
820 kΩ
680 pF
0.082 µF
MFO
29
2200 pF 0.022 µF
1000 pF
12 V
–
0.022 µF
0.1 µF
FC1 FC2FC3 FC4 VCC
MFI
LF1
30
28
2 3 4 5
15
22 µF
0.1 µF
OFC +
25
LF2
6
6800 pF
LTC
LBC
10
9
Volume control
/Mute
Tone control
–
Lin
+
Volume control
/Mute
26
22 µF
14 L1 OUT
17 L2 OUT
DA
18
LPF
–
+
PS1PS2PS3 PS4
–
+
Effect
control
LPF
Offset
absorption
+
Bass
1
2 VCC
DA
–
Rin
+
3.3 µF
DA
Matrix
Phase shifter
19
DA
RVC
+
DA
–
LVC
–
3.3 µF
Treble
DA
27
22 µF
Volume control
/Mute
Tone control
1
2 VCC
Volume control
/Mute
Volume control
/Mute
I2C bus interface
L + R volume
control/Mute
16 R2 OUT
13
R1 OUT
11 Rear OUT
DA
DA
12 L+R OUT
22 21 20 23
ADS SDA SCL GND
1
GND
8
RBC
0.1 µF
7
RTC
6800 pF
µPC1853
24
1
2 VCC+
22 µF
–
µPC1853
PIN CONFIGURATION (Top View)
(1) µPC1853-01
1
GND
MFI
30
Monaural filter input
Phase shift filter 1
2
FC1
MFO
29
Monaural filter output
Phase shift filter 2
3
FC2
LF1
28
Low-pass filter 1
Phase shift filter 3
4
FC3
Rin
27
R-channel signal input
Phase shift filter 4
5
FC4
Lin
26
L-channel signal input
Low-pass filter 2
6
LF2
OFC
25
Offset absorption capacitor
R-channel treble capacitor
7
RTC
1 VCC
2
24
Reference voltage filter
R-channel bass capacitor
8
RBC
GND
23
Ground (for I2C bus)
L-channel treble capacitor
9
LTC
ADS
22
Slave address select
L-channel bass capacitor
10
LBC
SDA
21
Serial data (for I2C bus)
Rear output
11
Rear OUT
SCL
20
Serial clock (for I2C bus)
L+R signal output
12
L+R OUT
BAL-C
19
Balance offset absorption capacitor
R-channel signal output 1
13
R1 OUT
VOL-C
18
Volume offset absorption capacitor
L-channel signal output 1
14
L1 OUT
L2 OUT
17
L-channel signal output 2
Power supply
15
VCC
R2 OUT
16
R-channel signal output 2
µPC1853CT –01
Ground (for Analog)
5
µPC1853
(2) µPC1853-02
1
GND
MFI
30
Monaural filter input
Phase shift filter 1
2
FC1
MFO
29
Monaural filter output
Phase shift filter 2
3
FC2
LF1
28
Low-pass filter 1
Phase shift filter 3
4
FC3
Rin
27
R-channel signal input
Phase shift filter 4
5
FC4
Lin
26
L-channel signal input
Low-pass filter 2
6
LF2
OFC
25
Offset absorption capacitor
R-channel treble capacitor
7
RTC
1 VCC
2
24
Reference voltage filter
R-channel bass capacitor
8
RBC
GND
23
Ground (for I2C bus)
L-channel treble capacitor
9
LTC
ADS
22
Slave address select
L-channel bass capacitor
10
LBC
SDA
21
Serial data (for I2C bus)
Rear output
11
Rear OUT
SCL
20
Serial clock (for I2C bus)
L+R signal output
12
L+R OUT
RVC
19
R-channel volume offset absorption capacitor
R-channel signal output 1
13
R1 OUT
LVC
18
L-channel volume offset absorption capacitor
L-channel signal output 1
14
L1 OUT
L2 OUT
17
L-channel signal output 2
Power supply
15
VCC
R2 OUT
16
R-channel signal output 2
µPC1853CT –02
6
Ground (for Analog)
µPC1853
CONTENTS
1. EXPLANATION OF PINS ................................................................................................................
8
2. ATTENTIONS .................................................................................................................................... 16
3. I2C BUS INTERFACE ...................................................................................................................... 17
3.1 Data Transfer .............................................................................................................................................
17
3.1.1
Start condition ..............................................................................................................................
17
3.1.2
Stop condition ...............................................................................................................................
18
3.1.3
Data transfer ..................................................................................................................................
18
3.2 Data Transfer Format ...............................................................................................................................
18
3.2.1
1 byte data transfer .......................................................................................................................
19
3.2.2
Serial data transfer .......................................................................................................................
20
3.2.3
Acknowledge .................................................................................................................................
20
4. EXPLANATION OF EACH COMMAND ......................................................................................... 21
4.1 Subaddress List ........................................................................................................................................
21
4.2 Initialization ...............................................................................................................................................
23
4.3 Surround Function ...................................................................................................................................
24
4.4 Explanation of Each Command ...............................................................................................................
25
4.4.1
µPC1853-01 ...................................................................................................................................
25
4.4.2
µPC1853-02 ...................................................................................................................................
32
5. ELECTRICAL CHARACTERISTICS ............................................................................................... 35
6. CHARACTERISTIC CURVES .......................................................................................................... 63
6.1 Frequency Response Characteristics in Each Mode ............................................................................
63
6.2 Characteristics of Phase Shifter and Rear Output ................................................................................
66
6.3 Control Characteristics ............................................................................................................................
68
6.4 Input/Output Characteristics, Distortion Rate .......................................................................................
73
7. MEASURING CIRCUIT .................................................................................................................... 74
8. PACKAGE DIMENSIONS ................................................................................................................ 75
7
µPC1853
1. EXPLANATION OF PINS
Table 1-1 Explanation of Pins (1/8)
Pin Number
1
Pin Name
Equivalent Circuit
GND
Description
Ground for analog signal.
Pin voltage: approx. 0.0 V
15
1
23
2
FC1
Capacitor connection pin which
determines time constant of phase
shifter.
Pin voltage: approx. 6.0 V
VCC
36 kΩ
36 kΩ
18 kΩ
VCC
2
0.1 µF
3
FC2
VCC
36 kΩ
36 kΩ
18 kΩ
VCC
3
2200 pF
4
FC3
VCC
36 kΩ
36 kΩ
18 kΩ
VCC
4
0.022 µF
8
µPC1853
Table 1-1 Explanation of Pins (2/8)
Pin Number
5
Pin Name
FC4
Equivalent Circuit
Description
Capacitor connection pin which
determines time constant of phase
shifter.
Pin voltage: approx. 6.0 V
VCC
36 kΩ
36 kΩ
18 kΩ
VCC
5
0.022 µF
6
LF2
VCC
Low-pass filter.
Pin voltage: approx. 6.0 V
17.7 kΩ
17.7 kΩ
VCC
6
1000 pF
7
RTC
Capacitor connection pin for treble
boost/cut frequency characteristic of
R-channel signal.
Pin voltage: approx. 6.0 V
VCC
7.5 kΩ
5.8 kΩ
VCC
3 kΩ
7
6800 pF
8
RBC
Capacitor connection pin for bass
boost/cut frequency characteristic of Rchannel signal.
Pin voltage: approx. 6.0 V
VCC
6.5 kΩ
VCC
3 kΩ
8
0.1 µF
9
µPC1853
Table 1-1 Explanation of Pins (3/8)
Pin Number
9
Pin Name
LTC
Equivalent Circuit
Description
Capacitor connection pin for treble
boost/cut frequency characteristic of
L-channel signal.
Pin voltage: approx. 6.0 V
VCC
7.5 kΩ
5.8 kΩ
VCC
3 kΩ
9
6800 pF
10
LBC
Capacitor connection pin for bass
boost/cut frequency characteristic of
L-channel signal.
Pin voltage: approx. 6.0 V
VCC
6.5 kΩ
VCC
3 kΩ
10
0.1 µF
11
VCC
Rear OUT
VCC
500 Ω
4 kΩ
VCC
4 kΩ
15 kΩ
L-R signal output pin. Select the
output signal (φ(L-R) signal or (L-R)
signal) (see 4.4.1(4) or 4.4.2(2) Rear
output selection).
• φ(L-R): Phase-shifted.
• (L-R) : Not phase-shifted.
Pin voltage: approx. 6.0 V
11
4 kΩ
4 kΩ
12
L+R OUT
VCC
500 Ω
4 kΩ
VCC
4 kΩ
15 kΩ
12
4 kΩ
4 kΩ
10
L+R signal output pin.
Pin voltage: approx. 6.0 V
VCC
µPC1853
Table 1-1 Explanation of Pins (4/8)
Pin Number
13
Pin Name
Equivalent Circuit
Description
VCC
R1 OUT
VCC
500 Ω
4 kΩ
R-channel signal output pin (for main
output).
Pin voltage: approx. 6.0 V
4 kΩ
VCC
15 kΩ
13
4 kΩ
4 kΩ
14
L1 OUT
VCC
VCC
500 Ω
4 kΩ
VCC
L-channel signal output pin (for main
output).
Pin voltage: approx. 6.0 V
4 kΩ
15 kΩ
14
4 kΩ
4 kΩ
15
VCC
Supply voltage.
Pin voltage: approx. 12.0 V
15
1
16
VCC
R2 OUT
VCC
R-channel signal output pin for
500 Ω
4 kΩ
VCC
external audio processor and so on.
Pin voltage: approx. 6.0 V
4 kΩ
15 kΩ
16
4 kΩ
4 kΩ
11
µPC1853
Table 1-1 Explanation of Pins (5/8)
Pin Number
17
Pin Name
Equivalent Circuit
L2 OUT
Description
VCC
VCC
500 Ω
4 kΩ
VCC
L-channel signal output pin for external
audio processor and so on.
Pin voltage: approx. 6.0 V
4 kΩ
15 kΩ
17
4 kΩ
4 kΩ
18
VOL-C
(µPC1853-01)
VCC
4 kΩ
VCC
Capacitor connection pin which
absorbs shock noise of D/A converter
for volume control.
Pin voltage: approx. 6.0 V
500 Ω
LVC
(µPC1853-02)
3.3 µF
+ 18
4 kΩ
19
BAL-C
(µPC1853-01)
VCC
4 kΩ
VCC
Capacitor connection pin which
absorbs shock noise of D/A converter
for L-channel volume control.
Pin voltage: approx. 6.0 V
Capacitor connection pin which
absorbs shock noise of D/A converter
for balance control.
Pin voltage: approx. 4.8 V
15 kΩ
RVC
(µPC1853-02)
3.3 µF
+ 19
500 Ω
4 kΩ
20
SCL
20
12
4 kΩ
Capacitor connection pin which
absorbs shock noise of D/A converter
for R-channel volume control.
Pin voltage: approx. 4.8 V
Serial clock line pin (clock input for I2C
bus).
Pin voltage: approx. 0.0 V
µPC1853
Table 1-1 Explanation of Pins (6/8)
Pin Number
21
Pin Name
Equivalent Circuit
Description
Serial data line pin (data input for I2C
bus).
Pin voltage: approx. 0.0 V
SDA
VCC
4 kΩ
VCC
1 kΩ
1 kΩ
25
kΩ
125 kΩ
21
150 Ω
22
ADS
Slave address selection pin.
Pin voltage: approx. 0.0 V
4 kΩ
22
23
DGND
Ground for I2C bus signal.
Pin voltage: approx. 0.0 V
1
23
24
1
VCC
2
VCC
VCC
VCC
5 kΩ
10 kΩ
Filter pin for middle point of supply
voltage.
Pin voltage: approx. 6.0 V
VCC
20 kΩ
22 µF
+
24
20 kΩ 10 kΩ
5 kΩ
13
µPC1853
Table 1-1 Explanation of Pins (7/8)
Pin Number
25
Pin Name
OFC
Equivalent Circuit
Description
Capacitor connection pin which
absorbs offset voltage generated by
phase shifter.
Pin voltage: approx. 6.0 V
VCC
10 kΩ
10 kΩ
VCC
25
+
26
Lin
22 µF
VCC
60 kΩ
L-channel signal input pin.
Input impedance: 60 kΩ
Pin voltage: approx. 6.0 V
26
22 µF
+
L-channel
signal input
27
Rin
VCC
60 kΩ
R-channel signal input pin.
Input impedance: 60 kΩ
Pin voltage: approx. 6.0 V
27
22 µF
+
R-channel
signal input
28
LF1
1 kΩ 18 kΩ
VCC
28
680 pF
14
Low-pass filter.
Pin voltage: approx. 6.0 V
µPC1853
Table 1-1 Explanation of Pins (8/8)
Pin Number
29
Pin Name
Equivalent Circuit
MFO
Description
High-pass filter output pin for surround
1 kΩ
18 kΩ
function (Simulated mode)
(see 4.3 Surround Function).
Pin voltage: approx. 6.0 V
15 kΩ
High-pass filter input pin for surround
function (Simulated mode)
(see 4.3 Surround Function).
Pin voltage: approx. 6.0 V
VCC
29
30
MFI
820 kΩ
0.082 µF VCC
30
47 kΩ
15
µPC1853
2. ATTENTIONS
<1> Attention on Pop Noise Reduction
When changing the surround mode and switching power, use the mute function (approx. 200 ms) for pop noise
reduction (see 4.4.1(2) Mute for the µPC1853-01 or 4.4.2(1) Mute for the µPC1853-02).
<2> Attention on Supply Voltage
Drive data on the I2C bus after supply voltage of total application system becomes stable.
16
µPC1853
3. I2C BUS INTERFACE
The µPC1853 has serial bus function. This serial bus (I2C bus) is a double wired bus developed by Philips. It is
composed of 2 wires: serial clock line (SCL) and serial data line (SDA).
The µPC1853 has built-in I2C bus interface circuit, 9 rewritable registers (8 bits).
SCL (Serial Clock Line)
The master CPU outputs serial clock to synchronize with the data. According to this clock, the µPC1853 takes
in the serial data.
Input level is compatible with CMOS.
Clock frequency is 0 to 100 kHz.
SDA (Serial Data Line)
The master CPU outputs the data which is synchronized with serial clock. The µPC1853 takes in this data according
to the clock.
Input level is compatible with CMOS.
Fig. 3-1 Internal Equivalent Circuits of Interface Pin
RP
RP
SCL
SDA
µPC1853
3.1 Data Transfer
3.1.1 Start condition
Start condition is made by falling of SDA from “High” to “Low” during SCL is “High” as shown in Fig. 3-2.
When this start condition is received, the µPC1853 takes in the data synchronizing with the clock after that.
17
µPC1853
3.1.2 Stop condition
Stop condition is made by rising of SDA from “Low” to “High” during SCL is “High” as shown in Fig. 3-2.
When this stop condition is received, the µPC1853 stops to take in or output the data.
Fig. 3-2 Start/Stop Condition of Data Transfer
3.5 V
SDA
1.5 V
4.0 µs
MIN.
4.7 µs
MIN.
3.5 V
SCL
1.5 V
START
STOP
3.1.3 Data transfer
In the case of data transfer, data changing should be executed while SCL is “Low” like Fig. 3-3. When SCL is “High”,
be sure not to change the data.
Fig. 3-3 Data Transfer
SDA
Note 1
Note 2
SCL
Note 1. Data hold time for I2C device: 300 ns MIN., Data hold time for CPU: 5 µs MIN.
2. Data set-up time: 250 ns MIN.
Remark Clock frequency: 0 to 100 kHz
3.2 Data Transfer Format
Fig. 3-4 is an example of data transfer in write mode.
18
µPC1853
Fig. 3-4 Example of Data Transfer in Write Mode
Slave address
Subaddress
Data
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0 W
ACK
SDA
D7 D6 D5 D4 D3 D2 D1 D0
ACK
ACK
SCL
Remark W: Write mode, ACK: Acknowledge bit
Data is composed of 8 bits. Acknowledge bit is always added after this 8 bits data. Data should be transferred
from MSB first.
The 1 byte immediately after start condition specifies the slave address (chip address). This slave address is
composed of 7 bits.
Table 3-1 is the slave address of the µPC1853. This slave address is registered by Phillips.
Table 3-1 Slave Address of µPC1853
Slave address
Bias Voltage of ADS (Pin 22)
D6
D5
D4
D3
D2
D1
D0
5V
1
0
0
0
1
1
0
GND
1
0
0
0
1
0
0
User can set bit D1 freely.
0: Bias voltage of ADS (pin 22) is GND.
1: Bias voltage of ADS (pin 22) is 5 V.
The remaining 1 bit is the read/write bit which specifies the direction of the data transferred after that. Set “0”
because the µPC1853 has write mode only.
The byte following the slave address is subaddress byte of the µPC1853.
The µPC1853 has 9 subaddresses from SA0 to SA8, and each of them is composed of 8 bits. The data to be set
to the subaddress follows this subaddress byte.
The µPC1853 has automatic increment function. This function increments subaddress automatically in write mode.
By using automatic increment function, once slave address and subaddress are set, data can be transferred
continuously to the next subaddress. Use this function for initializing and so on. In the case of changing the data
continuously of one subaddress (adjustment and so on), set the automatic increment function OFF (see 4.4.1(8)
Automatic increment function).
3.2.1 1 byte data transfer
The following is the format in the case of transferring 1 byte data.
S
T
A
SLAVE
ADDRESS
A
W C
K
SUB
ADDRESS
A
C
K
DATA
A
C
K
S
T
P
Remark STA: Start, W: Write mode, ACK: Acknowledge bit, STP: Stop
19
µPC1853
3.2.2 Serial data transfer
The following is the format in the case of transferring 8 bytes data at one time by using automatic increment function
(the data of subaddress 01H to 08H, bit D6 is “1”).
S
T
A
SLAVE
ADDRESS
A
W C
K
SUB
ADDRESS
A
C
K
DATA1
A
C
K
DATA2
A
C
K
DATA9
A
C
K
S
T
P
Remark STA: Start, W: Write mode, ACK: Acknowledge, STP: Stop
The master CPU transfers “00H” as subaddress SA0 after start and slave address like above figure. It transfers
the data of SA0 after subaddress, and then transfers the data of SA1, SA2..., SA8 continuously without transferring
stop condition. Finally, it transfers stop condition and terminates.
The increments of the subaddress of the µPC1853 stops automatically when the subaddress comes to “08H” inside
of it.
3.2.3 Acknowledge
On I2C bus, acknowledge bit is added to the 9th bit after the data in order to judge whether data transfer has been
succeeded or not. The master CPU judges it from “High” and “Low” of acknowledge condition.
When this acknowledge period is “Low”, it means success. And when the condition is “High”, it means failure of
transfer or forced release of bus as NAK state.
The condition of being NAK state is when wrong slave address is transferred to slave IC or data transfer from slave
side is finished in read state.
20
00H
01H
02H
MSB
D7
Rear output
selection
0: φ(L-R)
1: L-R
0
0
D6
D5
D4
D3
Low boost gain
0: 6 dB
Rear output
mute
L+R signal
output mute
Audio output
mute
Main output
mute
Audio output
control link
1: ON
1: 3 dB
0: OFF
1: ON
0: OFF
1: ON
0: OFF
1: ON
0: OFF
1: ON
0: OFF
1: ON
Automatic increment
0: OFF
Attenuation volume
1: ON
Data
Automatic increment
04H
0
Main output volume control
:
Flat
to
Low
:
111111 to 000000
Balance control
L-channel attenuation volume :
R-channel attenuation volume :
Data
0
:
Low
Flat
to
to
Flat
Flat
Gain
Data
Bass control
: Boost
to
0 dB to
Cut
: 111111 to 100000 to 000000
Automatic increment
0: OFF
1: ON
Gain
Data
Treble control
: Boost
to
0 dB to
Cut
: 111111 to 100000 to 000000
Automatic increment
0: OFF
1: ON
L+R signal output volume control
Attenuation volume
:
Flat
to
Low
Data
: 111111 to 000000
06H
0
Automatic increment
0: OFF
1: ON
Attenuation volume
Data
Audio output volume control
:
Flat
to
Low
: 111111 to 000000
Automatic increment
0: OFF
Attenuation volume
Rear output volume control
:
Flat
to
Low
1: ON
Data
Surround
Automatic increment
Units of phase
Monaural/Stereo
ON/OFF
0: OFF
1: ON
0: OFF
1: ON
shifters
0: 4 units
1: 1 unit
selection
0: Stereo
1: Monaural
21
Caution Be sure to write data “0” in the subaddress 01H to 07H, bit D7.
:
111111 to 000000
Effect control
Effect :
Data :
Large to Normal to Small
1111 to 1000
to 0000
µPC1853
08H
Flat
Low
Automatic increment
0: OFF
1: ON
0
0
to
to
111111 to 100000 to 000000
05H
07H
LSB
D0
D1
Low boost
0: OFF
0: OFF
1: ON
03H
D2
4. EXPLANATION OF EACH COMMAND
Bit
Subaddress
4.1 Subaddress List
(1) µPC1853-01
22
(2) µPC1853-02
Bit
Subaddress
00H
MSB
D7
Rear output
selection
0: φ(L-R)
D6
D5
0
0
1: L-R
01H
0
D4
D3
D2
Rear output
mute
L+R signal
output mute
Audio output
mute
0: OFF
1: ON
0: OFF
1: ON
0: OFF
1: ON
D1
LSB
D0
0
0
Automatic increment
0: OFF
R-channel signal output (R1 OUT pin) volume control
Attenuation volume
:
Flat
to
Low
1: ON
Data
:
111111 to 000000
02H
0
Automatic increment
0: OFF
1: ON
L-channel signal output (L1 OUT pin) volume control
Attenuation volume
:
Flat
to
Low
Data
: 111111 to 000000
03H
0
Automatic increment
0: OFF
1: ON
Gain
Data
Bass control
: Boost
to
0 dB to
Cut
: 111111 to 100000 to 000000
Automatic increment
0: OFF
1: ON
Gain
Data
Treble control
: Boost
to
0 dB to
Cut
: 111111 to 100000 to 000000
04H
0
05H
0
Automatic increment
0: OFF
1: ON
L+R signal output volume control
Attenuation volume
:
Flat
to
Low
Data
: 111111 to 000000
06H
0
Automatic increment
0: OFF
1: ON
Attenuation volume
Data
Audio output volume control
:
Flat
to
Low
: 111111 to 000000
Automatic increment
0: OFF
1: ON
Attenuation volume
Data
Rear output volume control
:
Flat
to
Low
: 111111 to 000000
07H
08H
0
Automatic increment
Units of phase
Monaural/Stereo
ON/OFF
0: OFF
1: ON
0: OFF
1: ON
shifters
0: 4 units
1: 1 unit
selection
0: Stereo
1: Monaural
Effect :
Data :
Effect control
Large to Normal to Small
1111 to 1000
to 0000
Caution Be sure to fix data of the subaddress 00H, bit D6, D5, D1, D0 and subaddress 01H to 07H, bit D7 to “0”.
µPC1853
Surround
µPC1853
4.2 Initialization
After power-on, be sure to initialize the subaddress data to table below.
Table 4-1 Initial Data of µPC1853-01
Bit
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
00H
1
0
0
0
0
0
0
0
01H
0
1
1
1
1
1
1
1
02H
0
1
1
0
0
0
0
0
03H
0
1
1
0
0
0
0
0
04H
0
1
1
0
0
0
0
0
05H
0
1
1
1
1
1
1
1
06H
0
1
1
1
1
1
1
1
07H
0
1
1
1
1
1
1
1
08H
0
1
0
0
1
0
0
0
Subaddress
Table 4-2 Initial Data of µPC1853-02
Bit
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
00H
1
0
0
0
0
0
0
0
01H
0
1
1
1
1
1
1
1
02H
0
1
1
1
1
1
1
1
03H
0
1
1
0
0
0
0
0
04H
0
1
1
0
0
0
0
0
05H
0
1
1
1
1
1
1
1
06H
0
1
1
1
1
1
1
1
07H
0
1
1
1
1
1
1
1
08H
0
1
0
0
1
0
0
0
Subaddress
Caution Until initializing completely, mute by the external units.
23
µPC1853
4.3 Surround Function
About the setting of surround mode, see table below.
Table 4-3 Setting of Surround Mode
Setting
Surround
mode
Subaddress: 08H
Description
D7
D5
D4
Surround
ON/OFF
Units of
phase shifter
Monaural/Stereo
selection
OFF
0
–
–
OFF
–
–
Movie
1
0
0
Music
1
1
0
Simulated
1
0
1
4 units
ON
Stereo
1 unit
4 units
Monaural
–: Don’t care.
Caution When changing the surround mode, use the mute function (approx. 200 ms) for pop noise
reduction (see 4.4.1(2) Mute for the µPC1853-01 or 4.4.2(1) Mute for the µPC1853-02).
24
µPC1853
4.4 Explanation of Each Command
4.4.1 µPC1853-01
(1) Audio Output Control Link
By the data of subaddress 00H, bit D0, audio output volume link can be controlled (linked with main output control
or not).
Fig. 4-1 Audio Output Control Link
Subaddress
00H
D7
D6
D5
D4
Rear
output
selection
Low
boost
Low
boost
gain
Rear
output
mute
D3
L+R
signal
output
mute
D2
Audio
output
mute
D1
Main
output
mute
D0
Audio
output
control
link
Audio output
control link
Audio output control link
0
Audio output volume controlled independently.
Main output volume control (Subaddress: 01H, Bit: D5 to D0)
Audio output volume control (Subaddress: 06H, Bit: D5 to D0)
1
Audio output volume control can be linked with main output volume control.
Main output volume and audio output volume control (Subaddress: 01H, Bit: D5 to D0)
(2) Mute
By the data of subaddress 00H, bit D1 to D4, ON/OFF of mute function can be controlled.
25
µPC1853
Fig. 4-2 Mute (µPC1853-01)
Subaddress
00H
D7
D6
D5
D4
Rear
output
selection
Low
boost
Low
boost
gain
Rear
output
mute
D3
D2
L+R
signal
output
mute
Audio
output
mute
D1
Main
output
mute
D0
Audio
output
control
link
Main output mute
0
Main output not muted
1
Main output muted
Audio output mute
0
Audio output not muted
1
Audio output muted
L+R signal output mute
0
L+R output not muted
1
L+R output muted
Rear output mute
0
Rear output not muted
1
Rear output muted
Caution Use the mute function (approx. 200 ms) for pop noise reduction when changing the surround
mode and switching power.
(3) Low boost function
By the data of subaddress 00H, bit D5, the low boost gain can be selected (3 dB or 6 dB). And, by the data of
subaddress 00H, bit D6 ON/OFF of the low boost can be controlled.
Fig. 4-3 Low Boost Function
Subaddress
00H
D7
D6
D5
D4
D3
Rear
output
selection
Low
boost
Low
boost
gain
Rear
output
mute
L+R
signal
output
mute
D2
Audio
output
mute
Low boost gain
0
Low boost gain: 6 dB
1
Low boost gain: 3 dB
Low boost ON/OFF
26
0
Low boost: OFF
1
Low boost: ON
D1
Main
output
mute
D0
Audio
output
control
link
µPC1853
(4) Rear output selection
By the data of subaddress 00H, bit D7, output signal of the rear output pin can be selected (φ (L-R) signal or
(L-R) signal).
Fig. 4-4 Rear Output Selection (µPC1853-01)
Subaddress
00H
D7
D6
D5
D4
Rear
output
selection
Low
boost
Low
boost
gain
Rear
output
mute
D3
D2
L+R
signal
output
mute
D1
Main
output
mute
Audio
output
mute
D0
Audio
output
control
link
Rear output selection
0
φ (L-R) signal: Phase-shifted
1
(L-R) signal: Not phase-shifted
(5) Volume control
By the data of subaddress 01H, 05H, 06H and 07H, bit D5 to D0, the volume control can be adjusted in 64 levels.
Fig. 4-5 Volume Control (µPC1853-01) (1/2)
• Main output volume control
Subaddress
01H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Main output volume control
Main output volume control
Data
Attenuation volume
D5 ··· D0
111111
Flat
000000
Low
• L+R signal output volume control
Subaddress
05H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
L+R signal output volume control
L+R signal output volume control
Data
D5 ··· D0
Attenuation volume
111111
Flat
000000
Low
27
µPC1853
Fig. 4-5 Volume Control (µPC1853-01) (2/2)
• Audio output volume controlNote
Subaddress
06H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Audio output volume control
Audio output volume control
Data
Attenuation volume
D5 ··· D0
111111
Flat
000000
Low
Note When selecting the mode linking main output volume control to audio output volume control, the audio
output volume can be controlled by the data of main output volume control (see (1) Audio Output
Control Link). In that case, fix the audio output volume control data to “111111”.
• Rear output volume control
Subaddress
07H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Rear output volume control
Rear output volume control
Data
D5 ··· D0
Attenuation volume
111111
Flat
000000
Low
(6) Balance control
By the data of subaddress 02H, bit D5 to D0, the balance level of L1 OUT and R1 OUT pin can be adjusted in
64 levels.
Fig. 4-6 Balance Control
Subaddress
02H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Balance control
Balance control
L-channel
Data
attenuation
D5 ··· D0 volume
28
R-channel
attenuation
volume
111111
Low
Flat
100000
Flat
Flat
000000
Flat
Low
µPC1853
(7) Bass and treble control
By the data of subaddress 03H and 04H, bit D5 to D0, the bass and treble tone for main output (L1 OUT and R1
OUT pin) can be adjusted in 64 levels.
Fig. 4-7 Bass and Treble Control
• Bass control
Subaddress
03H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Bass control
Bass control
Data
D5 ··· D0
Gain
111111
Boost
100000
0 dB
000000
Cut
• Treble control
Subaddress
04H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Treble control
Treble control
Data
Gain
D5 ··· D0
111111
Boost
100000
0 dB
000000
Cut
(8) Automatic increment function
By the data of subaddress 01H to 08H, bit D6, ON/OFF of the automatic increment function can be controlled.
Fig. 4-8 Automatic Increment Function
Subaddress
01H to 08H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Main output volume control
Automatic increment function
0
Automatic increment function: OFF
1
Automatic increment function: ON
29
µPC1853
Caution After power-on, be sure to initialize the subaddress data (see 4.2 Initialization).
The automatic increment function increments subaddress automatically.
Automatic increment function is ON : Subaddress is incremented automatically.
If once slave address and subaddress are set, without setting the next
subaddress, data of the next subaddress can be transferred.
Automatic increment function is OFF: Subaddress is fixed.
Data of the fixed subaddress can be set repeatedly.
The automatic increment ON/OFF bit is in the subaddress 01H to 08H. The increment of subaddress is controlled
individually by each automatic increment ON/OFF bit. As for 00H, subaddress is not incremented automatically (see
4.1 Subaddress List).
For example, when the automatic increment function of subaddress 01H is ON and that of 02H is OFF, subaddress
is incremented from 01H to 02H automatically and is fixed on 02H.
In case of the automatic increment function of 08H is ON, subaddress is not incremented. If next data is transferred
after setting data of 08H (acknowledge bit: L), the acknowledge condition is changed into NAK state (acknowledge
bit: H). And the data transfer from the master CPU is stopped.
(9) Effect control
By the data of subaddress 08H, bit D3 to D0, the level of indirect sound signal (surround signal) added to the
original signal can be adjusted in 16 levels.
Fig. 4-9 Effect Control
Subaddress
08H
D7
D6
D5
D4
Surround
ON/OFF
Automatic
increment
Units of
phase
shifters
Monaural/
stereo
selection
D3
D2
D1
D0
Effect control
Effect control
Data
D3 ··· D0
Effect
1111
Large
1000
Normal
0000
Small
(10) Monaural/Stereo selection
By the data of subaddress 08H, bit D4, the surround mode can be selected (stereo mode or simulated mode).
Stereo mode
:
Surround signal processing for stereo source.
The phase of the difference between L-channel and R-channel signals is shifted and
added to the original signal.
Simulated mode :
Stereo sound simulation for monaural source.
The phase of the difference between the signal through HPF and the signal through LPF
is shifted, and the signals are added to the original signal. When the output frequency
characteristics of L-channel and R-channel signals become the form of comb, stereo
sound simulation can be realized.
30
µPC1853
Fig. 4-10 Monaural/Stereo Selection
Subaddress
D7
08H
Surround
ON/OFF
D6
D5
Automatic
increment
Units of
phase
shifters
D4
D3
Monaural/
stereo
selection
D2
D1
D0
Effect control
Monaural/stereo selection
0
Stereo mode
1
Simulated mode
(11) Units of phase shifters
By the data of subaddress 08H, bit D5, the number of phase shifter’s units (1 or 4 units) can be selected for the
indirect sound signal (surround signal).
Fig. 4-11 Units of Phase Shifters
Subaddress
D7
08H
Surround
ON/OFF
D6
D5
Automatic
increment
Units of
phase
shifters
D4
D3
Monaural/
stereo
selection
D2
D1
D0
Effect control
Units of phase shifers
0
Phase shifter: 4 units
1
Phase shifter: 1 unit
(12) Surround ON/OFF
By the data of subaddress 08H, bit D7, ON/OFF of surround (indirect sound signal) mode can be selected.
Surround OFF:
Surround ON :
Original signal is taken out directly (OFF mode).
The signal passed through the phase shifter (indirect sound) is added to the original signal
(Movie, Music and Simulated mode).
Fig. 4-12 Surround ON/OFF
Subaddress
D7
08H
Surround
ON/OFF
D6
Automatic
increment
D5
Units of
phase
shifters
D4
Monaural/
stereo
selection
D3
D2
D1
D0
Effect control
Surround ON/OFF
0
Surround: OFF
1
Surround: ON
31
µPC1853
4.4.2 µPC1853-02
(1) Mute
By the data of subaddress 00H, bit D2 to D4, ON/OFF of mute function can be controlled.
Fig. 4-13 Mute (µPC1853-02)
Subaddress
00H
D7
D6
D5
D4
Rear
output
selection
0
0
Rear
output
mute
D3
L+R
signal
output
mute
D2
D1
D0
Audio
output
mute
0
0
Audio output mute
0
Audio output not muted
1
Audio output muted
L+R signal output mute
0
L+R output not muted
1
L+R output muted
Rear output mute
0
Rear output not muted
1
Rear output muted
Caution Use the mute function (approx. 200 ms) for pop noise reduction when changing the surround
mode and switching power.
(2) Rear output selection
By the data of subaddress 00H, bit D7, output signal of the rear output pin can be selected (φ (L-R) signal or
(L-R) signal).
Fig. 4-14 Rear Output Selection (µPC1853-02)
Subaddress
00H
D7
D6
D5
D4
Rear
output
selection
0
0
Rear
output
mute
D3
L+R
signal
output
mute
Rear output selection
32
0
φ (L-R) signal: Phase-shifted
1
(L-R) signal: Not phase-shifted
D2
D1
D0
Audio
output
mute
0
0
µPC1853
(3) Volume control
By the data of subaddress 01H, 02H, 05H, 06H and 07H, bit D5 to D0, the volume control can be adjusted in 64
levels.
Fig. 4-15 Volume Control (µPC1853-02) (1/2)
• R-channel output volume control
Subaddress
01H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
R-channel output volume control
R-channel output volume control
Data
R-channel attenuation
volume
D5 ··· D0
111111
Flat
000000
Low
• L-channel output volume control
Subaddress
02H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
L-channel output volume control
L-channel output volume control
Data
L-channel attenuation
volume
D5 ··· D0
111111
Flat
000000
Low
• L+R signal output volume control
Subaddress
05H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
L+R signal output volume control
L+R signal output volume control
Data
D5 ··· D0
Attenuation volume
111111
Flat
000000
Low
33
µPC1853
Fig. 4-15 Volume Control (µPC1853-02) (2/2)
• Audio output volume control
Subaddress
06H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Audio output volume control
Audio output volume control
Data
Attenuation volume
D5 ··· D0
111111
Flat
000000
Low
• Rear output volume control
Subaddress
07H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Rear output volume control
Rear output volume control
Data
D5 ··· D0
(4) Bass and treble control
See 4.4.1 (7) Bass and treble control.
(5) Automatic increment function
See 4.4.1 (8) Automatic increment function.
(6) Effect control
See 4.4.1 (9) Effect control.
(7) Monaural/Stereo selection
See 4.4.1 (10) Monaural/Stereo selection.
(8) Units of phase shifters
See 4.4.1 (11) Units of phase shifters.
(9) Surround ON/OFF
See 4.4.1 (12) Surround ON/OFF.
34
Attenuation volume
111111
Flat
000000
Low
µPC1853
5. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (Unless otherwise specified, TA = 25 ˚C)
Parameter
Symbol
Test conditions
No signal
Ratings
Unit
14.0
V
Supply voltage
VCC
Input signal voltage
VIN
VCC
V
I2C bus input pin voltage
Vcont
VCC + 0.2
V
Power dissipation
PD
TA = 75 ˚C
500
mW
Operating temperature
TA
VCC = 12 V
–20 to +75
˚C
Storage temperature
Tstg
–40 to +125
˚C
Recommended Operating Conditions (Unless otherwise specified, TA = 25 ˚C)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
10.8
12.0
13.2
V
Supply voltage
VCC
Input signal voltage
VIN
VCC = 12 V,
Gain of input-output: 0 dB
0.0
1.4
7.9
Vp-p
I2C bus input pin voltage (H)
VcontH
Pins SDA and SCL
3.5
5.0
6.0
V
I2C bus input pin voltage (L)
VcontL
0.0
0.0
1.5
V
35
36
Electrical Characteristics
(VCC = 12 V, TA = 25 ˚C, RH ≤ 70 %, f = 1 kHz, VIN = 0.5 Vrms, No load impedance, unless otherwise specified)
General (1/1)
Switch modeNote
Parameter
Symbol
Subaddress data
Test conditions
S1
S2
S3
00 01 02 03 04 05 06 07 08
MIN.
TYP.
MAX.
Unit
Supply current
ICC
No signal
b
b
–
80 7F 60 60 60 7F 7F 7F 48
16
24
32
mA
Maximum input voltage 1
VOM1
Lin, Rin ≥ 2.8 Vrms,
a
a
–
80 7F 60 60 60 7F 7F 7F 48
7.9
8.8
9.3
Vp-p
a
b
–
2.5
2.8
3.3
Vp-p
a
b
–
–
0.1
0.5
%
b
a
–
–
0.1
0.5
%
THD = 1 %,
L1 OUT, R1 OUT,
L2 OUT, R2 OUT,
L+R OUT
Maximum input voltage 2
VOM2
Lin ≥ 2.8 Vrms, Rin = GND,
THD = 1 %,
Rear OUT
Distortion rate (L-ch)
THDL
f = 1 kHz,
80 7F 60 60 60 7F 7F 7F 48
Lin = 0.5 Vrms,
Rin = GND,
L1 OUT, L2 OUT
Distortion rate (R-ch)
THDR
f = 1 kHz,
Lin = GND,
Rin = 0.5 Vrms,
R1 OUT, R2 OUT
–: Don’t care.
Remark The values are common to both the µPC1853CT-01 and µPC1853CT-02.
µPC1853
Note See 7. MEASURING CIRCUIT.
(1) µPC1853CT-01 Volume control, tone control block (1/3)
Switch modeNote
Symbol
Volume attenuation 1 (1)
ATTVL11
Lin = 0.5 Vrms, Rin = GND,
Volume attenuation 1 (2)
ATTVL12
L1 OUT
Volume attenuation 1 (3)
ATTVL13
Volume attenuation 2 (1)
ATTVL21
Lin = 0.5 Vrms, Rin = GND,
Volume attenuation 2 (2)
ATTVL22
L2 OUT
Volume attenuation 2 (3)
ATTVL23
L+R volume attenuation 1
ATTVLR1
Lin = 0.5 Vrms, Rin = 0.5 Vrms,
L+R volume attenuation 2
ATTVLR2
L+R OUT
L+R volume attenuation 3
ATTVLR3
Rear volume attenuation 1
ATTVRE1
Lin = 0.5 Vrms, Rin = GND,
Rear volume attenuation 2
ATTVRE2
Rear OUT
Balance attenuation (L-ch) 1 (1)
ATTBL11
Lin = 0.5 Vrms, Rin = GND,
Balance attenuation (L-ch) 1 (2)
ATTBL12
L1 OUT
Balance attenuation (L-ch) 1 (3)
ATTBL13
Balance attenuation (R-ch) 1 (1)
ATTBR11
Lin = GND, Rin = 0.5 Vrms,
Balance attenuation (R-ch) 1 (2)
ATTBR12
R1 OUT
Balance attenuation (R-ch) 1 (3)
ATTBR13
Low-band boost control
VBB
f = 100 Hz, Lin = 0.5 Vrms,
Low-band flat control
VBF
Rin = GND, L1 OUT
Low-band cut control
VBC
Low-band boost control (6 dB) 1
VB6dB1
f = 100 Hz, Lin = 0.5 Vrms,
Low-band boost control (6 dB) 2
VB6dB2
Rin = GND, L1 OUT
Low-band boost control (6 dB) 3
VB6dB3
–: Don’t care.
37
Note See 7. MEASURING CIRCUIT.
Test conditions
Subaddress data
MIN.
TYP.
MAX.
Unit
–1.5
0.0
+1.5
dB
60
–25.0
–19.0
–13.0
dB
40
–80.0
–
–
dB
–1.5
0.0
+1.5
dB
60
–25.0
–19.0
–13.0
dB
40
–80.0
–
–
dB
–1.5
0.0
+1.5
dB
60
–25.0
–19.0
–13.0
dB
40
–80.0
–
–
dB
8.5
10.0
11.5
dB
–15.0
–9.0
–3.0
dB
–1.5
0.0
+1.5
dB
60
–1.5
0.0
+1.5
dB
7F
–80.0
–
–
dB
–80.0
–
–
dB
60
–1.5
0.0
+1.5
dB
7F
–1.5
0.0
+1.5
dB
7.0
10.0
13.0
dB
60
–3.0
0.0
+3.0
dB
41
–13.0
–10.0
–7.0
dB
80 7F 60 60 60 7F 7F 7F 48
2.0
3.0
4.0
dB
↓ 60
3.0
4.0
5.0
dB
C0 50
4.0
6.0
8.0
dB
S1
S2
S3
00 01 02 03 04 05 06 07 08
a
b
–
80 7F 60 60 60 7F 7F 7F 48
a
a
a
b
a
b
–
–
–
80 7F 60 60 60 7F 7F 7F 48
80 7F 60 60 60 7F 7F 7F 48
80 7F 60 60 60 7F 7F 7F 48
60
a
b
a
a
b
a
b
b
–
–
–
–
80 7F 41 60 60 7F 7F 7F 48
80 7F 41 60 60 7F 7F 7F 48
80 7F 60 7F 60 7F 7F 7F 48
µPC1853
Parameter
38
(1) µPC1853CT-01 Volume control, tone control block (2/3)
Switch modeNote
Parameter
Symbol
Test conditions
Subaddress data
MIN.
TYP.
MAX.
Unit
0.5
1.5
2.5
dB
↓ 60
1.0
2.0
3.0
dB
E0 50
2.0
3.0
4.0
dB
80 7F 60 60 7F 7F 7F 7F 48
7.0
10.0
13.0
dB
60
–3.0
0.0
+3.0
dB
41
–13.0
–10.0
–7.0
dB
80 7F 60 60 60 7F 7F 7F 48
–1.0
0.0
+1.0
dB
–1.0
0.0
+1.0
dB
–1.0
0.0
+1.0
dB
–1.0
0.0
+1.0
dB
–1.0
0.0
+1.0
dB
S1
S2
S3
00 01 02 03 04 05 06 07 08
a
b
–
A0 7F 60 60 60 7F 7F 7F 48
Low-band boost control (3 dB) 1
VB3dB1
f = 100 Hz, Lin = 0.5 Vrms,
Low-band boost control (3 dB) 2
VB3dB2
Rin = GND, L1 OUT
Low-band boost control (3 dB) 3
VB3dB3
High-band boost control
VTB
f = 10 kHz, Lin = 0.5 Vrms,
High-band flat control
VTF
Rin = GND, L1 OUT
High-band cut control
VTC
L, R in-phase gain difference 1 (1)
DG11
Lin = GND, Rin = 0.5 Vrms,
L, R in-phase gain difference 1 (2)
DG12
L1 OUT, R1 OUT
L, R in-phase gain difference 2 (1)
DG21
Lin = GND, Rin = 0.5 Vrms,
L, R in-phase gain difference 2 (2)
DG22
L2 OUT, R2 OUT
L, R in-phase gain difference 3 (1)
DG31
f = 100 Hz, Lin = 0.5 Vrms,
L, R in-phase gain difference 3 (2)
DG32
Rin = 0.5 Vrms,
60
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 3 (3)
DG33
L1 OUT, R1 OUT
41
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 4 (1)
DG41
f = 10 kHz, Lin = 0.5 Vrms,
80 7F 60 60 7F 7F 7F 7F 48
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 4 (2)
DG42
Rin = 0.5 Vrms,
60
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 4 (3)
DG43
L1 OUT, R1 OUT
41
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 5 (1)
DG51
f = 100 Hz, Lin = 0.5 Vrms,
80 7F 60 60 60 7F 7F 7F 48
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 5 (2)
DG52
Rin = 0.5 Vrms,
↓ 60
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 5 (3)
DG53
L1 OUT, R1 OUT
C0 48
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 6 (1)
DG61
f = 100 Hz, Lin = 0.5 Vrms,
A0 7F 60 60 60 7F 7F 7F 48
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 6 (2)
DG62
Rin = 0.5 Vrms,
↓ 60
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 6 (3)
DG63
L1 OUT, R1 OUT
E0 48
–1.0
0.0
+1.0
dB
a
b
b
a
–
–
60
b
a
–
80 7F 60 60 60 7F 7F 7F 48
60
a
a
a
a
a
a
a
a
–
–
–
–
80 7F 60 7F 60 7F 7F 7F 48
–: Don’t care.
µPC1853
Note See 7. MEASURING CIRCUIT.
(1) µPC1853CT-01 Volume control, tone control block (3/3)
Switch modeNote
Parameter
Muting attenuation 1
Symbol
Test conditions
Subaddress data
MIN.
TYP.
MAX.
Unit
–80.0
–
–
dB
–80.0
–
–
dB
–80.0
–
–
dB
–80.0
–
–
dB
88
–80.0
–
–
dB
–
90
–70.0
–
–
dB
–
80 7F 60 60 60 7F 7F 7F 48
↓
82
–50
0
+50
mV
VOS2
80
↓
84
–50
0
+50
mV
VOS3
80
↓
88
–50
0
+50
mV
VOS4
80
↓
90
–50
0
+50
mV
Mute 1
Lin = 0.5 Vrms,
S1
S2
S3
00 01 02 03 04 05 06 07 08
a
b
–
82 7F 60 60 60 7F 7F 7F 48
b
a
–
a
b
–
b
a
–
a
a
–
a
b
b
b
Rin = GND, L1 OUT
Muting attenuation 2
Mute 2
Lin = GND,
Rin = 0.5 Vrms, R1 OUT
Muting attenuation 3
Mute 3
Lin = 0.5 Vrms,
84
Rin = GND, L2 OUT
Muting attenuation 4
Mute 4
Lin = GND,
Rin = 0.5 Vrms, R2 OUT
Muting attenuation 5
Mute 5
Lin = 0.5 Vrms,
Rin = 0.5 Vrms, L+R OUT
Muting attenuation 6
DC offset at muting mode
Mute 6
Lin = 0.5 Vrms,
(Rear)
Rin = GND, Rear OUT
VOS1
No signal
(L1 OUT, R1 OUT)
DC offset at muting mode
(L2 OUT, R2 OUT)
DC offset at muting mode
(L+R OUT)
DC offset at muting mode
(Rear OUT)
–: Don’t care.
39
µPC1853
Note See 7. MEASURING CIRCUIT.
40
(2) µPC1853CT-02 Volume control, tone control block (1/2)
Switch modeNote
Parameter
Symbol
Test conditions
Subaddress data
S1
S2
S3
00 01 02 03 04 05 06 07 08
a
b
–
80 7F 7F 60 60 7F 7F 7F 48
MIN.
TYP.
MAX.
Unit
–1.5
0.0
+1.5
dB
ATTVL11
Lin = 0.5 Vrms,
Volume attenuation 1 (2) L-ch
ATTVL12
Rin = GND,
60
–25.0
–19.0
–13.0
dB
Volume attenuation 1 (3) L-ch
ATTVL13
L1 OUT
40
–80.0
–
–
dB
Volume attenuation 1 (4) R-ch
ATTVR14
Lin = GND,
–1.5
0.0
+1.5
dB
Volume attenuation 1 (5) R-ch
ATTVR15
Rin = 0.5 Vrms, R1 OUT
60
–25.0
–19.0
–13.0
dB
Volume attenuation 1 (6) R-ch
ATTVR16
40
–80.0
–
–
dB
Volume attenuation 2 (1)
ATTVL21
Lin = 0.5 Vrms, Rin = GND,
–1.5
0.0
+1.5
dB
Volume attenuation 2 (2)
ATTVL22
L2 OUT
60
–25.0
–19.0
–13.0
dB
Volume attenuation 2 (3)
ATTVL23
40
–80.0
–
–
dB
L+R volume attenuation 1
ATTVLR1
Lin = 0.5 Vrms, Rin = 0.5 Vrms,
–1.5
0.0
+1.5
dB
L+R volume attenuation 2
ATTVLR2
L+R OUT
60
–25.0
–19.5
–13.0
dB
L+R volume attenuation 3
ATTVLR3
40
–80.0
–
–
dB
Rear volume attenuation 1
ATTVRE1
Lin = 0.5 Vrms, Rin = GND,
8.5
10.0
11.5
dB
Rear volume attenuation 2
ATTVRE2
Rear OUT
–15.0
–9.0
–3.0
dB
Low-band boost control
VBB
f = 100 Hz, Lin = 0.5 Vrms,
7.0
10.0
13.0
dB
Low-band flat control
VBF
Rin = GND, L1 OUT
60
–3.0
0.0
+3.0
dB
Low-band cut control
VBC
41
–13.0
–10.0
–7.0
dB
High-band boost control
VTB
f = 100 kHz, Lin = 0.5 Vrms,
80 7F 7F 60 7F 7F 7F 7F 48
7.0
10.0
13.0
dB
High-band flat control
VTF
Rin = GND, L1 OUT
60
–3.0
0.0
+3.0
dB
High-band cut control
VTC
41
–13.0
–10.0
–7.0
dB
L, R in-phase gain difference 1 (1)
DG11
Lin = GND, Rin = 0.5 Vrms,
80 7F 7F 60 60 7F 7F 7F 48
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 1 (2)
DG12
L1 OUT, R1 OUT
–1.5
0.0
+1.5
dB
L, R in-phase gain difference 2 (1)
DG21
Lin = GND, Rin = 0.5 Vrms,
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 2 (2)
DG22
L2 OUT, R2 OUT
–1.0
0.0
+1.0
dB
–: Don’t care.
Note See 7. MEASURING CIRCUIT.
a
a
a
a
b
b
a
b
–
–
–
–
80 7F 7F 60 60 7F 7F 7F 48
80 7F 7F 60 60 7F 7F 7F 48
80 7F 7F 60 60 7F 7F 7F 48
80 7F 7F 60 60 7F 7F 7F 48
60
a
a
b
b
b
a
–
–
–
80 7F 7F 7F 60 7F 7F 7F 48
60 60
b
a
–
80 7F 7F 60 60 7F 7F 7F 48
60
µPC1853
Volume attenuation 1 (1) L-ch
(2) µPC1853CT-02 Volume control, tone control block (2/2)
Switch modeNote
Parameter
Symbol
Test conditions
Subaddress data
S1
S2
S3
00 01 02 03 04 05 06 07 08
a
a
–
80 7F 7F 7F 60 7F 7F 7F 48
MIN.
TYP.
MAX.
Unit
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 3 (1)
DG31
f = 100 Hz, Lin = 0.5 Vrms,
L, R in-phase gain difference 3 (2)
DG32
Rin = 0.5 Vrms,
60
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 3 (3)
DG33
L1 OUT, R1 OUT
41
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 4 (1)
DG41
f = 10 kHz, Lin = 0.5 Vrms,
80 7F 7F 60 7F 7F 7F 7F 48
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 4 (2)
DG42
Rin = 0.5 Vrms,
60
–1.0
0.0
+1.0
dB
L, R in-phase gain difference 4 (3)
DG43
L1 OUT, R1 OUT
41
–1.0
0.0
+1.0
dB
Muting attenuation 1
Mute 1
Lin = 0.5 Vrms,
84 7F 7F 60 60 7F 7F 7F 48
–80.0
–
–
dB
–80.0
–
–
dB
a
a
–
a
b
–
b
a
–
a
a
–
88
–80.0
–
–
dB
a
b
–
90
–70.0
–
–
dB
b
b
–
80 7F 7F 60 60 7F 7F 7F 48
↓
82
–50
0
+50
mV
VOS2
80
↓
84
–50
0
+50
mV
VOS3
80
↓
88
–50
0
+50
mV
VOS4
80
↓
90
–50
0
+50
mV
Rin = GND, L2 OUT
Muting attenuation 2
Mute 2
Lin = GND,
Rin = 0.5 Vrms, R2 OUT
Muting attenuation 3
Mute 3
Lin = 0.5 Vrms,
Rin = 0.5 Vrms, L+R OUT
Muting attenuation 4
DC offset at muting mode
Mute 4
Lin = 0.5 Vrms,
(Rear)
Rin = GND, Rear OUT
VOS1
No signal
(L1 OUT, R1 OUT)
DC offset at muting mode
(L2 OUT, R2 OUT)
DC offset at muting mode
(L+R OUT)
DC offset at muting mode
–: Don’t care.
41
Note See 7. MEASURING CIRCUIT.
µPC1853
(Rear OUT)
42
Matrix surround block (1/2)
Switch modeNote1
Parameter
Symbol
In-phase gain
GMOV1
Movie mode 1 Note2
GMOV2
Movie mode 2 Note2
GMUS1
Note2
GMUS2
Note2
GSIML1
Note2
In-phase gain
GSIML2
a
b
–
80 7F 60 60 60 7F 7F 7F C8
MIN.
TYP.
MAX.
Unit
3.0
7.0
11.0
dB
f = 1 kHz, Lin = 0.5 Vrms,
0.0
4.0
8.0
dB
f = 1 kHz, Lin = 0.5 Vrms,
E8
3.5
5.5
7.5
dB
f = 1 kHz, Lin = 0.5 Vrms,
–2.5
–0.5
+1.5
dB
GSIML3
GSIMR1
a
–
D8
–0.5
+3.5
+6.5
dB
f = 1 kHz, Lin = 0.5 Vrms,
–
–3.0
+4.5
dB
f = 4 kHz, Lin = 0.5 Vrms,
2.0
6.0
10.0
dB
f = 250 Hz, Lin = 0.5 Vrms,
D8
–
–5.5
–1.0
dB
0.0
3.0
6.0
dB
–
–7.0
+5.0
dB
Rin = 0.5 Vrms, R1 OUT
GSIMR2
Simulated mode (R-ch) 2 Note2
In-phase gain
a
Rin = 0.5 Vrms, L1 OUT
Note2
In-phase gain
f = 250 Hz, Lin = 0.5 Vrms,
Rin = 0.5 Vrms, L1 OUT
Note2
In-phase gain
Simulated mode (R-ch) 1
00 01 02 03 04 05 06 07 08
Rin = 0.5 Vrms, L1 OUT
Note2
In-phase gain
Simulated mode (L-ch) 3
S3
Rin = GND, R1 OUT
In-phase gain
Simulated mode (L-ch) 2
S2
Rin = GND, L1 OUT
In-phase gain
Simulated mode (L-ch) 1
S1
Rin = GND, R1 OUT
In-phase gain
Music mode 2
f = 1 kHz, Lin = 0.5 Vrms,
Subaddress data
Rin = GND, L1 OUT
In-phase gain
Music mode 1
Test conditions
f = 1 kHz, Lin = 0.5 Vrms,
Rin = 0.5 Vrms, R1 OUT
GSIMR3
Simulated mode (R-ch) 3 Note2
f = 4 kHz, Lin = 0.5 Vrms,
Rin = 0.5 Vrms, R1 OUT
–: Don’t care.
Note 1. See 7. MEASURING CIRCUIT.
Remark The values are common to both the µPC1853CT-01 and µPC1853CT-02.
µPC1853
2. See 4.3 Surround Function about setting of surround mode.
Matrix surround block (2/2)
Switch modeNote
Parameter
Output noise
Symbol
NO1
Test conditions
Lin = GND, Rin = GND,
Subaddress data
MIN.
TYP.
MAX.
Unit
80 7F 60 60 60 7F 7F 7F 48
–
25
50
µVrms
80 7F 60 60 60 7F 7F 7F 48
–
–80
–70
dB
–
–80
–70
dB
–50
0
+50
mV
S1
S2
S3
00 01 02 03 04 05 06 07 08
b
b
–
a
b
–
b
a
–
b
b
–
Surround: OFF, DIN-AUDIO filter,
L1 OUT, R1 OUT, L2 OUT,
R2 OUT, L+R OUT, Rear OUT
Crosstalk 1
CT1
Lin = 0.5 Vrms, Rin = GND,
0 dB: 0.5 Vrms
Crosstalk 2
CT2
Lin = GND, Rin = 0.5 Vrms,
0 dB: 0.5 Vrms
Inter-mode offset
VOSM
No signal.
80 7F 60 60 60 7F 7F 7F ×F
At surround mode switching.
–: Don’t care.
Note See 7. MEASURING CIRCUIT.
Remark The values are common to both the µPC1853CT-01 and µPC1853CT-02.
µPC1853
43
44
ELECTRICAL CHARACTERISTICS MEASUREMENT LIST
Set subaddress data as shown in 4.2 Initialization unless otherwise specified.
General (1/1)
Data
Parameter
Supply current
Symbol
ICC
Test conditions
Subaddress
D7 D6 D5 D4 D3 D2 D1 D0
Current flowing to pin 15.
No signal
Maximum input voltage 1
VOM1
Input signal level of pins 13, 14, 16 and 17.
Distortion rate of pins 13, 14, 16 and 17: 1 %
Pins 26 and 27: Input SIN wave (1 kHz, 2.8 Vrms).
Maximum input voltage 2
VOM2
Input signal level of pin 11.
Distortion rate of pin 11: 1 %
Pin 26: Input SIN wave (1 kHz, 2.8 Vrms).
Pin 27: No signal
Distortion rate (L-ch)
THDL
Distortion rate of pins 14 and 17.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Distortion rate (R-ch)
THDR
Distortion rate of pins 13 and 16.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
Remark The methods are common to both the µPC1853CT-01 and µPC1853CT-02.
µPC1853
(1) µPC1853CT-01 Volume control, tone control block (1/9)
Data
Parameter
Symbol
Volume attenuation 1 (1)
ATTVL11
Test conditions
L1 output
Volume attenuation = 20 log
Volume attenuation 1 (2)
ATTVL12
Subaddress
01
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
L input
L1 output: Output signal level of pin 14.
L input: Input signal level of pin 26.
Volume attenuation 1 (3)
ATTVL13
Volume attenuation 2 (1)
ATTVL21
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
L2 output
Volume attenuation = 20 log
Volume attenuation 2 (2)
ATTVL22
06
L input
L2 output: Output signal level of pin 17.
L input: Input signal level of pin 26.
Volume attenuation 2 (3)
ATTVL23
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
L+R volume attenuation 1
ATTVLR1
L+R output
L+R volume attenuation = 20 log
L+R volume attenuation 2
ATTVLR2
05
L, R input
L+R output: Output signal level of pin 12.
L, R input: Input signal level of pin 26 or 27.
L+R volume attenuation 3
ATTVLR3
Rear volume attenuation 1
ATTVRE1
Pin 26, 27: Input SIN wave (1 kHz, 0.5 Vrms).
Rear output
Rear volume attenuation = 20 log
07
L input
Rear output: Output signal level of pin 11.
Rear volume attenuation 2
ATTVRE2
L input: Input signal level of pin 26.
Pin 27: No signal (Connect to GND with an input coupling capacitor).
45
µPC1853
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
46
(1) µPC1853CT-01 Volume control, tone control block (2/9)
Data
Parameter
Balance attenuation (L-ch) 1 (1)
Symbol
Test conditions
L1 output
ATTBL12
02
D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
00
1
0
↓
1
0
0
0
0
0
0
VBON: Output signal level of pin 14 (Low boost: ON).
01
0
1
1
1
1
1
1
1
VBOFF: Output signal level of pin 14 (Low boost: OFF).
00
1
0
↓
1
0
0
0
0
0
0
01
0
1
1
0
0
0
0
0
ATTBL11
Balance attenuation = 20 log
Balance attenuation (L-ch) 1 (2)
Subaddress
L input
L1 output: Output signal level of pin 14.
L input: Input signal level of pin 26.
Balance attenuation (L-ch) 1 (3)
ATTBL13
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Balance attenuation (R-ch) 1 (1)
ATTBR11
R1 output
Balance attenuation = 20 log
Balance attenuation (R-ch) 1 (2)
ATTBR12
02
R input
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
Balance attenuation (R-ch) 1 (3)
ATTBR13
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
Low-band boost control
L1 output
VBB
Bass response = 20 log
Low-band flat control
VBF
Low-band cut control
VBC
03
L input
L1 output: Output signal level of pin 14.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (100 Hz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Low-band boost control (6 dB) 1
VBON
VB6dB1
Bass response = 20 log
Low-band boost control (6 dB) 2
VB6dB2
VBOFF
Pin 26: Input SIN wave (100 Hz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
µPC1853
(1) µPC1853CT-01 Volume control, tone control block (3/9)
Data
Parameter
Low-band boost control (6 dB) 3
Symbol
Test conditions
VBON
VB6dB3
Subaddress
D7 D6 D5 D4 D3 D2 D1 D0
00
1
0
↓
1
0
0
0
0
0
0
01
0
1
0
1
0
0
0
0
00
1
0
↓
1
1
0
0
0
0
0
VBON : Output signal level of pin 14 (Low boost: ON).
01
0
1
1
1
1
1
1
1
VBOFF: Output signal level of pin 14 (Low boost: OFF).
00
1
0
↓
1
1
0
0
0
0
0
01
0
1
1
0
0
0
0
0
00
1
0
↓
1
1
0
0
0
0
0
01
0
1
0
1
0
0
0
0
04
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
Bass response = 20 log
VBOFF
VBON : Output signal level of pin 14 (Low boost: ON).
VBOFF: Output signal level of pin 14 (Low boost: OFF).
Pin 26: Input SIN wave (100 Hz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Low-band boost control (3 dB) 1
VBON
VB3dB1
Bass response = 20 log
Low-band boost control (3 dB) 2
VB3dB2
VBOFF
Pin 26: Input SIN wave (100 Hz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Low-band boost control (3 dB) 3
High-band boost control
VB3dB3
L1 output
VTB
Treble response = 20 log
High-band flat control
VTF
L input
L1 output: Output signal level of pin 14.
L input: Input signal level of pin 26.
High-band cut control
VTC
Pin 26: Input SIN wave (10 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
µPC1853
47
48
(1) µPC1853CT-01 Volume control, tone control block (4/9)
Data
Parameter
L, R in-phase gain difference 1 (1)
Symbol
Test conditions
Subaddress
R1 output
01
DG11
Channel to channel error = 20 log
R input
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
– ATTVL11
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
ATTVL11: Gain of the Volume attenuation 1 (1).
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
L, R in-phase gain difference 1 (2)
R1 output
DG12
Channel to channel error = 20 log
R input
– ATTVL12
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
ATTVL12: Gain of the Volume attenuation 1 (2).
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
L, R in-phase gain difference 2 (1)
R2 output
DG21
Channel to channel error = 20 log
R input
06
– ATTVL21
R2 output: Output signal level of pin 16.
R input: Input signal level of pin 27.
ATTVL21: Gain of the Volume attenuation 2 (1).
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
L, R in-phase gain difference 2 (2)
R2 output
DG22
Channel to channel error = 20 log
R input
– ATTVL22
R2 output: Output signal level of pin 16.
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
µPC1853
ATTVL22: Gain of the Volume attenuation 2 (2).
(1) µPC1853CT-01 Volume control, tone control block (5/9)
Data
Parameter
L, R in-phase gain difference 3 (1)
Symbol
Test conditions
Subaddress
R1 output
03
DG31
Channel to channel error = 20 log
R input
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
– VBB
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
VBB: Gain of the Low-band boost control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
L, R in-phase gain difference 3 (2)
R1 output
DG32
Channel to channel error = 20 log
R input
– VBF
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
VBF: Gain of the Low-band flat control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
L, R in-phase gain difference 3 (3)
R1 output
DG33
Channel to channel error = 20 log
R input
– VBC
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
VBC: Gain of the Low-band cut control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
L, R in-phase gain difference 4 (1)
R1 output
DG41
Channel to channel error = 20 log
R input
05
– VTB
R input: Input signal level of pin 27.
VTB: Gain of the High-band boost control.
49
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 Vrms).
µPC1853
R1 output: Output signal level of pin 13.
50
(1) µPC1853CT-01 Volume control, tone control block (6/9)
Data
Parameter
L, R in-phase gain difference 4 (2)
Symbol
Test conditions
Subaddress
R1 output
05
DG42
Channel to channel error = 20 log
R input
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
– VTF
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
VTF: Gain of the High-band flat control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 Vrms).
L, R in-phase gain difference 4 (3)
R1 output
DG43
Channel to channel error = 20 log
R input
– VTC
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
VTC: Gain of the High-band cut control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 Vrms).
L, R in-phase gain difference 5 (1)
VBON
DG51
Channel to channel error = 20 log
VBOFF
00
– VB6dB1
↓
VBON : Output signal level of pin 13 (Low boost: ON).
1
VBOFF : Output signal level of pin 13 (Low boost: OFF).
VB6dB1: Gain of the Low-band boost control (6 dB) 1.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
01
0
00
1
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
L, R in-phase gain difference 5 (2)
VBON
DG52
Channel to channel error = 20 log
VBOFF
– VB6dB2
↓
VBON : Output signal level of pin 13 (Low boost: ON).
1
VBOFF : Output signal level of pin 13 (Low boost: OFF).
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
01
0
1
µPC1853
VB6dB2: Gain of the Low-band boost control (6 dB) 2.
(1) µPC1853CT-01 Volume control, tone control block (7/9)
Data
Parameter
L, R in-phase gain difference 5 (3)
Symbol
Test conditions
VBON
DG53
Channel to channel error = 20 log
VBOFF
Subaddress
00
D7 D6 D5 D4 D3 D2 D1 D0
1
– VB6dB3
0
0
0
0
0
0
0
↓
VBON : Output signal level of pin 13 (Low boost: ON).
1
VBOFF : Output signal level of pin 13 (Low boost: OFF).
VB6dB3: Gain of the Low-band boost control (6 dB) 3.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
01
0
1
0
0
1
0
0
0
00
1
0
1
0
0
0
0
0
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
L, R in-phase gain difference 6 (1)
VBON
DG61
Channel to channel error = 20 log
VBOFF
– VB3dB1
↓
VBON : Output signal level of pin 13 (Low boost: ON).
1
VBOFF: Output signal level of pin 13 (Low boost: OFF).
VB3dB1: Gain of the Low-band boost control (3 dB) 1.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
01
0
1
1
1
1
1
1
1
00
1
0
1
0
0
0
0
0
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
L, R in-phase gain difference 6 (2)
VBON
DG62
Channel to channel error = 20 log
VBOFF
– VB3dB2
↓
VBON : Output signal level of pin 13 (Low boost: ON).
1
VBOFF: Output signal level of pin 13 (Low boost: OFF).
VB3dB2: Gain of the Low-band boost control (3 dB) 2.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
01
0
1
1
0
0
0
0
0
00
1
0
1
0
0
0
0
0
0
0
1
0
0
0
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
L, R in-phase gain difference 6 (3)
VBON
DG63
Channel to channel error = 20 log
VBOFF
– VB3dB3
↓
1
VBOFF : Output signal level of pin 13 (Low boost: OFF).
VB3dB3: Gain of the Low-band boost control (3 dB) 3.
51
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
01
0
1
µPC1853
VBON : Output signal level of pin 13 (Low boost: ON).
52
(1) µPC1853CT-01 Volume control, tone control block (8/9)
Data
Parameter
Muting attenuation 1
Symbol
Test conditions
Mute 1
L1 output
Mute 1 = 20 log
Subaddress
00
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
L input
L1 output : Output signal level of pin 14.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Muting attenuation 2
Mute 2
R1 output
Mute 2 = 20 log
R input
R1 output : Output signal level of pin 13.
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
Muting attenuation 3
Mute 3
L2 output
Mute 3 = 20 log
L input
L2 output : Output signal level of pin 17.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Muting attenuation 4
Mute 4
R2 output
Mute 4 = 20 log
R input
R2 output : Output signal level of pin 16.
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
µPC1853
(1) µPC1853CT-01 Volume control, tone control block (9/9)
Data
Parameter
Muting attenuation 5
Symbol
Test conditions
Mute 5
L+R output
Mute 5 = 20 log
Subaddress
00
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
L, R input
L+R output : Output signal level of pin 12.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (1 kHz, 0.5 Vrms).
Muting attenuation 6
Mute 6
(Rear)
Rear output
Mute 6 = 20 log
L input
Rear output : Output signal level of pin 11.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
DC offset at muting mode
VOS1
(L1 OUT, R1 OUT)
VOS1 = V1 - V0
00
V1: DC voltage of pin 14 or 13 (Main output mute: ON).
↓
V0: DC voltage of pin 14 or 13 (Main output mute: OFF).
1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
DC offset at muting mode
VOS2
(L2 OUT, R2 OUT)
VOS2 = V1 - V0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
V1: DC voltage of pin 17 or 16 (Audio output mute: ON).
↓
V0: DC voltage of pin 17 or 16 (Audio output mute: OFF).
1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
DC offset at muting mode
VOS3
(L+R OUT)
VOS3 = V1 - V0
1
0
0
0
0
V1: DC voltage of pin 12 (L+R output mute: ON).
↓
V0: DC voltage of pin 12 (L+R output mute: OFF).
1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
(Rear OUT)
VOS4
VOS4 = V1 - V0
1
0
0
0
V1: DC voltage of pin 11 (Rear output mute: ON).
↓
V0: DC voltage of pin 11 (Rear output mute: OFF).
1
53
Pins 26 and 27: Connect to GND with an input coupling capacitor.
0
µPC1853
DC offset at muting mode
54
(2) µPC1853CT-02 Volume control, tone control block (1/6)
Data
Parameter
Volume attenuation 1 (1) L-ch
Symbol
Test conditions
L1 output
ATTVL11
Volume attenuation = 20 log
Volume attenuation 1 (2) L-ch
ATTVL12
Subaddress
02
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
L input
L1 output: Output signal level of pin 14.
L input: Input signal level of pin 26.
Volume attenuation 1 (3) L-ch
ATTVL13
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Volume attenuation 1 (4) R-ch
ATTVR14
R1 output
Volume attenuation = 20 log
Volume attenuation 1 (5) R-ch
ATTVR15
01
R input
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
Volume attenuation 1 (6) R-ch
ATTVR16
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
Volume attenuation 2 (1)
L2 output
ATTVL21
Volume attenuation = 20 log
Volume attenuation 2 (2)
ATTVL22
Volume attenuation 2 (3)
ATTVL23
06
L input
L2 output: Output signal level of pin 17.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
L+R volume attenuation 1
ATTVLR1
L+R output
L+R volume attenuation = 20 log
L+R volume attenuation 2
ATTVLR2
05
L, R input
L+R output: Output signal level of pin 12.
L, R input: Input signal level of pin 26 or 27.
L+R volume attenuation 3
ATTVLR3
Pin 26, 27: Input SIN wave (1 kHz, 0.5 Vrms).
µPC1853
(2) µPC1853CT-02 Volume control, tone control block (2/6)
Data
Parameter
Rear volume attenuation 1
Symbol
Test conditions
Subaddress
Rear output
ATTVRE1
Rear volume attenuation = 20 log
07
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
L input
Rear output: Output signal level of pin 11.
Rear volume attenuation 2
ATTVRE2
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Low-band boost control
VBB
L1 output
Bass response = 20 log
Low-band flat control
VBF
03
L input
L1 output: Output signal level of pin 14.
L input: Input signal level of pin 26.
Low-band cut control
VBC
Pin 26: Input SIN wave (100 Hz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
High-band boost control
VTB
L1 output
Treble response = 20 log
High-band flat control
VTF
04
L input
L1 output: Output signal level of pin 14.
L input: Input signal level of pin 26.
High-band cut control
VTC
Pin 26: Input SIN wave (10 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
L, R in-phase gain difference 1 (1)
DG11
R1 output
Channel to channel error = 20 log
R input
01
– ATTVL11
02
R1 output : Output signal level of pin 13.
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
Same method about L-ch input/output signal
55
µPC1853
ATTVL11: Gain of the Volume attenuation 1 (1).
56
(2) µPC1853CT-02 Volume control, tone control block (3/6)
Data
Parameter
L, R in-phase gain difference 1 (2)
Symbol
Test conditions
Subaddress
R1 output
DG12
Channel to channel error = 20 log
R input
01
– ATTVL12
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
02
R1 output : Output signal level of pin 13.
R input: Input signal level of pin 27.
ATTVL12: Gain of the Volume attenuation 1 (2).
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
Same method about L-ch input/output signal
L, R in-phase gain difference 2 (1)
DG21
R2 output
Channel to channel error = 20 log
R input
06
– ATTVL21
R2 output : Output signal level of pin 16.
R input: Input signal level of pin 27.
ATTVL21: Gain of the Volume attenuation 2 (1).
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
L, R in-phase gain difference 2 (2)
R2 output
DG22
Channel to channel error = 20 log
R input
– ATTVL22
R2 output : Output signal level of pin 16.
R input: Input signal level of pin 27.
ATTVL22: Gain of the Volume attenuation 2 (2).
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
L, R in-phase gain difference 3 (1)
R1 output
DG31
Channel to channel error = 20 log
R input
03
– VBB
R1 output : Output signal level of pin 13.
VBB: Gain of the Low-band boost control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
µPC1853
R input: Input signal level of pin 27.
(2) µPC1853CT-02 Volume control, tone control block (4/6)
Data
Parameter
L, R in-phase gain difference 3 (2)
Symbol
Test conditions
Subaddress
R1 output
03
DG32
Channel to channel error = 20 log
R input
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
– VBF
R1 output : Output signal level of pin 13.
R input: Input signal level of pin 27.
VBF: Gain of the Low-band flat control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
L, R in-phase gain difference 3 (3)
R1 output
DG33
Channel to channel error = 20 log
R input
– VBC
R1 output : Output signal level of pin 13.
R input: Input signal level of pin 27.
VBC: Gain of the Low-band cut control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
L, R in-phase gain difference 4 (1)
R1 output
DG41
Channel to channel error = 20 log
R input
05
– VTB
R1 output : Output signal level of pin 13.
R input: Input signal level of pin 27.
VTB: Gain of the High-band boost control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 Vrms).
L, R in-phase gain difference 4 (2)
R1 output
DG42
Channel to channel error = 20 log
R input
– VTF
R input: Input signal level of pin 27.
VTF: Gain of the High-band flat control.
57
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 Vrms).
µPC1853
R1 output : Output signal level of pin 13.
58
(2) µPC1853CT-02 Volume control, tone control block (5/6)
Data
Parameter
L, R in-phase gain difference 4 (3)
Symbol
Test conditions
Subaddress
R1 output
05
0
1
0
0
0
0
0
1
00
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
DG43
Channel to channel error = 20 log
R input
D7 D6 D5 D4 D3 D2 D1 D0
– VTC
R1 output : Output signal level of pin 13.
R input: Input signal level of pin 27.
VTC: Gain of the High-band cut control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 Vrms).
Muting attenuation 1
Mute 1
L2 output
Mute 1 = 20 log
L input
L2 output : Output signal level of pin 17.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Muting attenuation 2
Mute 2
R2 output
Mute 2 = 20 log
R input
R2 output : Output signal level of pin 16.
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
Muting attenuation 3
Mute 3
L+R output
Mute 3 = 20 log
L, R input
L+R output : Output signal level of pin 12.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (1 kHz, 0.5 Vrms).
µPC1853
(2) µPC1853CT-02 Volume control, tone control block (6/6)
Data
Parameter
Muting attenuation 4
Symbol
Test conditions
Mute 4
(Rear)
Rear output
Mute 4 = 20 log
Subaddress
D7 D6 D5 D4 D3 D2 D1 D0
00
1
0
0
1
0
0
0
0
00
1
0
0
0
0
0
0
0
L input
Rear output : Output signal level of pin 11.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
DC offset at muting mode
VOS1
(L1OUT, R1 OUT)
VOS1 = V1 - V0
V1: DC voltage of pin 14 or 13 (Main output mute: ON).
↓
V0: DC voltage of pin 14 or 13 (Main output mute: OFF).
1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
DC offset at muting mode
VOS2
(L2 OUT, R2 OUT)
VOS2 = V1 - V0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
V1: DC voltage of pin 17 or 16 (Audio output mute: ON).
↓
V0: DC voltage of pin 17 or 16 (Audio output mute: OFF).
1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
DC offset at muting mode
VOS3
(L+R OUT)
VOS3 = V1 - V0
1
0
0
0
0
V1: DC voltage of pin 12 (L+R output mute: ON).
↓
V0: DC voltage of pin 12 (L+R output mute: OFF).
1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
DC offset at muting mode
(Rear OUT)
VOS4
VOS4 = V1 - V0
1
0
0
0
V1: DC voltage of pin 11 (Rear output mute: ON).
↓
V0: DC voltage of pin 11 (Rear output mute: OFF).
1
0
Pins 26 and 27: Connect to GND with an input coupling capacitor.
µPC1853
59
60
Matrix surround block (1/3)
Data
Parameter
In-phase gain
Symbol
Test conditions
L1, R1 output
GMOV1
Response = 20 log
Movie mode 1
Subaddress
D7 D6 D5 D4 D3 D2 D1 D0
08
1
1
0
0
1
0
0
0
08
1
1
1
0
1
0
0
0
08
1
1
0
1
1
0
0
0
L input
L1, R1 output: Output signal level of pin 14 or 13.
In-phase gain
GMOV2
Movie mode 2
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
In-phase gain
GMUS1
L1, R1 output
Response = 20 log
Music mode 1
L input
L1, R1 output: Output signal level of pin 14 or 13.
In-phase gain
GMUS2
Music mode 2
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
In-phase gain
L1 output
GSIML1
Response = 20 log
Simulated mode
(L-ch) 1
L, R input
L1 output : Output signal level of pin 14.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (250 Hz, 0.5 Vrms).
In-phase gain
L1 output
GSIML2
Response = 20 log
Simulated mode
(L-ch) 2
L, R input
L1 output : Output signal level of pin 14.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (1 kHz, 0.5 Vrms).
In-phase gain
Simulated mode
(L-ch) 3
L1 output
GSIML3
Response = 20 log
L, R input
L1 output : Output signal level of pin 14.
Pins 26 and 27: Input SIN wave (4 kHz, 0.5 Vrms).
Remark The methods are common to both the µPC1853CT-01 and µPC1853CT-02.
µPC1853
L, R input: Input signal level of pin 26 or 27.
Matrix surround block (2/3)
Data
Parameter
In-phase gain
Symbol
Test conditions
R1 output
GSIMR1
Response = 20 log
Simulated mode
(R-ch) 1
Subaddress
08
D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
1
1
0
0
0
L, R input
R1 output: Output signal level of pin 13.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (250 Hz, 0.5 Vrms).
In-phase gain
R1 output
GSIMR2
Response = 20 log
Simulated mode
(R-ch) 2
L, R input
R1 output: Output signal level of pin 13.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (1 kHz, 0.5 Vrms).
In-phase gain
R1 output
GSIMR3
Response = 20 log
Simulated mode
(R-ch) 3
L, R input
R1 output : Output signal level of pin 13.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (4 kHz, 0.5 Vrms).
Output noise
NO1
NO1: Output noise voltage of pins 11, 12, 13, 14, 16 and 17.
Pins 26 and 27: Connect to GND with an input coupling capacitor.
Filter of noise meter: DIN-AUDIO filter
Crosstalk 1
CT1
R output
Crosstalk = 20 log
L input
R output: Output signal level of pin 13 or 16.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz. 0.5 Vrms).
Remark The methods are common to both the µPC1853CT-01 and µPC1853CT-02.
61
µPC1853
Pin 27: No signal (Connect to GND with an input coupling capacitor).
62
Matrix surround block (3/3)
Data
Parameter
Crosstalk 2
Symbol
Test conditions
CT2
Subaddress
D7 D6 D5 D4 D3 D2 D1 D0
L output
Crosstalk = 20 log
R input
L output : Output signal level of pin 14 or 17.
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz. 0.5 Vrms).
Inter-mode offset
VOSM
No signal.
08
×
1
×
×
1
1
1
1
At surround mode switching.Note
Note See 4.3 Surround Function.
Remark The methods are common to both the µPC1853CT-01 and µPC1853CT-02.
µPC1853
µPC1853
6. CHARACTERISTIC CURVES
About surround mode, see 4.3 Surround Function.
6.1 Frequency Response Characteristics in Each Mode
(1) OFF mode (L-channel, R-channel)
VCC = 12 V
VIN = 1.4 Vp-p (= 0 dB)
8
6
Gain G (dB)
4
2
0
–2
–4
–6
100
1k
10 k
Frequency f (Hz)
63
µPC1853
(2) Movie Mode
10
VCC = 12 V
Lin: VIN = 1.4 Vp-p (= 0 dB)
Rin: GND
L1 OUT
R1 OUT
5
0
Gain G (dB)
–5
–10
–15
–20
–25
–30
–35
100
1k
10 k
Frequency f (Hz)
(3) Music Mode
12
VCC = 12 V
Lin: VIN = 1.4 Vp-p (= 0 dB)
Rin: GND
L1 OUT
R1 OUT
8
4
Gain G (dB)
0
–4
–8
–12
–16
–18
–20
100
1k
Frequency f (Hz)
64
10 k
µPC1853
(4) Simulated Mode
12
VCC = 12 V
Lin, Rin: VIN = 1.4 Vp-p (= 0 dB)
L1 OUT
R1 OUT
8
4
Gain G (dB)
0
–4
–8
–12
–16
–20
100
1k
10 k
Frequency f (Hz)
65
µPC1853
6.2 Characteristics of Phase Shifter and Rear Output
(1) Movie Mode
Gain G (dB)
0
Phase φ (deg.)
VCC = 12 V
Lin: VIN = 1.4 Vp-p (=0 dB)
Rin: GND
Rear OUT pin
Characteristics of
+100
Phase Shifter
Characteristics of
Rear Output
–10
0
–20
–100
10
30
50 70 100
300 500700 1 k
3k
5 k 7 k 10 k
20 k
Frequency f (Hz)
(2) Music Mode
Gain G (dB)
0
–10
0
–20
–100
10
30
50 70 100
300 500 700 1 k
Frequency f (Hz)
66
Phase φ (deg.)
VCC = 12 V
Lin: VIN = 1.4 Vp-p (=0 dB)
Rin: GND
Rear OUT pin
Characteristics of
Phase Shifter
+100
Characteristics of
Rear Output
3k
5 k 7 k 10 k
20 k
µPC1853
(3) Simulated Mode
VCC = 12 V
Lin, Rin: VIN = 1.4 Vp-p (=0 dB)
Rear OUT pin
Gain G (dB)
Phase φ (deg.)
+100
0
–10
0
–20
–100
10
30
50 70 100
300 500 700 1 k
3k
5 k 7 k 10 k
Characteristics of
Phase Shifter
Characteristics of
Rear Output
20 k
Frequency f (Hz)
67
µPC1853
6.3 Control Characteristics
(1) Volume Control Characteristics
0
OFF mode
f = 1 kHz
Lin or Rin: VIN = 1.4 Vp-p (=0 dB)
Lin or Rin: GND
–20
Attenuation (dB)
–40
–60
–80
–100
000000
001000
010000
011000
100000
101000
110000
111000
111111
Data of Subaddress: 01H (D5······D0)
(2) Balance Control Characteristics
0
OFF mode
f = 1 kHz
L1 OUT
Lin: VIN = 1.4 Vp-p (=0 dB)
Rin: GND
R1 OUT
Lin: GND
Rin: VIN = 1.4 Vp-p (=0 dB)
–20
Attenuation (dB)
–40
Lch
Rch
flat
ATT
Lch
Rch
ATT
flat
–60
–80
–100
000000
001000
010000
011000
100000
101000
110000
Data of Subaddress: 02H (D5······D0)
68
111000
111111
µPC1853
(3) Tone Control Characteristics (Bass)
10
OFF mode
Bass: f = 100 Hz
Lin: VIN = 1.4 Vp-p (=0 dB)
Rin: GND
L1 OUT
Attenuation (dB)
5
0
–5
–10
000000
001000
010000
011000
100000
101000
110000
111000
111111
Data of Subaddress: 03H (D5······D0)
(4) Tone Control Characteristics (Treble)
10
OFF mode
Treble: f = 10 kHz
Lin: VIN = 1.4 Vp-p (=0 dB)
Rin: GND
L1 OUT
Attenuation (dB)
5
0
–5
–10
000000
001000
010000
011000
100000
101000
110000
111000
111111
Data of Subaddress: 04H (D5······D0)
69
µPC1853
(5) Tone Frequency Characteristics
20
OFF mode
Lin: VIN = 1.4 Vp-p (=0 dB)
Rin: GND
L1 OUT
F
A
Curve
10
G
B
Gain G (dB)
H
C
I
D
111111
B
110000
J
E
03H
100000
D
010000
E
000001
F
111111
G
110000
H
–10
Data (D5 ·····D0)
A
C
0
Subaddress
04H
100000
I
010000
J
000001
–20
10
100
1k
10 k
100 k
Frequency f (Hz)
(6) Low Boost Control Characteristics
10
OFF mode
f = 100 Hz
Lin: VIN = 1.4 Vp-p (= 0 dB)
Rin : GND
L1 OUT
Low Boost 1 (6 dB)
Low Boost 2 (3 dB)
Attenuation (dB)
5
0
–5
–10
000000
001000
010000
011000
100000
101000
110000
Data of Subaddress: 01H (D5·····D0)
70
111000
111111
µPC1853
(7) Low Boost 1 (6 dB)
20
VCC = 12 V
Lin: VIN = 1.4 Vp-p (= 0 dB)
Rin: GND
L1 OUT
A
Curve
0
A
B
Data (D5 ·····D0)
111111
01H
C
B
Gain G (dB)
Subaddress
100000
010000
–20
C
–40
–60
10
100
1k
10 k
100 k
Frequency f (Hz)
(8) Low Boost 2 (3 dB)
20
VCC = 12 V
Lin: VIN = 1.4 Vp-p (= 0 dB)
Rin: GND
L1 OUT
A
Curve
0
Subaddress
A
Gain G (dB)
B
C
B
Data (D5 ·····D0)
111111
01H
100000
010000
–20
C
–40
–60
10
100
1k
10 k
100 k
Frequency f (Hz)
71
µPC1853
(9) Effect Control Characteristics
10
f = 1 kHz
Lin: VIN = 1.4 Vp-p (= 0 dB)
Rin: GND
Rear OUT pin
0 dB : Subaddress: 08 H, Data “1000”
0
Movie Mode
Music Mode
Simulated Mode
Attenuation (dB)
–10
–20
–30
–40
0000
0100
1000
Data of Subaddress: 08H (D3······D0)
72
1100
1111
µPC1853
5.0
5.0
1.0
1.0
0.5
0.5
0.1
0.1
0.05
0.05
Distortion Rate (%)
Output Signal Voltage (Vrms)
6.4 Input/Output Characteristics, Distortion Rate
f = 1 kHz
Lin or Rin: VIN = 1.4 Vp-p (= 0 dB)
Lin or Rin: GND
µ PC1853-01
Subaddress: 01H, Data “111111”
Subaddress: 02H, Data “100000”
µ PC1853-02
Subaddress: 01H, 02H,
Data “111111”
Output Signal Voltage
Distortion Rate
0.01
0.05
0.1
0.5
1.0
Input Signal Voltage (Vrms)
5.0
73
µPC1853
7. MEASURING CIRCUIT
L, R channel
signal input
I2C bus
DGND SDA SCL
DVDD (+5 V)
DGND
b
a
L channel
signal 2
output
R channel
signal 2 output
Switch 3
a b
b a
Switch 1
Switch 2
820 kΩ
Note
3.3 µF 3.3 µF
+
+
+
+
+
+
0.082 µF
BAL-C VOL-C
680 pF 22 µF 22 µF 22 µF 22 µF
(RVC)
(LVC) L2 OUT R2 OUT
DGND
1/2
V
CC
OFC
ADS SDA SCL
MFI MFO LF1
Rin
Lin
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Note
Note
µPC1853CT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FC1 FC2 FC3 FC4 LF2
RTC RBC LTC LBC Rear OUT L+R OUT R1 OUT L1 OUT VCC
AGND Note
Note
Note
Note
Note
Note
Note
Note
Note
0.01 µF
0.1 µF 2200 pF 0.022 µF 0.022 µF1000 pF 6800 pF 0.1 µF 6800 pF 0.1 µF
+
47 µF
Rear L+R Routput signal channel
output signal1
output
AGND
Note
Recommended external parts.
Lchannel
signal1
output
AVCC (+12 V)
Attention on Printed Wiring
Carbon-film resistor :
±1 %
1. AGND: Wide area grounding.
Film capacitor
:
±1 %
2. Connect terminating resistors as near pins 26 and 27
Ceramic capacitor
:
±1 %
as possible.
3. Make the wiring of I2C bus block distant from the
Use external parts as follows unless otherwise
74
wiring of analog block.
4. Connect by-pass capacitor near pin 15 (VCC pin).
specified.
Carbon-film resistor :
±5 %
Film capacitor
:
±20 %
Electrolytic capacitor :
±20 %
µPC1853
8. PACKAGE DIMENSIONS
30PIN PLASTIC SHRINK DIP (400 mil)
30
16
1
15
A
K
L
I
J
H
F
D
G
C
N
M
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
2) ltem "K" to center of leads when formed parallel.
M
R
B
ITEM
MILLIMETERS
INCHES
A
B
28.46 MAX.
1.78 MAX.
1.121 MAX.
0.070 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.85 MIN.
0.033 MIN.
G
H
3.2±0.3
0.51 MIN.
0.126±0.012
0.020 MIN.
I
J
4.31 MAX.
5.08 MAX.
0.170 MAX.
0.200 MAX.
K
10.16 (T.P.)
0.400 (T.P.)
L
8.6
0.339
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
S30C-70-400B-1
75
µPC1853
[MEMO]
Caution: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11