TDA7443D TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR WITH AGC PRODUCT PREVIEW ■ ■ ■ ■ ■ ■ ■ ■ INPUT MULTIPLEXER - 5 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT AGC TREBLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION TWO SURROND MODES AVAILABLE - MUSIC PSEUDO STEREO ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7443D is a volume tone (bass and treble) SO28 ORDERING NUMBER: TDA7443D balance (Left/Right) processor for quality audio applications in Hi-Fi systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. PIN CONNECTION (Top view) VS 1 28 PS1 AGC 2 27 LP L-IN1 3 26 R-IN1 L-IN2 4 25 R-IN2 L-IN3 5 24 R-IN3 L-IN4 6 23 R-IN4 L-IN5 7 22 R-IN5 L-MUX 8 21 R-MUX L-TREBLE 9 20 R-TREBLE L-BASSI 10 19 R-BASSI L-BASSO 11 18 R-BASSO L-OUT 12 17 R-OUT SDA 13 16 CREF SCL 14 15 GND D01AU1319 July 2002 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/15 1.2nF 0.47µF 0.47µF 0.47µF 0.47µF 0.47µF 100nF 100nF 0.47µF 0.47µF 0.47µF 0.47µF 28 PS1 7 6 5 4 3 50K 50K 50K 50K 50K 50K 50K 50K 50K 50K D01AU1328 L-IN5 L-IN4 L-IN3 L-IN2 L-IN1 2 27 LP AGC 26 25 24 23 22 R-IN1 R-IN2 R-IN3 R-IN4 R-IN5 VREF INPUT SELECT 1 GND 15 input gain: 0 to 14dB /2dB step input gain: 0 to 14dB /2dB step SUPPLY VS AGC CONTROL SURROUND INPUT SELECT 16 22µF CREF AGC gain: 0 to 7dB /1dB step AGC gain: 0 to 7dB /1dB step 8 L-MUX VOLUME IN SELECT MUTE NON SURROUND MUTE SURROUND IN SELECT SURROUND IN SELECT VOLUME IN SELECT MUTE NON-SURROUND MUTE R-MUX 21 SURROUND ON SURROUND ON 0.47µF SURROUND 2/15 SURROUND -63dB att. /1dB step VOLUME VOLUME -63dB att. /1dB step 19 100nF 5.6K R-BASSO -63 att. /1dB step BALANCE BASS 18 -14 to +14dB /2dB step RB R-BASSI 100nF 5.6nF L-TREBLE 9 -14 to +14dB /2dB step TREBLE 10 100nF 100nF 5.6K L-BASSI RB -14 to +14dB /2dB step BASS 11 L-BASSO -63 att. /1dB step BALANCE I2C BUS DECODER + LATCHES TREBLE -14 to +14dB /2dB step 20 R-TREBLE 5.6nF 12 13 14 17 L-OUT SDA SCL R-OUT TDA7443D BLOCK DIAGRAM & TEST CIRCUIT TDA7443D ABSOLUTE MAXIMUM RATINGS Symbol Vs Parameter Operating Supply Voltage Value Unit 10.5 V Tamb Operating Ambient Temperature -10 to 85 °C Tstg Storage Temperature Range -55 to 150 °C Value Unit 85 °C/W THERMAL DATA Symbol Rth j-pin Parameter Thermal Resistance Junction-pins QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. Unit 9 10 V VS Supply Voltage 5 VCL Max. input signal handling 2 THD Total Harmonic Distortion V=1Vrms f=1kHz 0.01 S/N Signal to Noise Ratio VOUT=1Vrms(mode=OFF) 100 dB SC Channel Separation f=1kHz 90 dB Vrms 0.1 % Input Gain (2dB step) 0 14 dB AGC Gain (1dB step) 0 7 dB Volume Control (1dB step) -63 0 dB Treble Control (2dB step) -14 +14 dB Bass Control (2dB step) -14 +14 dB Balance Control (1dB step) -63 0 dB Mute Attenuation 90 dB 3/15 TDA7443D ELECTRICAL CHARACTERISTICS (Refer to the test circuit Tamb=25C, Vs=9V, f=1kHz ,all controls flat, unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit 5 9 10 V SUPPLY VS Supply Voltage IS Supply Current SVR Ripple Rejection tbd mA 60 80 dB 35 50 2 2.5 Vrms dB INPUT STAGE RIN Input Resistance VCL Clipping Level SIN Input Separation 80 100 Gin min Minimum Input Gain -1 0 1 dB Gin max Maximum Input Gain 13 14 15 dB Gin step Step Resolution 1.5 2 2.5 dB GAGCmin Minimum AGC Gain -1 0 1 dB GAGCmax Maximum AGC Gain 6 7 8 dB 0.5 1 1.5 dB Input Resistance 35 50 65 kΩ RPS0 Phase Shifter:D1=0,D0=0 8.3 11.8 15.2 kΩ RPS1 Phase Shifter:D1=0,D0=1 10 14.1 18.3 kΩ RPS2 Phase Shifter:D1=1,D0=0 12.6 17.9 23.3 kΩ RPS3 Phase Shifter:D1=1,D0=1 26.4 37.3 48.85 kΩ Effect Control Range -21 -6 dB Effect Control Step Resolution 0.5 1 1.5 dB THD = 0.3% 65 kΩ AGC GAGCstep Step Resolution SURROUND RIN CRANGE Sstep VOLUME CONTROL AVOLmin Minimum Attenuation -1 0 1 dB AVOLmax Maximum Attenuation 61 63 65 dB AVOLstep Step Resolution 0.5 1 1.5 dB EA Attenuation set error AV = 0 to –24 dB -1 0 1 dB AV = –24 to –63 dB -2 0 2 dB Adjacent att. steps -3 0 3 mV ±12 ±14 ±16 dB VDC DC Steps BASS CONTROL GB 4/15 Control Range Max. Boost/Cut TDA7443D ELECTRICAL CHARACTERISTICS (continued) (Refer to the test circuit Tamb=25C, Vs=9V, f=1kHz ,all controls flat, unless otherwise specified) Symbol Bstep RB Parameter Conditions Min. Typ. Max. Unit Step Resolution 1 2 3 dB Internal Feedback Resistance 33 44 55 kΩ ±13 ±14 ±15 dB 1 2 3 dB TREBLE CONTROL GT Tstep RT Control Range Max. Boost/Cut Step Resolution Internal Feedback Resistance 25 kΩ BALANCE CONTROL ABALmin Minimum Attenuation -1 0 1 dB ABALmax Maximum Attenuation 61 63 65 dB ABALstep Step Resolution EA VDC Attenuation set error DC Steps 1 dB AV = 0 to –24 dB -1 0 1 dB AV = –24 to –63 dB -2 0 2 dB Adjacent att. steps -3 0 3 mV THD = 0.3% 2 2.5 AUDIO OUTPUTS VOCL RL VOUT NO(OFF) NO(MUS) NO(PS) AMUTE Clipping Level Output Load Resistance Output Noise (Music) Output Noise(Pseudo Stereo) Signal to Noise Ratio SC Channel Separation Left/Right Distortion kΩ 4.5 V BW=20Hz to 20kHz; All gains 0dB; Output muted flat 5 10 BW=20Hz to 20kHz; Mode=Music 30 µV BW=20Hz to 20kHz; Mode=Pseudo Stereo 30 µV 90 dB 100 dB 90 dB Output Mute Condition S/N d 2 DC Voltage Level Output Noise (OFF) Vrms All gains 0dB;VO = 1Vrms AV = 0; VI = 1Vrms 0.01 15 µV µV 0.1 % 1 V BUS INPUT VIL Input Low Voltage VIH Input High Voltage IIN Input Current VIN = 0.4V VO Output Voltage (ACK) IO = 1.6mA 2.5 V -5 0.4 5 µA 0.8 V 5/15 TDA7443D I2C BUS INTERFACE Data transmission from microprocessor to the TDA7443D and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig. 2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 3). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 1. Data Validity on the I2CBUS SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 2. Timing Diagram of I2CBUS SCL I2CBUS SDA D99AU1032 START STOP Figure 3. Acknowledge on the I2CBUS SCL 1 2 3 7 8 9 SDA MSB START 6/15 D99AU1033 ACKNOWLEDGMENT FROM RECEIVER TDA7443D SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: ■ A start condition (S) ■ A chip address byte, containing the TDA7440D address ■ A subaddress bytes ■ A sequence of data (N byte + acknowledge) ■ A stop condition (P) SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 DATA 1 to DATA n MSB ACK X LSB X X B DATA MSB ACK LSB DATA ACK P D96AU420 ACK = Acknowledge; S = Start; P = Stop; A = Address; B = Auto Increment EXAMPLES No Incremental Bus The TDA7443D receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition. SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA LSB X X 0 D3 D2 D1 D0 MSB ACK LSB DATA ACK P D96AU421 Incremental Bus The TDA7443D receivea start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA 1 to DATA n LSB X X 1 D3 D2 D1 D0 MSB ACK LSB DATA ACK P D96AU422 7/15 TDA7443D POWER ON RESET CONDITION MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 0 DATA BYTES Address=(HEX) 10001000 FUNCTION SELECTION: First byte (subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 X X X B 0 0 0 0 X X X B 0 0 0 1 AGC X X X B 0 0 1 0 SURROUND X X X B 0 0 1 1 VOLUME X X X B 0 1 0 0 TONE X X X B 0 1 0 1 BALANCE “L” X X X B 0 1 1 0 BALANCE “R” D3 D2 D1 D0 0 0 0 IN1 0 0 1 IN2 0 1 0 IN3 INPUT B=1: INCREMENTAL BUS; ACTIVE B=0: NO INCREMENTAL BUS X= INDIFFERENT 0/1 INPUT MSB D7 LSB D6 D5 D4 SUBADDRESS INPUT SELECT 0 1 1 IN4 1 X X IN5 MUTE 0 Output Mute OFF 1 Output Mute ON SURROUND IN SELECT 0 1 Surround ONl Mute INPUT GAIN 8/15 0 0 0 0dB 0 0 1 2dB 0 1 0 4dB 0 1 1 6dB 1 0 0 8dB 1 0 1 10dB 1 1 0 12dB 1 1 1 14dB TDA7443D AGC MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 AGC MODE 0 OFF 1 ON DETECTOR 0 OFF 1 ON RELEASE CURRENT 0 OFF 1 ON ATTACK TIME 0 0 ATTACK1 0 1 ATTACK2 1 0 ATTACK3 1 1 ATTACK4 TARGET LEVEL 0 0 TARGET1 0 1 TARGET2 1 0 TARGET3 1 1 TARGET4 ZEROCROSS 0 OFF 1 ON 9/15 TDA7443D SURROUND MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 SURROUND MODE 0 PSEUDO STEREO 1 MUSIC EFFECT CONTROL 0 0 0 0 -6 dB 0 0 0 1 -7 dB 0 0 1 0 -8 dB 0 0 1 1 -9 dB 0 1 0 0 -10 dB 0 1 0 1 -11 dB 0 1 1 0 -12 dB 0 1 1 1 -13 dB 1 0 0 0 -14 dB 1 0 0 1 -15 dB 1 0 1 0 -16 dB 1 0 1 1 -17 dB 1 1 0 0 -18 dB 1 1 0 1 -19 dB 1 1 1 0 -20 dB 1 1 1 1 -21 dB PHASE SHIFT RESISTOR 0 0 12 kohm 0 1 14 kohm 1 0 18 kohm 1 1 37 kohm 10/15 TDA7443D VOLUME MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 VOLUME IN SELECT 0 0 Surround 0 1 Non Surround 1 X Mute 1dB STEPS 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 8dB STEPS 0 0 0 0dB 0 0 1 -8dB 0 1 0 -16dB 0 1 1 -24dB 1 0 0 -32dB 1 0 1 -40dB 1 1 0 -48dB 1 1 1 -56dB VOLUME=0 to –63dB 11/15 TDA7443D TREBLE & BASS MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 TREBLE 0 0 0 0 -14 dB 0 0 0 1 -12 dB 0 0 1 0 -10 dB 0 0 1 1 -8 dB 0 1 0 0 -6 dB 0 1 0 1 -4 dB 0 1 1 0 -2 dB 0 1 1 1 0 dB 1 0 0 0 14 dB 1 0 0 1 12 dB 1 0 1 0 10 dB 1 0 1 1 8 dB 1 1 0 0 6 dB 1 1 0 1 4 dB 1 1 1 0 2 dB 1 1 1 1 0 dB BASS 0 0 0 0 -14 dB 0 0 0 1 -12 dB 0 0 1 0 -10 dB 0 0 1 1 -8 dB 0 1 0 0 -6 dB 0 1 0 1 -4 dB 0 1 1 0 -2 dB 0 1 1 1 0 dB 1 0 0 0 14 dB 1 0 0 1 12 dB 1 0 1 0 10 dB 1 0 1 1 8 dB 1 1 0 0 6 dB 1 1 0 1 4 dB 1 1 1 0 2 dB 1 1 1 1 0 dB 12/15 TDA7443D BALANCE MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 1dB STEPS 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 8dB STEPS 0 0 0 0dB 0 0 1 -8dB 0 1 0 -16dB 0 1 1 -24dB 1 0 0 -32dB 1 0 1 -40dB 1 1 0 -48dB 1 1 1 -56dB VOLUME=0 to –63dB 13/15 TDA7443D mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S 14/15 OUTLINE AND MECHANICAL DATA 8 ° (max.) SO28 TDA7443D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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