DATA SHEET MOS INTEGRATED CIRCUIT µ PD44321182, 44321362 32M-BIT ZEROSBTM SRAM PIPELINED OPERATION Description The µPD44321182 is a 2,097,152-word by 18-bit and the µPD44321362 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44321182 and µPD44321362 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD44321182 and µPD44321362 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD44321182 and µPD44321362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • Low voltage core supply : VDD = 3.3 ± 0.165 V / 2.5 ± 0.125 V • Synchronous operation • 100 percent bus utilization • Internally self-timed write control • Burst read / write : Interleaved burst and linear burst sequence • Fully registered inputs and outputs for pipelined operation • All registers triggered off positive clock edge • 3.3V or 2.5V LVTTL Compatible : All inputs and outputs • Fast clock access time : 3.2 ns (200 MHz) • Asynchronous output enable : /G • Burst sequence selectable : MODE • Sleep mode : ZZ (ZZ = Open or Low : Normal operation) • Separate byte write enable : /BW1 to /BW4 (µPD44321362) /BW1 and /BW2 (µPD44321182) • Three chip enables for easy depth expansion • Common I/O using three state outputs The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. Document No. M16024EJ5V0DS00 (5th edition) Date Published April 2005 NS CP(K) Printed in Japan The mark shows major revised points. 2002, 2005 µPD44321182, 44321362 Ordering Information Part number µPD44321182GF-A50 µPD44321362GF-A50 2 Access Clock Core Supply Time Frequency Voltage ns MHz V 3.2 200 3.3 ± 0.165 3.2 200 I/O Interface Package 3.3 V or 2.5 V LVTTL 100-pin PLASTIC LQFP 2.5 ± 0.125 2.5 V LVTTL 3.3 ± 0.165 3.3 V or 2.5 V LVTTL 2.5 ± 0.125 2.5 V LVTTL Data Sheet M16024EJ5V0DS (14 x 20) µPD44321182, 44321362 Pin Configurations /××× indicates active low signal. 100-pin PLASTIC LQFP (14 × 20) [µPD44321182GF] A9 A8 A17 A18 ADV /G /CKE /WE CLK VSS VDD /CE2 /BW1 /BW2 NC NC CE2 /CE A7 A6 Marking Side 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC 1 80 A20 NC 2 79 NC NC 3 78 NC VDDQ 4 77 VDDQ VSSQ 5 76 VSSQ NC 6 75 NC NC 7 74 I/OP1 I/O9 8 73 I/O8 I/O10 9 72 I/O7 VSSQ 10 71 VSSQ VDDQ 11 70 VDDQ I/O11 12 69 I/O6 I/O12 13 68 I/O5 VDD 14 67 VSS VDD 15 66 VDD VDD 16 65 VDD VSS 17 64 ZZ I/O13 18 63 I/O4 I/O14 19 62 I/O3 VDDQ 20 61 VDDQ VSSQ 21 60 VSSQ I/O15 22 59 I/O2 I/O16 23 58 I/O1 I/OP2 24 57 NC NC 25 56 NC VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ NC 28 53 NC NC 29 52 NC NC 30 51 NC A16 A15 A14 A13 A12 A11 A10 A19 NC VDD VSS NC NC A0 A1 A2 A3 A4 A5 MODE 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M16024EJ5V0DS 3 µPD44321182, 44321362 Pin Identifications [µPD44321182GF] Symbol A0 to A20 Pin No. Description 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input 45, 46, 47, 48, 49, 50, 83, 84, 43, 80 I/O1 to I/O16 I/OP1, I/OP2 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In, 18, 19, 22, 23 Synchronous / Asynchronous Data Out 74, 24 Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity) ADV 85 Synchronous Address Load / Advance Input /CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input /WE 88 Synchronous Write Enable Input /BW1, /BW2 93, 94 Synchronous Byte Write Enable Input /G 86 Asynchronous Output Enable Input CLK 89 Clock Input /CKE 87 Synchronous Clock Enable Input MODE 31 Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation ZZ 64 Asynchronous Power Down State Input VDD 14, 15, 16, 41, 65, 66, 91 Power Supply VSS 17, 40, 67, 90 Ground VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground NC 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 51, No Connection 52, 53, 56, 57, 75, 78, 79, 95, 96 4 Data Sheet M16024EJ5V0DS µPD44321182, 44321362 100-pin PLASTIC LQFP (14 × 20) [µPD44321362GF] A9 A8 A17 A18 ADV /G /CKE /WE CLK VSS VDD /CE2 /BW1 /BW2 /BW3 /BW4 CE2 /CE A7 A6 Marking Side 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 1 80 I/OP2 I/O17 2 79 I/O16 I/O18 3 78 I/O15 VDDQ 4 77 VDDQ VSSQ 5 76 VSSQ I/O19 6 75 I/O14 I/O20 7 74 I/O13 I/O21 8 73 I/O12 I/O22 9 72 I/O11 VSSQ 10 71 VSSQ VDDQ 11 70 VDDQ I/O23 12 69 I/O10 I/O24 13 68 I/O9 VDD 14 67 VSS VDD 15 66 VDD VDD 16 65 VDD VSS 17 64 ZZ I/O25 18 63 I/O8 I/O26 19 62 I/O7 VDDQ 20 61 VDDQ VSSQ 21 60 VSSQ I/O27 22 59 I/O6 I/O28 23 58 I/O5 I/O29 24 57 I/O4 I/O30 25 56 I/O3 VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ I/O31 28 53 I/O2 I/O32 29 52 I/O1 I/OP4 30 51 I/OP1 A16 A15 A14 A13 A12 A11 A10 A19 NC VDD VSS NC NC A0 A1 A2 A3 A4 A5 MODE 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M16024EJ5V0DS 5 µPD44321182, 44321362 Pin Identifications [µPD44321362GF] Symbol A0 to A19 Pin No. Description 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input 45, 46, 47, 48, 49, 50, 83, 84, 43 I/O1 to I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out 18, 19, 22, 23, 24, 25, 28, 29 I/OP1 to I/OP4 51, 80, 1, 30 Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity) ADV 85 Synchronous Address Load / Advance Input /CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input /WE 88 Synchronous Write Enable Input /BW1 to /BW4 93, 94, 95, 96 Synchronous Byte Write Enable Input /G 86 Asynchronous Output Enable Input CLK 89 Clock Input /CKE 87 Synchronous Clock Enable Input MODE 31 Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation ZZ 64 Asynchronous Power Down State Input VDD 14, 15, 16, 41, 65, 66, 91 Power Supply VSS 17, 40, 67, 90 Ground VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground NC 38, 39, 42 No Connection 6 Data Sheet M16024EJ5V0DS µPD44321182, 44321362 Block Diagrams [µPD44321182] A0 to A20 21 Address register 0 MODE CLK 19 A1 A0 Burst logic ADV K K 21 A1’ A0’ /CKE 21 Write address register 1 2,048 x 18 columns (37,748,736 bits) /WE I/O1 to I/O16 I/OP1, I/OP2 18 18 Input register 1 E /G 18 E E 18 /CE 18 Output buffers 1,024 rows Data steering Write drivers Output registers Memory Cell Array Write registry and data coherency control logic Sense amplifiers ADV /BW1 /BW2 Write address register 0 21 Input register 0 E Read logic CE2 /CE2 ZZ Power down control Burst Sequence [µPD44321182] Interleaved Burst Sequence Table (MODE = VDD) External Address A20 to A2, A1, A0 1st Burst Address A20 to A2, A1, /A0 2nd Burst Address A20 to A2, /A1, A0 3rd Burst Address A20 to A2, /A1, /A0 Linear Burst Sequence Table (MODE = VSS) External Address A20 to A2, 0, 0 A20 to A2, 0, 1 A20 to A2, 1, 0 A20 to A2, 1, 1 1st Burst Address A20 to A2, 0, 1 A20 to A2, 1, 0 A20 to A2, 1, 1 A20 to A2, 0, 0 2nd Burst Address A20 to A2, 1, 0 A20 to A2, 1, 1 A20 to A2, 0, 0 A20 to A2, 0, 1 3rd Burst Address A20 to A2, 1, 1 A20 to A2, 0, 0 A20 to A2, 0, 1 A20 to A2, 1, 0 Data Sheet M16024EJ5V0DS 7 µPD44321182, 44321362 [µPD44321362] A0 to A19 20 Address register 0 MODE CLK 18 A1 A0 ADV K K Burst logic 20 A1’ A0’ /CKE 20 Write address register 1 1,024 x 36 columns (37,748,736 bits) I/O1 to I/O32 I/OP1 to I/OP4 36 36 Input register 1 E /G 36 E E 36 /CE 36 Output buffers 1,024 rows Data steering Write drivers Output registers Memory Cell Array Write registry and data coherency control logic Sense amplifiers ADV /BW1 /BW2 /BW3 /BW4 /WE Write address register 0 20 Input register 0 E Read logic CE2 /CE2 ZZ Power down control Burst Sequence [µPD44321362] Interleaved Burst Sequence Table (MODE = VDD) External Address A19 to A2, A1, A0 1st Burst Address A19 to A2, A1, /A0 2nd Burst Address A19 to A2, /A1, A0 3rd Burst Address A19 to A2, /A1, /A0 Linear Burst Sequence Table (MODE = VSS) External Address A19 to A2, 0, 0 A19 to A2, 0, 1 A19 to A2, 1, 0 A19 to A2, 1, 1 1st Burst Address A19 to A2, 0, 1 A19 to A2, 1, 0 A19 to A2, 1, 1 A19 to A2, 0, 0 2nd Burst Address A19 to A2, 1, 0 A19 to A2, 1, 1 A19 to A2, 0, 0 A19 to A2, 0, 1 3rd Burst Address A19 to A2, 1, 1 A19 to A2, 0, 0 A19 to A2, 0, 1 A19 to A2, 1, 0 8 Data Sheet M16024EJ5V0DS µPD44321182, 44321362 State Diagram DS BURST DS DS DESELECT WRITE READ DS DS WRITE BEGIN READ READ READ READ BURST BURST WRITE BURST Command BEGIN WRITE WRITE WRITE READ BURST READ BURST WRITE BURST Operation DS Deselect Read New Read Write New Write Burst Burst Read, Burst Write or Continue Deselect Remarks 1. States change on the rising edge of the clock. 2. A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH only blocks the clock (CLK) input and does not change the state of the device. Data Sheet M16024EJ5V0DS 9 µPD44321182, 44321362 Asynchronous Truth Table Operation /G I/O Read Cycle L Data-Out Read Cycle H High-Z Write Cycle × High-Z, Data-In Deselected × High-Z Remark × : don’t care Synchronous Truth Table Operation /CE CE2 /CE2 ADV /WE /BWs /CKE CLK I/O Address Note Deselected H × × L × × L L→H High-Z None 1 Deselected × L × L × × L L→H High-Z None 1 Deselected × × H L × × L L→H High-Z None 1 Continue Deselected × × × H × × L L→H High-Z None 1 Read Cycle / Begin Burst L H L L H × L L→H Data-Out External Read Cycle / Continue Burst × × × H × × L L→H Data-Out Next Write Cycle / Begin Burst L H L L L L L L→H Data-In External Write Cycle / Continue Burst × × × H × L L L→H Data-In Next Write Cycle / Write Abort L H L L L H L L→H High-Z External Write Cycle / Write Abort × × × H × H L L→H High-Z Next Stall / Ignore Clock Edge × × × × × × H L→H − Current Notes 2 1. Deselect status is held until new “Begin Burst” entry. 2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (Lowimpedance). If it occurs during a write cycle, the bus will remain High impedance. No write operation will be performed during the Ignore Clock Edge cycle. Remarks 1. × : don’t care 2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW. /BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH. 10 Data Sheet M16024EJ5V0DS µPD44321182, 44321362 Partial Truth Table for Write Enables [µPD44321182] Operation /WE /BW1 /BW2 Read Cycle H × × Write Cycle / Byte 1 (I/O [1:8], I/OP1) L L H Write Cycle / Byte 2 (I/O [9:16], I/OP2) L H L Write Cycle / All Bytes L L L Write Abort / NOP L H H /WE /BW1 /BW2 /BW3 /BW4 Read Cycle H × × × × Write Cycle / Byte 1 (I/O [1:8], I/OP1) L L H H H Write Cycle / Byte 2 (I/O [9:16], I/OP2) L H L H H Write Cycle / Byte 3 (I/O [17:24], I/OP3) L H H L H Write Cycle / Byte 4 (I/O [25:32], I/OP4) L H H H L Write Cycle / All Bytes L L L L L Write Abort / NOP L H H H H Remark × : don’t care [µPD44321362] Operation Remark × : don’t care ZZ (Sleep) Truth Table ZZ Chip Status ≤ 0.2 V Active Open Active ≥ VDD − 0.2 V Sleep Data Sheet M16024EJ5V0DS 11 µPD44321182, 44321362 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Output supply voltage Input voltage Symbol Conditions VDD MIN. TYP. –0.5 VDDQ –0.5 VIN MAX. Unit +4.0 V VDD V –0.5 Note VDD + 0.5 V Note VDDQ + 0.5 V Input / Output voltage VI/O –0.5 Operating ambient TA 0 70 °C Tstg –55 +125 °C temperature Storage temperature Note –2.0 V (MIN.) (Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (VDD = 3.3 ± 0.165 V) Parameter Supply voltage Symbol Conditions (1/2) MIN. TYP. MAX. Unit VDD 3.135 3.3 3.465 V VDDQ 2.375 2.5 2.9 V VIH 2.0 VDDQ + 0.3 V +0.7 V 2.5 V LVTTL Interface Output supply voltage High level input voltage Low level input voltage VIL –0.3 Note 3.3 V LVTTL Interface Output supply voltage VDDQ 3.135 High level input voltage VIH 2.0 Low level input voltage VIL –0.3 3.3 Note 3.465 V VDDQ + 0.3 V +0.8 V Note –0.8 V (MIN.) (Pulse width : 2 ns) Recommended DC Operating Conditions (VDD = 2.5 ± 0.125 V) Parameter Supply voltage Output supply voltage Symbol Conditions (2/2) MIN. TYP. MAX. Unit VDD 2.375 2.5 2.625 V 2.5 VDDQ 2.375 High level input voltage VIH 1.7 Low level input voltage VIL –0.3 Note –0.8 V (MIN.) (Pulse width : 2 ns) 12 Data Sheet M16024EJ5V0DS Note 2.625 V VDDQ + 0.3 V +0.7 V µPD44321182, 44321362 DC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current ILI VIN (except ZZ, MODE) = 0 V to VDD –2 +2 µA I/O leakage current ILO VI/O = 0 V to VDDQ, Outputs are disabled. –2 +2 µA Operating supply current IDD Device selected, Cycle = MAX. 410 mA 70 mA VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA Standby supply current ISB Device deselected, Cycle = 0 MHz, VIN ≤ VIL or VIN ≥ VIH, All inputs are static. ISB1 Device deselected, Cycle = 0 MHz, 60 VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V, VI/O ≤ 0.2 V, All inputs are static. ISB2 Device deselected, Cycle = MAX. 130 VIN ≤ VIL or VIN ≥ VIH Power down supply current ISBZZ ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V VOH IOH = –2.0 mA 1.7 IOH = –1.0 mA 2.1 60 mA 2.5 V LVTTL Interface High level output voltage Low level output voltage VOL V IOL = +2.0 mA 0.7 IOL = +1.0 mA 0.4 V 3.3 V LVTTL Interface High level output voltage VOH IOH = –4.0 mA Low level output voltage VOL IOL = +8.0 mA 2.4 V 0.4 V MAX. Unit Capacitance (TA = 25 °C, f = 1MHz) Parameter Symbol Test condition MIN. TYP. Input capacitance CIN VIN = 0 V 6.0 pF Input / Output capacitance CI/O VI/O = 0 V 8.0 pF Clock input capacitance Cclk Vclk = 0 V 6.0 pF Remark These parameters are periodically sampled and not 100% tested. Data Sheet M16024EJ5V0DS 13 µPD44321182, 44321362 AC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V) AC Test Conditions 2.5 V LVTTL Interface Input waveform (Rise / Fall time ≤ 2.4 ns) 2.4 V 1.2 V Test points 1.2 V 1.2 V Test points 1.2 V VSS Output waveform 3.3 V LVTTL Interface Input waveform (Rise / Fall time ≤ 3.0 ns) 3.0 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V VSS Output waveform Output load condition CL : 30 pF 5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ) Figure External load at test ZO = 50 Ω I/O (Output) 50 Ω CL VT = +1.2 V / +1.5 V Remark CL includes capacitances of the probe and jig, and stray capacitances. 14 Data Sheet M16024EJ5V0DS µPD44321182, 44321362 Read and Write Cycle Parameter Symbol -A50 (200 MHz) Unit Notes Standard Alias MIN. MAX. Cycle time TKHKH TCYC 5 – ns Clock access time TKHQV TCD – 3.2 ns Output enable access time TGLQV TOE – 3.2 ns Clock high to output active TKHQX1 TDC1 1.5 – ns Clock high to output change TKHQX2 TDC2 1.5 – ns Output enable to output active TGLQX TOLZ 0 – ns 1 Output disable to output High-Z TGHQZ TOHZ 0 3.2 ns 1 Clock high to output High-Z TKHQZ TCZ 1.5 3.2 ns 1, 2 Clock high pulse width TKHKL TCH 1.8 – ns Clock low pulse width TKLKH TCL 1.8 – ns Setup times TAVKH TAS 1.5 – ns TADVVKH TADVS Clock enable TEVKH TCES Chip enable TCVKH TCSS Data in TDVKH TDS Write enable TWVKH TWS Address TKHAX TAH 0.5 – ns TKHADVX TADVH (1.0) (–) Clock enable TKHEX TCEH Chip enable TKHCX TCSH Data in TKHDX TDH Write enable TKHWX TWH Power down entry time TZZE TZZE – 10 ns Power down recovery time TZZR TZZR – 10 ns Address Address advance Hold times Address advance 1, 2 3 Notes 1. Transition is measured ±200 mV from steady state. 2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA min., VDD max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.). 3. These values apply when VDD = 3.3 V ±0.165 V with a 3.3 V LVTTL interface, or when VDD = 2.5 V ±0.125 V with a 2.5 V LVTTL interface. Values in parentheses apply when VDD = 3.3 V ±0.165 V with a 2.5 V LVTTL interface. Data Sheet M16024EJ5V0DS 15 µPD44321182, 44321362 READ / WRITE CYCLE 2 TKHKH 3 1 4 5 6 A3 A4 D (A2) D (A2+1) 7 8 A5 A6 9 10 CLK TEVKH TKHEX TCVKH TKHCX TKHKL TKLKH /CKE /CEs Note 1 TADVVKH TKHADVX ADV TWVKH TKHWX /WE TWVKH TKHWX /BWs Note 2 Address Data In A2 A1 TAVKH TKHAX High-Z D (A1) TDVKH Data Out TKHDX A7 High-Z TKHQX1 TKHQX2 High-Z Q (A3) TKHQV D (A5) High-Z TGLQV TKHQZ Q (A4) Q (A4+1) High-Z Q (A6) TKHQX2 TGHQZ TGLQX /G Command Notes WRITE D (A1) WRITE D (A2) BURST WRITE D (A2+1) READ Q (A3) READ Q (A4) BURST READ Q (A4+1) WRITE D (A5) READ Q (A6) WRITE Q (A7) DESELECT 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW. 16 Data Sheet M16024EJ5V0DS µPD44321182, 44321362 NOP, STALL AND DESELECT CYCLE 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK /CKE /CEs ADV /WE /BWs Address High-Z High-Z D (A1) Data In A5 High-Z D (A4) TKHQZ Data Out High-Z Q (A2) High-Z Q (A3) Q (A5) TKHQX2 Command WRITE D (A1) READ Q (A2) STALL READ Q (A3) WRITE D (A4) STALL Data Sheet M16024EJ5V0DS NOP READ Q (A5) DESELECT CONTINUE DESELECT 17 µPD44321182, 44321362 POWER DOWN (ZZ) CYCLE 1 2 TKHKH 3 4 5 6 7 8 9 10 11 12 CLK TKHKL TKLKH /CKE /CEs Note ADV /WE Note /BWs Address A1 A2 /G Data Out High-Z High-Z Q1 (A2) Q (A1) ZZ TZZE TZZR Power Down (ISBZZ) State Note /WE or /CEs must be held HIGH at CLK rising edge (clock edge No.2 and No.3 in this figure) prior to power down state entry. 18 Data Sheet M16024EJ5V0DS µPD44321182, 44321362 Package Drawing 100-PIN PLASTIC LQFP (14x20) A B 80 81 51 50 detail of lead end S C D R Q 31 30 100 1 F G H I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 22.0±0.2 B 20.0±0.2 C 14.0±0.2 D 16.0±0.2 F 0.825 G 0.575 H 0.32 +0.08 −0.07 I J 0.13 0.65 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.06 −0.05 N 0.10 P 1.4 Q 0.125±0.075 R +7° 3° −3° S 1.7 MAX. S100GF-65-8ET-1 Data Sheet M16024EJ5V0DS 19 µPD44321182, 44321362 Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the µPD44321182 and µPD44321362. Types of Surface Mount Devices µPD44321182GF : 100-pin PLASTIC LQFP (14 x 20) µPD44321362GF : 100-pin PLASTIC LQFP (14 x 20) 20 Data Sheet M16024EJ5V0DS µPD44321182, 44321362 Revision History Edition/ Date 5th edition/ Page Type of This Previous edition edition Throughout Deletion p.12 p.12 Description (Previous edition → This edition) revision Throughout Modification Apr. 2005 Location − Preliminary Data Sheet → Data Sheet − -A60, -A50Y, -A60Y Modification Recommended DC VIH (MIN.) : 1.7 V → 2.0 V Operating Conditions (1/2) Data Sheet M16024EJ5V0DS 21 µPD44321182, 44321362 [MEMO] 22 Data Sheet M16024EJ5V0DS µPD44321182, 44321362 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet M16024EJ5V0DS 23 µPD44321182, 44321362 ZEROSB is a trademark of NEC Electronics Corporation. • The information in this document is current as of April, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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