DATA SHEET MOS INTEGRATED CIRCUIT μPD43257B 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT Description The μPD43257B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery backup is available. And the μPD43257B has two chip enable pins (/CE1, CE2) to extend the capacity. The μPD43257B is packed in 28-pin PLASTIC DIP and 28-pin PLASTIC SOP. Features • 32,768 words by 8 bits organization • Fast access time: 70, 85 ns (MAX.) • Low VCC data retention: 2.0 V (MIN.) • Two Chip Enable inputs: /CE1, CE2 Part number Access time ns (MAX.) μPD43257B-xxL 70, 85 μPD43257B-xxLL Operating supply Operating ambient Supply current voltage temperature At operating At standby At data retention V °C mA (MAX.) μA (MAX.) μA (MAX.) Note 4.5 to 5.5 0 to 70 45 50 3 45 15 2 Note TA ≤ 40 °C, VCC = 3.0 V The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M10693EJ9V0DS00 (9th edition) Date Published June 2006 NS CP (K) Printed in Japan 1992 μPD43257B Ordering Information Part number Package Access time Supply current μA (MAX.) At standby 50 3 L version 15 2 LL version 50 3 L version 15 2 LL version 50 3 L version 15 2 LL version 28-pin PLASTIC DIP 70 μPD43257BCZ-85L (15.24 mm (600)) 85 μPD43257BCZ-70LL 70 μPD43257BCZ-85LL 85 μPD43257BGU-70L 28-pin PLASTIC SOP 70 μPD43257BGU-85L (11.43 mm (450)) 85 μPD43257BGU-70LL 70 μPD43257BGU-85LL 85 μPD43257BGU-70L-A 28-pin PLASTIC SOP 70 μPD43257BGU-85L-A (11.43 mm (450)) 85 μPD43257BGU-70LL-A 70 μPD43257BGU-85LL-A 85 Note TA ≤ 40 °C, VCC = 3.0 V Remark 2 Note ns (MAX.) μPD43257BCZ-70L Products with -A at the end of the part number are lead-free products. Data Sheet M10693EJ9V0DS At data retention Remark μPD43257B Pin Configurations (Marking Side) /xxx indicates active low signal. 28-pin PLASTIC DIP (15.24 mm (600)) [ μPD43257BCZ-xxL ] [ μPD43257BCZ-xxLL ] A14 1 28 VCC A12 2 27 /WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 CE2 A2 8 21 A10 A1 9 20 /CE1 A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 A0 - A14 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1 : Chip Enable 1 CE2 : Chip Enable 2 /WE : Write Enable VCC : Power supply GND : Ground Remark Refer to Package Drawings for the 1-pin marking. Data Sheet M10693EJ9V0DS 3 μPD43257B 28-pin PLASTIC SOP (11.43 mm (450)) [ μPD43257BGU-xxL ] [ μPD43257BGU-xxLL ] [ μPD43257BGU-xxL-A ] [ μPD43257BGU-xxLL-A ] A14 1 28 VCC A12 2 27 /WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 CE2 A2 8 21 A10 A1 9 20 /CE1 A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 A0 - A14 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1 : Chip Enable 1 CE2 : Chip Enable 2 /WE : Write Enable VCC : Power supply GND : Ground Remark Refer to Package Drawings for the 1-pin marking. 4 Data Sheet M10693EJ9V0DS μPD43257B Block Diagram A0 Address buffer A14 Row decoder I/O1 Input data controller I/O8 Memory cell array 262,144 bits Sense amplifier / Switching circuit Output data controller Column decoder Address buffer /CE1 CE2 /WE VCC GND Truth Table /CE1 CE2 /WE Mode I/O Supply current H × × Not selected High impedance ISB × L × L H H Read DOUT ICCA L H L Write DIN Remark × : VIH or VIL Data Sheet M10693EJ9V0DS 5 μPD43257B Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol Condition Rating VCC –0.5 –0.5 Note Note Unit to +7.0 V to VCC + 0.5 V Input / Output voltage VT Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width : 50 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 5.0 5.5 V VCC+0.5 V +0.8 V 70 °C MAX. Unit Supply voltage VCC 4.5 High level input voltage VIH 2.2 Low level input voltage VIL –0.3 Operating ambient temperature TA 0 Note Note –3.0 V (MIN.) (Pulse width: 50 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test conditions MIN. TYP. Input capacitance CIN VIN = 0 V 5 pF Input / Output capacitance CI/O VI/O = 0 V 8 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. 6 Data Sheet M10693EJ9V0DS μPD43257B DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol μPD43257B-xxL Test condition MIN. Input leakage TYP. μPD43257B-xxLL MAX. MIN. TYP. Unit MAX. ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 μA ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 –1.0 +1.0 μA mA current I/O leakage current CE2 = VIL or /WE = VIL Operating ICCA1 supply current /CE1 = VIL, CE2 = VIH, μPD43257B-70 45 45 Minimum cycle time, II/O = 0 mA μPD43257B-85 45 45 ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA 10 10 ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle = 1 MHz, 10 10 3 3 mA μA II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby ISB /CE1 = VIH or CE2 = VIL, supply current ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 1.0 50 0.5 15 ISB2 CE2 ≤ 0.2 V 1.0 50 0.5 15 High level VOH1 IOH = –1.0 mA 2.4 2.4 output voltage VOH2 IOH = –0.1 mA VCC–0.5 VCC–0.5 Low level VOL IOL = 2.1 mA 0.4 V 0.4 V output voltage Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types and access time. Data Sheet M10693EJ9V0DS 7 μPD43257B AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ μPD43257B-70L, μPD43257B-85L, μPD43257B-70LL, μPD43257B-85LL ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V Test points 1.5 V 1.5 V 0.8 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics with notes should be measured with the output load shown in Figure 1 and Figure 2. Figure 1 Figure 2 (tAA, tCO1, tCO2, tOH) (tLZ1, tLZ2, tHZ1, tHZ2, tWHZ, tOW) +5 V +5 V 1.8 kΩ 1.8 kΩ I/O (Output) I/O (Output) 990 Ω 100 pF CL 990 Ω Remark CL includes capacitance of the probe and jig, and stray capacitance. 8 Data Sheet M10693EJ9V0DS 5 pF CL μPD43257B Read Cycle Parameter μPD43257B-70 Symbol MIN. MAX. 70 μPD43257B-85 MIN. Unit Condition MAX. Read cycle time tRC 85 ns Address access time tAA 70 85 ns /CE1 access time tCO1 70 85 ns CE2 access time tCO2 70 85 ns Output hold from address change tOH 10 10 ns /CE1 to output in low impedance tLZ1 10 10 ns CE2 to output in low impedance tLZ2 10 10 ns /CE1 to output in high impedance tHZ1 30 30 ns CE2 to output in high impedance tHZ2 30 30 ns Note 1 Note 2 Notes 1. See the output load shown in Figure 1. 2. See the output load shown in Figure 2. Remark These AC characteristics are in common regardless of package types and L, LL versions. Read Cycle Timing Chart tRC Address (Input) tAA tOH /CE1 (Input) tHZ1 tCO1 tLZ1 CE2 (Input) tCO2 tHZ2 tLZ2 I/O (Output) Remark High impedance Data out In read cycle, /WE should be fixed to high level. Data Sheet M10693EJ9V0DS 9 μPD43257B Write Cycle Parameter Symbol μPD43257B-70 MIN. MAX. μPD43257B-85 MIN. Unit MAX. Write cycle time tWC 70 85 ns /CE1 to end of write tCW1 50 70 ns CE2 to end of write tCW2 50 70 ns Address valid to end of write tAW 50 70 ns Address setup time tAS 0 0 ns Write pulse width tWP 55 65 ns Write recovery time tWR 0 0 ns Data valid to end of write tDW 30 35 ns Data hold time tDH 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 30 10 30 10 Note See the output load shown in Figure 2. Remark These AC characteristics are in common regardless of package types and L, LL versions. 10 Data Sheet M10693EJ9V0DS Condition ns ns Note μPD43257B Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance Data in tDH High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M10693EJ9V0DS 11 μPD43257B Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance Data in I/O (Input) tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remark 12 Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M10693EJ9V0DS μPD43257B Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M10693EJ9V0DS 13 μPD43257B Low VCC Data Retention Characteristics (TA = 0 to 70 °C) Parameter Symbol μPD43257B-xxL Test Condition MIN. Data retention VCCDR1 MAX. MIN. TYP. 2.0 5.5 2.0 5.5 2.0 5.5 2.0 5.5 Unit MAX. V CE2 ≥ VCC − 0.2 V supply voltage Data retention /CE1 ≥ VCC − 0.2 V, TYP. μPD43257B-xxLL VCCDR2 CE2 ≤ 0.2 V ICCDR1 VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, 0.5 20 Note1 0.5 20 Note1 0.5 7 Note2 0.5 7 Note2 μA CE2 ≥ VCC − 0.2 V supply current ICCDR2 Chip deselection VCC = 3.0 V, CE2 ≤ 0.2 V tCDR 0 0 ns tR 5 5 ms to data retention mode Operation recovery time Notes 1. 3 μA (TA ≤ 40 °C) 2. 2 μA (TA ≤ 40 °C), 1 μA (TA ≤ 25 °C) 14 Data Sheet M10693EJ9V0DS μPD43257B Data Retention Timing Chart (1) /CE1 Controlled tCDR Data retention mode tR VCC 4.5 V /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V. The other pins (Address, I/O, /WE) can be in high impedance state. (2) CE2 Controlled tCDR Data retention mode tR VCC 4.5 V VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE) can be in high impedance state. Data Sheet M10693EJ9V0DS 15 μPD43257B Package Drawings 28-PIN PLASTIC DIP (15.24 mm (600)) 28 15 1 14 A J K I L F D C N B R M M H G NOTES 1. Each lead centerline is located within 0.25 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel. ITEM MILLIMETERS A 38.10 MAX. B 2.54 MAX. C 2.54 (T.P.) D 0.50±0.10 F 1.2 MIN. G 3.6±0.3 H 0.51 MIN. I 4.31 MAX. J 5.72 MAX. K L 15.24 (T.P.) 13.2 M 0.25 +0.10 −0.05 N 0.25 R 0 ∼ 15° P28C-100-600A1-2 16 Data Sheet M10693EJ9V0DS μPD43257B 28-PIN PLASTIC SOP (11.43 mm (450)) 28 15 detail of lead end P 1 14 A F H G I J S C D M N M L S B K E NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 18.0 +0.6 −0.05 B 1.27 MAX. C 1.27 (T.P.) D 0.42 +0.08 −0.07 E 0.2±0.1 F 2.95 MAX. G 2.55±0.1 H 11.8±0.3 I J 8.4±0.1 1.7±0.2 K 0.22±0.05 L M 0.7±0.2 0.12 N 0.10 P 3° +7° −3° P28GU-50-450A-4 Data Sheet M10693EJ9V0DS 17 μPD43257B Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the μPD43257B. Types of Surface Mount Device μPD43257BGU-xxL : 28-pin PLASTIC SOP (11.43 mm (450)) μPD43257BGU-xxLL : 28-pin PLASTIC SOP (11.43 mm (450)) μPD43257BGU-xxL-A : 28-pin PLASTIC SOP (11.43 mm (450)) μPD43257BGU-xxLL-A : 28-pin PLASTIC SOP (11.43 mm (450)) Types of Through Hole Mount Device μPD43257BCZ-xxL : 28-pin PLASTIC DIP (15.24 mm (600)) μPD43257BCZ-xxLL : 28-pin PLASTIC DIP (15.24 mm (600)) Soldering process Wave soldering (only to leads) Soldering conditions Solder temperature : 260 °C or below, Flow time : 10 seconds or below Partial heating method Terminal temperature : 300 °C or below, Time : 3 seconds or below (Per one lead) Caution Do not jet molten solder on the surface of package. 18 Data Sheet M10693EJ9V0DS μPD43257B Revision History Edition/ Date 9th edition/ Page Type of This Previous edition edition p.1 p.1 Location (Previous edition → This edition) revision Deletion Description − Description of Version X has been deleted. Jun. 2006 Data Sheet M10693EJ9V0DS 19 μPD43257B [ MEMO ] 20 Data Sheet M10693EJ9V0DS μPD43257B [ MEMO ] Data Sheet M10693EJ9V0DS 21 μPD43257B [ MEMO ] 22 Data Sheet M10693EJ9V0DS μPD43257B NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet M10693EJ9V0DS 23 μPD43257B • The information in this document is current as of June, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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