NEC UPD703039GM

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
TM
V850/SV1
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703039, 703039Y, 703040, 703040Y, 703041, and 703041Y (collectively known as the V850/SV1) are
products in the low-power series of V850 FamilyTM products, which are NEC’s single-chip microcontrollers for realtime control.
The V850/SV1 employs the CPU core of the V850 Family, and has on-chip peripheral functions such as large
capacity ROM/RAM, a multi-function timer/counter, serial interface, A/D converter, DMA controller, PWM, and a
Vsync/Hsync separation circuit.
The V850/SV1 not only realizes the low power consumption necessary for applications such as camcorders, but
also extremely high cost performance.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SV1 User’s Manual Hardware
: U14462E
V850 Family User’s Manual Architecture : U10243E
FEATURES
{ 10-bit resolution A/D converter: 16 channels
{ Number of instructions: 74
{ Timer/counter
{ Minimum instruction execution time:
24-bit: 2 channels, 16-bit: 2 channels
62.5 ns (@ 16 MHz operation with main system clock)
8-bit: 8 channels
30.5 µs (@ 32.768 kHz operation with subsystem clock) { Watch timer: 1 channel
{ General-purpose registers: 32 bits × 32 registers
{ Watchdog timer: 1 channel
{ Instruction set (signed multiplication, saturation
{ DMA controller: 6 channels
operations, 32-bit shift instructions, bit manipulation
instructions, load/store instructions)
{ Interrupts and exceptions
Non-maskable interrupt: 2 sources
{ Memory space:
Maskable interrupt
16 MB linear address space
: µPD703039, 703040, 703041 (51 sources)
Memory block allocation function: 2 MB per block
: µPD703039Y, 703040Y, 703041Y (52 sources)
{ External bus: 16-bit multiplexed bus
{ Internal memory:
Software exception: 32 sources
Exception trap: 1 source
µPD703039, 703039Y
{ Serial interface (SIO)
(ROM: 256 KB, RAM: 8 KB)
Asynchronous serial interface (UART)
µPD703040, 703040Y
Clocked serial interface (CSI)
(ROM: 256 KB, RAM: 16 KB)
3-wire variable length serial interface (CSI4)
µPD703041, 703041Y
I2C bus interface (I2C) (µPD703039Y, 703040Y,
(ROM: 192 KB, RAM: 8 KB)
703041Y)
{ RTP: 8 bits × 2 channels or 4 bits × 4 channels
{ I/O lines Total: 151
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U13953EJ1V0DS00 (1st edition)
Date Published March 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
{ PWM output: 4 channels
{ Vsync/Hsync separation circuit
{ On-chip key return function
{ On-chip clock generator
{ Power saving function: HALT/IDLE/STOP modes
{ ROM correction: 4 points changeable
{ Package: 176-pin plastic LQFP (24 × 24 mm)
APPLICATIONS
{ System/servo/camera control of camcorders
{ Portable cameras such as digital still cameras
{ Cellular phones, portable information terminals, etc.
ORDERING INFORMATION
Part Number
Package
µPD703039GM-×××-UEU
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
µPD703039YGM-×××-UEU
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
µPD703040GM-×××-UEU
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
µPD703040YGM-×××-UEU
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
µPD703041GM-×××-UEU
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
µPD703041YGM-×××-UEU
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
Remark ××× indicates ROM code suffix.
DIFFERENCES BETWEEN V850/SV1 PRODUCTS
Internal ROM
µPD703039
256 KB (mask ROM)
Internal RAM
8 KB
µPD703039Y
16 KB
µPD703040Y
192 KB (mask ROM)
8 KB
None
None
None
Provided
256 KB (flash memory)
16 KB
µPD70F3040Y
2
None
Provided
µPD703041Y
µPD70F3040
VPP Pin
Provided
µPD703040
µPD703041
2
IC
None
Provided
Preliminary Data Sheet U13953EJ1V0DS00
Provided
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
PIN CONFIGURATION
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
µPD703039GM-×××-UEU
µPD703039YGM-×××-UEU
µPD703040GM-×××-UEU
µPD703040YGM-×××-UEU
µPD703041GM-×××-UEU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
P147
P146
P145/RTPTRG1
P144/TI9/INTTI9
P143/INTCP93
P142/INTCP92
P141/INTCP91
P140/INTCP90
P137/TO81
P136/TO80
P135/TCLR8/INTTCLR8
P134/TI8/INTTI8
P133/INTCP83
P132/INTCP82
P131/INTCP81
P130/INTCP80
VSS
VDD
P07/INTP6
P06/INTP5/RTPTRG0
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P157/RTP17
P156/RTP16
P194
P195
P196
P197
P170/KR0
P171/KR1
P172/KR2
P173/KR3
P174/KR4
P175/KR5
P176/KR6
P177/KR7
P160/PWM0
P161/PWM1
P162/PWM2
P163/PWM3
P164/CSYNCIN
P165/VSOUT
P166/HSOUT0
P167/HSOUT1
ICNote 1
RESET
XT1
XT2
VDD
X2
X1
VSS
P100/RTP00
P101/RTP01
P102/RTP02
P103/RTP03
P104/RTP04
P105/RTP05
P106/RTP06
P107/RTP07
VDD
VSS
P150/RTP10
P151/RTP11
P152/RTP12
P153/RTP13
P154/RTP14
P155/RTP15
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
P12/SCK0/SCL0Note 2
P13/SI1/RXD0
P14/SO1/TXD0
P15/SCK1/ASCK0
P20/SI2/SDA1Note 2
P21/SO2
P22/SCK2/SCL1Note 2
P23/SI3/RXD1
P24/SO3/TXD1
P25/SCK3/ASCK1
P26/TI2/TO2
P27/TI3/TO3
VDD
VSS
P30/TI000
P31/TI001
P32/TI010
P33/TI011
P34/TO0
P35/TO1
P36/TI4/TO4
P37/TI5/TO5
P120/SI4
P121/SO4
P122/SCK4
P123/CLO
P124/TI6/TO6
P125/TI7/TO7
P126/TI10/TO10
P127/TI11/TO11
P180
P181
P182
P183
P184
P185
P186
P187
VDD
VSS
P190
P191
P192
P193
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
P11/SO0
P10/SI0/SDA0Note 2
P113
P112
P111
P110
WAIT
CLKOUT
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BVSS
BVDD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P96/HLDRQ
P95/HLDAK
P94/ASTB
P93/DSTB/RD
P92/R/W/WRH
P91/UBEN
P90/LBEN/WRL
VSS
VDD
AVDD
AVSS
AVREF
µPD703041YGM-×××-UEU
Notes 1. Connect directly to VSS.
2. SCL0, SCL1, SDA0, and SDA1 are valid for the µPD703039Y, 703040Y, and 703041Y only.
Preliminary Data Sheet U13953EJ1V0DS00
3
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
PIN IDENTIFICATION
A16 to A21:
Address Bus
P110 to P113:
Port 11
AD0 to AD15:
Address/Data Bus
P120 to P127:
Port 12
ADTRG:
AD Trigger Input
P130 to P137:
Port 13
ANI0 to ANI15:
Analog Input
P140 to P147:
Port 14
ASCK0, ASCK1:
Asynchronous Serial Clock
P150 to P157:
Port 15
ASTB:
Address Strobe
P160 to P167:
Port 16
AVDD:
Analog Power Supply
P170 to P177:
Port 17
AVREF:
Analog Reference Voltage
P180 to P187:
Port 18
AVSS:
Analog Ground
P190 to P197:
Port 19
BVDD:
Bus Interface Power Supply
PWM0 to PWM3:
Pulse Width Modulation
BVSS:
Bus Interface Ground
RD:
Read
CLKOUT:
Clock Output
RESET:
Reset
CLO:
Clock Output (divided)
RTP00 to RTP07,:
Real-time Output Port
CSYNCIN:
Csync Input
RTP10 to RTP17
DSTB:
Data Strobe
RTPTRG0, RTPTRG1: RTP Trigger Input
HLDAK:
Hold Acknowledge
R/W:
Read/Write Status
HLDRQ:
Hold Request
RXD0, RXD1:
Receive Data
HSOUT0, HSOUT1: Hsync Output
SCK0 to SCK4:
Serial Clock
IC:
SCL0, SCL1:
Serial Clock
INTCP80 to INTPC83,: Interrupt Request from Peripherals
Internally Connected
SDA0, SDA1:
Serial Data
INTCP90 to INTCP93,
SI0 to SI4:
Serial Input
INTP0 to INTP6,
SO0 to SO4:
Serial Output
INTTCLR8,
TCLR8:
Timer Clear
INTTI8, INTTI9
TI000, TI001, TI010,: Timer Input
KR0 to KR7:
Key Return
TI011, TI2 to TI11
LBEN:
Lower Byte Enable
TO0 to TO7, TO80,:
NMI:
Non-Maskable Interrupt Request
TO81, TO10, TO11
P00 to P07:
Port 0
TXD0,TXD1:
P10 to P15:
Port 1
UBEN:
Upper Byte Enable
P20 to P27:
Port 2
VDD:
Power Supply
P30 to P37:
Port 3
VSOUT:
Vsync Output
P40 to P47:
Port 4
VSS:
Ground
P50 to P57:
Port 5
WAIT:
Wait
P60 to P65:
Port 6
WRH:
Write Strobe High Level Data
P70 to P77:
Port 7
WRL:
Write Strobe Low Level Data
P80 to P87:
Port 8
X1, X2:
Crystal for Main System Clock
P90 to P96:
Port 9
XT1, XT2:
Crystal for Subsystem Clock
P100 to P107:
Port 10
4
Preliminary Data Sheet U13953EJ1V0DS00
Timer Output
Transmit Data
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
INTERNAL BLOCK DIAGRAM
KR0 to KR7
CPU
PC
Note 1
32-bit barrel
shifter
Timer/counter
16-bit timers
: TM0, TM1
8-bit timers
: TM2 to TM7,
TM10, TM11
24-bit timers
: TM8, TM9
Note 2
Instruction
queue
Multiplier
16 × 16 → 32
System
register
RAM
BCU
ALU
General registers
32 bits × 32
HLDRQ
HLDAK
ASTB
DSTB/RD
R/W/WRH
UBEN
LBEN/WRL
WAIT
A16 to A21
AD0 to AD15
Vsync/Hsync
SIO
CSI0/I2C0Note 4
Ports
A/D
converter
CSI2/I2C1Note 4
CG
CSI1/UART0
CSI3/UART1
Variable
length CSI4
Watch timer
Key return function
Watchdog timer
DMAC: 6 ch
RTP
PWM0 to PWM3
ROM correction
AVDD
AVREF
AVSS
ANI0 to ANI15
ADTRG
SO0
SI0/SDA0Note 3
SCK0/SCL0Note 3
SO2
SI2/SDA1Note 3
SCK2/SCL1Note 3
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SI4
SCK4
ROM
INTC
P190 to P197
P180 to P187
P170 to P177
P160 to P167
P150 to P157
P140 to P147
P130 to P137
P120 to P127
P110 to P113
P100 to P107
P90 to P96
P80 to P87
P70 to P77
P60 to P65
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P15
P00 to P07
NMI
INTP0 to INTP6
INTCP80 to INTCP83,
INTCP90 to INTCP93
INTTCLR8
INTTI8, INTTI9
TI000, TI001,
TI010, TI011
TO0, TO1
TO80, TO81
TI8, TI9
TCLR8
TI2/TO2, TI3/TO3
TI4/TO4, TI5/TO5
TI6/TO6, TI7/TO7
TI10/TO10, TI11/TO11
CSYNCIN
HSOUT0, HSOUT1,
VSOUT
PWM
CLKOUT
CLO
X1
X2
XT1
XT2
RESET
VDD
VSS
BVDD
BVSS
IC
RTP00 to RTP07,
RTP10 to RTP17
RTPTRG0,
RTPTRG1
Notes 1. µPD703039, 703039Y, 703040, 703040Y: 256 KB
µPD703041, 703041Y: 192 KB
2. µPD703039, 703039Y, 703041, 703041Y: 8 KB
µPD703040, 703040Y: 16 KB
3. SDA0, SDA1, SCL0, and SCL1 are valid for the µPD703039Y, 703040Y, and 703041Y only.
2
4. The I C function is valid for the µPD703039Y, 703040Y, and 703041Y only.
Preliminary Data Sheet U13953EJ1V0DS00
5
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
CONTENTS
1.
PIN FUNCTIONS .................................................................................................................................. 7
1.1
Port Pins .................................................................................................................................................... 7
1.2
Non-Port Pins........................................................................................................................................... 11
1.3
Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins ....................... 14
2.
ELECTRICAL SPECIFICATIONS...................................................................................................... 18
3.
PACKAGE DRAWING ....................................................................................................................... 37
4.
RECOMMENDED SOLDERING CONDITIONS................................................................................ 38
6
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1. PIN FUNCTIONS
1.1 Port Pins
(1/4)
Pin Name
P00
I/O
PULL
I/O
Yes
P01
Function
Port 0
8-bit I/O port
Input/output mode can be specified in 1-bit units.
Alternate Function
NMI
INTP0
P02
INTP1
P03
INTP2
P04
INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG0
P07
INTP6
P10
I/O
Yes
P11
Port 1
6-bit I/O port
Input/output mode can be specified in 1-bit units.
SI0/SDA0
SO0
P12
SCK0/SCL0
P13
SI1/RXD0
P14
SO1/TXD0
P15
SCK1/ASCK0
P20
I/O
Yes
P21
Port 2
8-bit I/O port
Input/output mode can be specified in 1-bit units.
SI2/SDA1
SO2
P22
SCK2/SCL1
P23
SI3/RXD1
P24
SO3/TXD1
P25
SCK3/ASCK1
P26
TI2/TO2
P27
TI3/TO3
P30
I/O
Yes
P31
Port 3
8-bit I/O port
Input/output mode can be specified in 1-bit units.
TI000
TI001
P32
TI010
P33
TI011
P34
TO0
P35
TO1
P36
TI4/TO4
P37
TI5/TO5
P40
P41
I/O
No
Port 4
8-bit I/O port
Input/output mode can be specified in 1-bit units.
AD0
AD1
P42
AD2
P43
AD3
P44
AD4
Remark
PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
7
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(2/4)
Pin Name
P45
I/O
PULL
I/O
No
P46
Function
Port 4
8-bit I/O port
Input/output mode can be specified in 1-bit units.
I/O
No
P51
AD6
Port 5
8-bit I/O port
Input/output mode can be specified in 1-bit units.
AD8
AD9
P52
AD10
P53
AD11
P54
AD12
P55
AD13
P56
AD14
P57
AD15
P60
I/O
No
P61
Port 6
6-bit I/O port
Input/output mode can be specified in 1-bit units.
A16
A17
P62
A18
P63
A19
P64
A20
P65
A21
P70
Input
No
P71
Port 7
8-bit input port
ANI0
ANI1
P72
ANI2
P73
ANI3
P74
ANI4
P75
ANI5
P76
ANI6
P77
ANI7
P80
Input
No
P81
Port 8
8-bit input port
ANI8
ANI9
P82
ANI10
P83
ANI11
P84
ANI12
P85
ANI13
P86
ANI14
P87
ANI15
P90
P91
I/O
No
Port 9
7-bit I/O port
Input/output mode can be specified in 1-bit units.
LBEN/WRL
UBEN
P92
R/W/WRH
P93
DSTB/RD
Remark
8
AD5
AD7
P47
P50
Alternate Function
PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(3/4)
Pin Name
P94
I/O
PULL
I/O
No
P95
Function
Port 9
7-bit I/O port
Input/output mode can be specified in 1-bit units.
ASTB
HLDAK
HLDRQ
P96
P100
Alternate Function
I/O
Yes
P101
Port 10
8-bit I/O port
Input/output mode can be specified in 1-bit units.
RTP00
RTP01
P102
RTP02
P103
RTP03
P104
RTP04
P105
RTP05
P106
RTP06
P107
RTP07
P110
I/O
No
P111
Port 11
4-bit I/O port
Input/output mode can be specified in 1-bit units.
–
–
P112
–
P113
–
P120
I/O
No
P121
Port 12
8-bit I/O port
Input/output mode can be specified in 1-bit units.
SI4
SO4
P122
SCK4
P123
CLO
P124
TI6/TO6
P125
TI7/TO7
P126
TI10/TO10
P127
TI11/TO11
P130
I/O
No
P131
Port 13
8-bit I/O port
Input/output mode can be specified in 1-bit units.
INTCP80
INTCP81
P132
INTCP82
P133
INTCP83
P134
TI8/INTTI8
P135
TCLR8/INTTCLR8
P136
TO80
P137
TO81
P140
P141
I/O
No
Port 14
8-bit I/O port
Input/output mode can be specified in 1-bit units.
INTCP90
INTCP91
P142
INTCP92
P143
INTCP93
P144
TI9/INTTI9
P145
RTPTRG1
P146
–
P147
–
Remark
PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
9
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(4/4)
Pin Name
P150
I/O
PULL
I/O
No
P151
P152
Function
Port 15
8-bit I/O port
Input/output mode can be specified in 1-bit units.
Alternate Function
RTP10
RTP11
RTP12
P153
RTP13
P154
RTP14
P155
RTP15
P156
RTP16
P157
RTP17
P160
I/O
No
P161
P162
Port 16
8-bit I/O port
Input/output mode can be specified in 1-bit units.
PWM0
PWM1
PWM2
P163
PWM3
P164
CSYNCIN
P165
VSOUT
P166
HSOUT0
P167
HSOUT1
P170
I/O
Yes
P171
P172
Port 17
8-bit I/O port
Input/output mode can be specified in 1-bit units.
KR0
KR1
KR2
P173
KR3
P174
KR4
P175
KR5
P176
KR6
P177
KR7
P180
I/O
No
P181
P182
Port 18
8-bit I/O port
Input/output mode can be specified in 1-bit units.
–
–
–
P183
–
P184
–
P185
–
P186
–
P187
–
P190
P191
P192
I/O
No
Port 19
8-bit I/O port
Input/output mode can be specified in 1-bit units.
–
–
–
P193
–
P194
–
P195
–
P196
–
P197
–
Remark
10
PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1.2 Non-Port Pins
(1/3)
Pin Name
I/O
PULL
Function
A16 to A21
Output
No
Address bus 16 to 21
P60 to P65
AD0 to AD7
I/O
No
Address/data multiplexed bus 0 to 15
P40 to P47
AD8 to AD15
Alternate Function
P50 to P57
ADTRG
Input
Yes
A/D converter external trigger input
P05/INTP4
ANI0 to ANI7
Input
No
Analog input to A/D converter
P70 to P77
ANI8 to ANI15
Input
No
ASCK0
Input
Yes
P80 to P87
Baud rate clock input for UART0 and UART1
ASCK1
P15/SCK1
P25/SCK3
ASTB
Output
No
AVDD
–
–
Positive power supply for A/D converter and ports used for
alternate functions
–
AVREF
Input
–
Reference voltage input for A/D converter
–
AVSS
–
–
Ground potential for A/D converter and ports used for alternate
functions
–
BVDD
–
–
Positive power supply for bus interface and ports used for
alternate functions
–
BVSS
–
–
Ground potential for bus interface and ports used for alternate
functions
–
CLKOUT
Output
–
Internal system clock output
–
CLO
Output
No
CLO output signal
P123
Input
No
Csync signal input
P164
DSTB
Output
No
External data strobe signal output
P93/RD
HLDAK
Output
No
Bus hold acknowledge output
P95
HLDRQ
Input
No
Bus hold request input
P96
HSOUT0
Output
No
Hsync signal output before revision
P166
Hsync signal output after revision
P167
CSYNCIN
HSOUT1
IC
External address strobe signal output
P94
–
–
INTCP80 to
INTCP83
Input
No
External capture input for CC80 to CC83
P130 to P133
INTCP90 to
INTCP93
Input
No
External capture input for CP90 to CP93
P140 to P143
INTP0 to INTP3
Input
Yes
External interrupt request input (digital noise elimination)
P01 to P04
External interrupt request input (digital noise elimination)
P05/ADTRG
INTP4
Internal connection (connect directly to VSS)
INTP5
INTP6
Remark
–
P06/RTPTRG0
External interrupt request input (digital noise elimination
supporting remote controller)
P07
PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
11
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(2/3)
Pin Name
I/O
PULL
INTTCLR8
Input
No
INTTI8
Input
No
Function
Alternate Function
External interrupt request input (digital noise elimination)
P135/TCLR8
P134/TI8
INTTI9
P144/TI9
KR0 to KR7
Input
Yes
Key return input
P170 to P177
Output
No
Lower byte enable signal output for external data bus
P90/WRL
Input
Yes
Non-maskable interrupt request input
P00
PWM0 to PWM3
Output
No
Output of PWM channels 0 to 3
P160 to P163
RD
Output
No
Bus read strobe signal output
P93/DSTB
Input
–
Output
Yes
LBEN
NMI
RESET
RTP00 to RTP07
System reset input
–
P100 to P107
Real-time output port
RTP10 to RTP17
RTPTRG0
P150 to P157
Input
RTPTRG1
R/W
RXD0
Yes
P06
RTP external trigger input
No
P146
Output
No
External read/write status output
P92/WRH
Input
Yes
Serial receive data input for UART0 and UART1
P13/SI1
RXD1
SCK0
P23/SI3
I/O
Yes
Serial clock I/O for CSI0 to CSI3 (3-wire mode)
P12/SCL0
SCK1
P15/ASCK0
SCK2
P22/SCL1
SCK3
P25/ASCK1
SCK4
SCL0
No
I/O
Yes
SCL1
SDA0
I/O
Yes
SDA1
SI0
Input
Yes
Variable-length CSI4 serial clock I/O
2
P122
2
Serial clock I/O for I C0 and I C1
(µPD703039Y, 703040Y and 703041Y)
2
P12/SCK0
P22/SCK2
2
Serial transmit/receive data I/O for I C0 and I C1
(µPD703039Y, 703040Y and 703041Y)
P10/SI0
P20/SI2
Serial receive data input for CSI0 to CSI3 (3-wire mode)
P10/SDA0
SI1
P13/RXD0
SI2
P20/SDA1
SI3
P23/RXD1
SI4
SO0
Output
No
Variable-length CSI4 serial receive data input (3-wire mode)
P120
Yes
Serial transmit data output for CSI0 to CSI3
P11
SO1
P14/TXD0
SO2
P21
SO3
P24/TXD1
SO4
No
Variable-length CSI4 serial transmit data output
P121
TCLR8
Input
No
External clear input for TM8
P135/INTTCLR8
TI000
Input
Yes
External count clock input/external capture trigger input for TM0
P30
Remark
12
PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(3/3)
Pin Name
TI001
I/O
PULL
Function
Alternate Function
External capture trigger input for TM0
P31
TI010
External count clock input/external capture trigger input for TM1
P32
TI011
External capture trigger input for TM1
P33
TI2
External count clock input for TM2
P26/TO2
TI3
External count clock input for TM3
P27/TO3
TI4
External count clock input for TM4
P36/TO4/A15
TI5
External count clock input for TM5
P37/TO5
External count clock input for TM6
P124/TO6
TI7
External count clock input for TM7
P125/TO7
TI8
External count clock input for TM8
P134/INTTI8
TI9
External count clock input for TM9
P144/INTTI9
TI10
External count clock input for TM10
P126/TO10
TI11
External count clock input for TM11
P127/TO11
Pulse signal output for TM0
P34
TO1
Pulse signal output for TM1
P35
TO2
Pulse signal output for TM2
P26/TI2
TO3
Pulse signal output for TM3
P27/TI3
TO4
Pulse signal output for TM4
P36/TI4
TO5
Pulse signal output for TM5
P37/TI5
Pulse signal output for TM6
P124/TI6
TO7
Pulse signal output for TM7
P125/TI7
TO80
Pulse signal output 0 for TM8
P136
TO81
Pulse signal output 1 for TM8
P137
TO10
Pulse signal output for TM10
P126/TI10
TO11
Pulse signal output for TM11
P127/TI11
Input
TI6
TO0
No
Output
Yes
No
TO6
TXD0
Yes
Output
Yes
Serial transmit data output for UART0 and UART1
TXD1
UBEN
Output
No
–
–
Output
No
–
–
WAIT
Input
WRH
Output
VDD
VSOUT
VSS
X1
Input
X2
–
XT1
Input
XT2
–
Higher byte enable signal output for external data bus
P91
Positive power supply pin
Vsync signal output
–
P165
Ground potential
–
No
External WAIT signal input
–
No
Higher byte write strobe signal output for external data bus
P92/R/W
Lower byte write strobe signal output for external data bus
P90/LBEN
WRL
Remark
P14/SO1
P24/SO3
No
Resonator connection for main system clock
–
–
No
Resonator connection for subsystem clock
–
–
PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
13
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins
Table 1-1 shows the I/O circuit type of each pin and the recommended connection of unused pins.
For the input/output configuration of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (1/2)
Pin
Alternate Function
I/O Circuit
Type
5-W
P00
NMI
P01 to P04
INTP0 to INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG0
P07
INTP6
I/O Buffer
Power Supply
VDD
10-F
SO0
10-E
P12
SCK0/SCL0
10-F
P13
SI1/RXD0
5-W
P14
SO1/TXD0
10-E
P15
SCK1/ASCK0
10-F
P20
SI2/SDA1
10-F
P21
SO2
10-E
P22
SCK2/SCL1
10-F
P23
SI3/RXD1
5-W
P24
SO3/TXD1
10-E
P25
SCK3/ASCK1
10-F
P26, P27
TI2/TO2, TI3/TO3
5-W
P30, P31
TI000, TI001
5-W
P32, P33
TI010, TI011
P34, P35
TO0, TO1
5-A
P36
TI4/TO4
5-W
P37
TI5/TO5
P40 to P47
AD0 to AD7
5
BVDD
P50 to P57
AD8 to AD15
5
BVDD
P60 to P65
A16 to A21
5
BVDD
P70 to P77
ANI0 to ANI7
9
AVDD
P80 to P87
ANI8 to ANI15
9
AVDD
P90
LBEN/WRL
5
BVDD
UBEN
R/W/WRH
P93
DSTB/RD
P94
ASTB
P95
HLDAK
P96
HLDRQ
P100 to P107
RTP00 to RTP07
P110 to P113
P120
14
SI4
VDD
VDD
Input:
Output:
10-E
VDD
5
VDD
5-K
VDD
Independently connect to BVDD or BVSS
via a resistor
Leave open
Connect to AVSS
Input:
Output:
–
Independently connect to VDD or VSS
via a resistor
Leave open
VDD
SI0/SDA0
P11
P92
Input:
Output:
P10
P91
Recommended Connection Method
Input:
Output:
Preliminary Data Sheet U13953EJ1V0DS00
Independently connect to BVDD or BVSS
via a resistor
Leave open
Independently connect to VDD or VSS
via a resistor
Leave open
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (2/2)
Pin
Alternate Function
I/O Circuit
Type
P121
SO4
10-G
P122
SCK4
10-H
P123
CLO
5
P124
TI6/TO6
5-K
P125
TI7/TO7
P126
TI10/TO10
P127
TI11/TO11
P130 to P133
INTCP80 to INTCP83
TI8/INTTI8
P135
TCLR8/INTTCLR8
P136, P137
TO80, TO81
5
P140 to P143
INTCP90 to INTCP93
5-K
P144
TI9/INTTI9
P145
RTPTRG1
P146, P147
P150 to P157
–
RTP10 to RTP17
VDD
PWM0 to PWM3
5
5-K
P165
VSOUT
5
P166
HSOUT0
HSOUT1
VDD
VDD
CSYNCIN
KR0 to KR7
VDD
5
P164
P170 to P177
Output:
Independently connect to VDD or VSS
via a resistor
Leave open
5
P160 to P163
P167
Recommended Connection Method
Input:
VDD
5-K
P134
I/O Buffer
Power Supply
5-K
VDD
P180 to P187
–
5
VDD
P190 to P197
–
5
VDD
CLKOUT
–
4
BVDD
Leave open
WAIT
–
1
BVDD
Connect to VDD via a resistor
RESET
–
2
VDD
–
X1
–
–
VDD
–
X2
–
–
VDD
Leave open
XT1
–
–
VDD
Connect to VSS
XT2
–
–
VDD
Leave open
AVREF
–
–
–
Connect to AVSS
IC
–
–
–
Connect directly to VSS
VDD
–
–
–
VSS
–
–
–
–
–
AVDD
–
–
–
Connect to
AVSS
–
–
–
Connect to VSS
BVDD
–
–
–
Connect to VDD
BVSS
–
–
–
Connect to VSS
Preliminary Data Sheet U13953EJ1V0DS00
VDD
15
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Figure 1-1. Pin Input/Output Circuits (1/2)
Type 1
Type 5
VDD
VDD
Data
P-ch
P-ch
IN/OUT
IN
Output
disable
N-ch
N-ch
Input
enable
Type 2
Type 5-A
Pullup
enable
Data
VDD
P-ch
VDD
P-ch
IN
IN/OUT
Output
disable
Schmitt-triggered input with hysteresis characteristics
Type 4
Input
enable
Type 5-K
VDD
VDD
Data
N-ch
Data
P-ch
P-ch
IN/OUT
OUT
Output
disable
N-ch
Push-pull output that can be set for high impedance output
(both P-ch and N-ch are off)
16
Output
disable
Input
enable
Preliminary Data Sheet U13953EJ1V0DS00
N-ch
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Figure 1-1. Pin Input/Output Circuits (2/2)
Type 5-W
Type 10-F
VDD
Pullup
enable
Pullup
enable
P-ch
VDD
Data
Data
P-ch
VDD
P-ch
VDD
P-ch
IN/OUT
Output
disable
IN/OUT
Open
Output
disable
N-ch
Input
enable
N-ch
Input
enable
Type 9
Type 10-G
VDD
P-ch
IN
Data
N-ch
P-ch
Comparator
+
–
IN/OUT
Open drain
VREF (Threshold voltage)
Input enable
Type 10-E
N-ch
Output
disable
Input
enable
Type 10-H
VDD
VDD
Pullup
enable
Data
Data
P-ch
IN/OUT
P-ch
IN/OUT
Open
Output
disable
Input
enable
P-ch
VDD
Open drain
Output
disable
N-ch
N-ch
Input
enable
Preliminary Data Sheet U13953EJ1V0DS00
17
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
2.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Supply voltage
Input voltage
Symbol
Ratings
Unit
VDD
–0.5 to +4.6
V
AVDD
–0.5 to +4.6
V
BVDD
–0.5 to +4.6
V
AVSS
–0.5 to +0.5
V
BVSS
–0.5 to +0.5
VI1
VI2
Clock input voltage
Analog input voltage
Analog reference input voltage
Output current, low
Output current, high
Output voltage
VK
VIAN
AVREF
IOL
IOH
Conditions
Note 1 (VDD)
Note 2 (BVDD)
X1, XT1, VDD = 2.7 to 3.6 V
Note 3 (AVDD)
AVREF pin
V
Note 4
–0.5 to VDD + 0.5
Note 4
–0.5 to BVDD + 0.5
V
V
Note 4
–0.5 to VDD + 1.0
Note 4
V
Note 4
V
–0.5 to AVDD + 0.5
–0.5 to AVDD + 0.5
Per pin
4.0
mA
Total for P00 to P07, P150 to P157
25
mA
Total for P100 to P107, P160 to P167
25
mA
Total for P170 to P177, P190 to P197
25
mA
Total for P124 to P127, P180 to P187
25
mA
Total for P30 to P37, P120 to P123
25
mA
Total for P12 to P15, P20 to P27, P110 to
P113
25
mA
Total for P50 to P57, P60 to P65, CLKOUT
25
mA
Total for P40 to P47, P90 to P96
25
mA
Total for P130 to P137, P140 to P147
25
mA
Per pin
–4.0
mA
Total for P00 to P07, P150 to P157
–25
mA
Total for P100 to P107, P160 to P167
–25
mA
Total for P170 to P177, P190 to P197
–25
mA
Total for P124 to P127, P180 to P187
–25
mA
Total for P30 to P37, P120 to P123
–25
mA
Total for P12 to P15, P20 to P27, P110 to
P113
–25
mA
Total for P50 to P57, P60 to P65, CLKOUT
–25
mA
Total for P40 to P47, P90 to P96
–25
mA
Total for P130 to P137, P140 to P147
–25
mA
–0.5 to VDD + 0.5
V
–0.5 to BVDD + 0.5
V
VO1
Note 1 (VDD)
VO2
Note 2 (BVDD)
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Notes 1.
2.
18
Ports 0, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, RESET (includes alternate function pins)
Ports 4, 5, 6, 9, CLKOUT, WAIT (includes alternate function pins)
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3.
Ports 7, 8 (includes alternate function pins)
4.
Be sure not to exceed each absolute maximum rating (MAX.).
Cautions
1. Do not directly connect to each other output pins (or I/O pins) of IC products, and do not
connect them directly to VDD, VCC, or GND. However, open-drain pins and open-connector
pins can be directly connected to each other. Moreover, external circuits that implement a
timing that avoids conflict with the output of pins that go into high-impedance can be
directly connected.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Input capacitance
CI
I/O capacitance
CIO
Output capacitance
CO
Conditions
MIN.
TYP.
fC = 1 MHz
Unmeasured pins returned to 0 V
MAX.
Unit
15
pF
15
pF
15
pF
MAX.
Unit
16
MHz
Operating Conditions
(1) CPU Operation Frequency
Parameter
CPU operation frequency
Symbol
fCPU
Conditions
MIN.
@ main system clock operation
TYP.
0.5
@ subsystem clock operation
32.768
MHz
(2) Supply Voltage
Parameter
Supply voltage
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VDD
2.7
3.6
V
AVDD
2.7
3.6
V
BVDD
2.7
3.6
V
(3) Operation Frequency for Each Supply Voltage
Internal Operation Clock Frequency
Supply Voltage (VDD = AVDD = BVDD)
4 MHz ≤ fXX ≤ 16 MHz
2.7 to 3.6 V
fXT = 32.768 kHz
2.7 to 3.6 V
Preliminary Data Sheet U13953EJ1V0DS00
19
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Recommended Oscillator
(1) Main System Clock Oscillator (TA = −40 to +85°°C)
X2
Parameter
Symbol
Oscillation frequency
X1
Conditions
MIN.
fXX
TYP.
4
Oscillation stabilization
time
MAX.
Unit
16
MHz
19
After reset release
2 /fXX
s
After STOP mode release
Note
s
Note Values vary depending on the settings of the oscillation stabilization time selection register (OSTS).
Remarks 1. Place the oscillator as close as possible to X1 and X2.
2. Do not wire other signal lines within the broken lines.
3. For resonator selection and oscillation constants, customers are advised to either evaluate the
oscillation themselves, or apply to the resonator manufacturer for evaluation.
(2) Subsystem Clock Oscillator (TA = −40 to +85°°C)
XT1
Parameter
Oscillation frequency
Symbol
XT2
Conditions
fXT
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
Oscillation stabilization time
10
s
Remarks 1. Place the oscillator as close as possible to XT1 and XT2.
2. Do not wire other signal lines within the broken lines.
3. For resonator selection and oscillation constants, customers are advised to either evaluate the
oscillation themselves, or apply to the resonator manufacturer for evaluation.
20
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
DC Characteristics (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Input voltage, high
Input voltage, low
Output voltage, high
Output voltage, low
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
0.7BVDD
BVDD
V
VIH1
Pins in Note 1 , WAIT
VIH2
Pins in Note 2
0.7VDD
VDD
V
VIH3
Pins in Note 3, RESET
0.75VDD
VDD
V
VIH4
Pins in Note 4
0.7AVDD
AVDD
V
VIH5
X, XT1, XT2
0.8VDD
VDD
V
VIL1
Pins in Note 1 , WAIT
BVSS – 0.5
0.3BVDD
V
VIL2
Pins in Note 2
VSS – 0.5
0.3VDD
V
VIL3
Pins in Note 3, RESET
VSS – 0.5
0.3VDD
V
VIL4
Pins in Note 4
AVSS – 0.5
0.3AVDD
V
VIL5
X, XT1, XT2
VSS
0.2VDD
V
VOH1
Note 1, CLKOUT
IOH = –3 mA
0.8BVDD
V
VOH2
Notes 2, 3
IOH = –1 mA
0.8VDD
V
VOL1
Note 1, CLKOUT
IOL = 1.6 mA
0.4
V
VOL2
Notes 2, 3 (except
IOL = 1.6 mA
0.4
V
0.4
V
P10, 12, 20, 22)
Input leakage current, high
VOL3
P10, 12, 20, 22
IOL = 3 mA
ILIH1
VI = VDD = AVDD =
BVDD
Other than X1, XT1, XT2
5
µA
X1, XT1, XT2
20
µA
VI = 0 V
Other than X1, XT1, XT2
–5
µA
X1, XT1, XT2
–20
µA
ILIH2
Input leakage current, low
ILIL1
ILIL2
Output leakage current, high
ILOH
VO = VDD = AVDD = BVDD
5
µA
Output leakage current, low
ILOL
VO = 0 V
–5
µA
IDD1
Normal operation mode (fXX = 16 MHz)
25
55
mA
IDD2
HALT mode (fXX = 16 MHz)
14
30
mA
IDD3
IDLE mode (fXX = 16 MHz)
1.2
4
mA
IDD4
STOP mode (subsystem clock operation: fXT
= 32.768 kHz, watch timer operation)
10
70
µA
STOP mode (subsystem clock stopped)
1
60
µA
30
100
kΩ
Supply current
Note 5
Pull-up resistor
RL
10
Notes 1. Ports 4, 5, 6, 9 (includes alternate-function pins)
2. P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147,
P150 to P157, P160 to P163, P165 to P167, P180 to P187, P190 to P197 (includes alternate-function
pins)
3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124
to P127, P130 to P135, P140 to P145, P164, P170 to P177 (includes alternate-function pins)
4. Ports 7, 8 (includes alternate-function pins)
5. The typical values listed are those of at VDD = 3.3 V. The current that is consumed at output buffers is
not included.
Preliminary Data Sheet U13953EJ1V0DS00
21
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Data Retention Characteristics (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
1.8
MAX.
Unit
3.6
V
60
µA
Data retention voltage
VDDDR
STOP mode
Data retention current
IDDDR
VDDDR [V]
Supply voltage rising time
tRVD
200
µs
Supply voltage falling time
tFVD
200
µs
Supply voltage hold time
(from STOP mode setting)
tHVD
0
ms
STOP release signal input time
tDREL
0
ms
Data retention high-level input voltage
VIHDR
All input port
VIHn
VDDDR
V
Data retention low-level input voltage
VILDR
All input port
0
VILn
V
1
Remark n = 1 to 5
Setting STOP mode
tFVD
tRVD
VDD
tHVD
VDDDR
RESET
(input)
VIHDR
NMI, INTP0 to INTP3
(input)
VIHDR
STOP release interrupt (NMI, etc.)
(when STOP mode is released
at rising edge)
VILDR
Caution Be sure to shift to and return from STOP mode when VDD is 2.7 V or higher.
22
Preliminary Data Sheet U13953EJ1V0DS00
tDREL
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
AC Characteristics
AC Test Input Waveforms (VDD, BVDD, AVDD)
VDD
VIH
VIH
Test points
0V
VIL
VIL
AC Test Output Test Point (BVDD)
VOH
VOH
Test points
VOL
VOL
Load Conditions
DUT
(Device under test)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load
capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Preliminary Data Sheet U13953EJ1V0DS00
23
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Clock Timing
Operating Conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
X1 input cycle
Symbol
Condition
<1>
tCYX
XT1 input cycle
X1 input high-level width
tWXH
<2>
XT1 input high-level width
X1 input low-level width
tWXL
<3>
XT1 input low-level width
MIN.
MAX.
Unit
62.5
250
ns
28.6
31.2
µs
31.2
125
ns
14.3
15.6
µs
31.2
125
ns
14.3
15.6
µs
X1 input rise time
tXR
<4>
(<1> – <2> – <3>)/2
ns
X1 input fall time
tXF
<5>
(<1> – <2> – <3>)/2
ns
CLKOUT output cycle
tCYK
<6>
62.5 ns
CLKOUT high-level width
tWKH
<7>
0.4(T – 20)
ns
CLKOUT low-level width
tWKL
<8>
0.4(T – 20)
ns
CLKOUT rise time
tKR
<9>
10
ns
CLKOUT fall time
tKF
<10>
10
ns
31.2 µs
Remark T = tCYK
Clock Timing
<1>
<2>
<3>
X1, XT1 (input)
<4>
<5>
<6>
<7>
<8>
CLKOUT (output)
<9>
<10>
Timing of Pins Other Than X1 and CLKOUT Pins
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, Output Pin Load Capacitance: CL
= 50 pF)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Output rise time
tOR
20
ns
Output fall time
tOF
20
ns
24
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Bus Timing (CLKOUT Asynchronous)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Address setup time (to ASTB↓)
tSAST
<11>
0.5T – 20
ns
Address hold time (from ASTB↓)
tHSTA
<12>
0.5T – 15
ns
Address float from DSTB↓
tFDA
<13>
2
ns
Data input setup time from address
tDAID
<14>
(2 + n)T – 30
ns
Data input setup time from DSTB↓
tDDID
<15>
(1 + n)T – 30
ns
DSTB↓ delay time from ASTB↓
tDSTD
<16>
0.5T – 15
ns
Data input hold time (from DSTB↑)
tHDID
<17>
0
ns
Address output time from DSTB↑
tDDA
<18>
(1 + i)T – 15
ns
ASTB↑ delay time from DSTB↑
tDDST1
<19>
0.5T – 15
ns
ASTB↓ delay time from DSTB↑
tDDST2
<20>
(1.5 + i)T – 15
ns
DSTB low-level width
tWDL
<21>
(1 + n)T – 15
ns
ASTB high-level width
tWSTH
<22>
T – 15
ns
Data output time from DSTB↓
tDDOD
<23>
Data output setup time (to DSTB↑)
tSODD
<24>
(1 + n)T – 20
ns
Data output hold time (from DSTB↑)
tHDOD
<25>
T – 15
ns
WAIT setup time (to address)
tSAWT1
<26>
tSAWT2
<27>
tHAWT1
<28>
tHAWT2
<29>
tSSTWT1
<30>
tSSTWT2
<31>
tHSTWT1
<32>
tHSTWT2
HLDRQ high-level width
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
15
n≥1
n≥1
1.5T – 30
ns
(1.5 + n)T – 30
ns
(0.5 + n)T
ns
(1.5 + n)T
ns
n≥1
n≥1
ns
1.5T – 25
ns
(1.5 + n)T – 25
ns
nT + 5
ns
<33>
(1 + n)T + 5
ns
tWHQH
<34>
T + 10
ns
HLDAK low-level width
tWHAL
<35>
T – 15
ns
Bus output delay time from HLDAK↑
tDHAC
<36>
0
ns
HLDAK↓ delay time from HLDRQ↓
tDHQHA1
<37>
1.5T
(2n + 7.5)T + 25
ns
HLDAK↑ delay time from HLDRQ↑
tDHQHA2
<38>
0.5T
1.5T + 25
ns
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
Sampling timing changes when a programmable wait is inserted.
3.
i: Number of idle states inserted after the read cycle (0 or 1).
4.
The specifications described above are the values of when a clock of duty ratio 1:1 is input from X1.
Preliminary Data Sheet U13953EJ1V0DS00
25
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Bus Timing (CLKOUT Synchronous)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Address delay time from CLKOUT↑
tDKA
<39>
0
19
ns
Address float delay time from CLKOUT↑
tFKA
<40>
–12
7
ns
ASTB↓ delay time from CLKOUT↓
tDKST
<41>
–12
7
ns
DSTB↑ delay time from CLKOUT↑
tDKD
<42>
–5
14
ns
Data input setup time (to CLKOUT↑)
tSIDK
<43>
15
ns
Data input hold time (from CLKOUT↑)
tHKID
<44>
5
ns
Data output delay time from CLKOUT↑
tDKOD
<45>
WAIT setup time (to CLKOUT↓)
tSWTK
<46>
15
ns
WAIT hold time (from CLKOUT↓)
tHKWT
<47>
5
ns
HLDRQ setup time (to CLKOUT↓)
tSHQK
<48>
15
ns
HLDRQ hold time (from CLKOUT↓)
tHKHQ
<49>
5
ns
Address float delay time from CLKOUT↑
tDKF
<50>
19
ns
HLDAK delay time from CLKOUT↑
tDKHA
<51>
19
ns
Remark
26
19
ns
The specifications described above are the values of when a clock of duty ratio 1:1 is input from X1.
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<39>
A16 to A21 (output), Note
<14>
<43>
<44>
<40>
AD0 to AD15 (I/O)
Hi-Z
Address
Data
<41>
<12>
<11>
<41>
<17>
ASTB (output)
<22>
<42>
<16>
<19>
<13>
<15>
<42>
<18>
<20>
DSTB (output),
RD (output)
<30> <46>
<32>
<31>
<33>
<47>
<21>
<46>
<47>
WAIT (input)
<26>
<28>
<27>
<29>
Note R/W (output), UBEN (output), LBEN (output)
Remark WRL and WRH are high level.
Preliminary Data Sheet U13953EJ1V0DS00
27
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<39>
A16 to A21 (output), Note
<45>
AD0 to AD15 (I/O)
Address
Data
<41>
<41>
<12>
<11>
ASTB (output)
<22>
<19>
<42>
<16>
<23>
<42>
<24>
<25>
DSTB (output),
WRL (output),
WRH (output)
<30> <46>
<32>
<31>
<33>
<47>
<21>
<46>
<47>
WAIT (input)
<26>
<28>
<27>
<29>
Note R/W (output), UBEN (output), LBEN (output)
Remark RD is high level.
28
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Bus Hold
TH
TH
TH
TI
CLKOUT (output)
<48>
<48> <49>
<34>
HLDRQ (input)
<51>
<51>
<37>
<38>
HLDAK (output)
<50>
<35>
Hi-Z
A16 to A21 (output), Note
AD0 to AD15 (I/O)
<36>
Data
Hi-Z
Hi-Z
ASTB (output)
Hi-Z
DSTB (output), RD (output),
WRL (output), WRH (output)
Note R/W (output), UBEN (output), LBEN (output)
Preliminary Data Sheet U13953EJ1V0DS00
29
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Reset/Interrupt Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
RESET high-level width
tWRSH
<52>
500
ns
RESET low-level width
tWRSL
<53>
500
ns
NMI high-level width
tWNIH
<54>
500
ns
NMI low-level width
tWNIL
<55>
500
ns
INTPn high-level width
tWITH
<56>
500
ns
3T + 20
ns
3Tsmp + 20
ns
500
ns
3T + 20
ns
3Tsmp + 20
ns
n = 0 to 3, analog noise elimination
n = 4, 5, digital noise elimination
n = 6, digital noise elimination
INTPn low-level width
tWITL
<57>
n = 0 to 3, analog noise elimination
n = 4, 5, digital noise elimination
n = 6, digital noise elimination
Remarks 1. T = 1/fXX
2. Tsmp = Noise elimination sampling clock frequency
Reset
<52>
<53>
RESET (input)
Interrupt
<54>
<55>
<56>
<57>
NMI (input)
INTPn (input)
Remark n = 0 to 6
30
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
TIn Input Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
TIn0, TIn1 (n = 00, 01)
high-level width
Symbol
tTIH
Condition
MAX.
Note
2Tsam + 20
<58>
TIn (n = 2 to 7, 10, 11)
high-level width
TIn0, TIn1 (n = 00, 01)
low-level width
MIN.
3/fXX + 20
tTIL
Note
2Tsam + 20
<59>
TIn (n = 2 to 7, 10, 11)
low-level width
3/fXX + 20
Unit
ns
ns
ns
ns
Note Tsam can be selected by setting the PRMn1 and PRMn0 bits of prescaler mode registers n0, n1 (PRMn0,
PRMn1) (n = 0, 1).
TM0 (PRM00, PRM01 registers): Tsam = 2/fXX, 4/fXX, 16/fXX, 64/fXX, 256/fXX, 1/INTWTI period
TM1 (PRM10, PRM11 registers): Tsam = 2/fXX, 4/fXX, 16/fXX, 32/fXX, 128/fXX, 256/fXX
However, when the TIn0 valid edge is selected as the count clock, Tsam = 4/fXX (n = 0, 1).
<58>
<59>
TIn
Remark n = 000, 001, 010, 011, 10, 11, 2 to 7
Preliminary Data Sheet U13953EJ1V0DS00
31
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3-Wire SIO Timing
(1) Master Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle time
tKCY1
<60>
400
ns
SCKn high-level width
tKH1
<61>
140
ns
SCKn low-level width
tKL1
<62>
140
ns
SIn setup time (to SCKn↑)
tSIK1
<63>
50
ns
SIn hold time (from SCKn↓)
tKSI1
<64>
50
ns
SOn output delay time from SCKn↓
tKSO1
<65>
60
ns
MAX.
Unit
Remark n = 0 to 3
(2) Slave Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
SCKn cycle time
tKCY2
<60>
400
ns
SCKn high-level width
tKH2
<61>
140
ns
SCKn low-level width
tKL2
<62>
140
ns
SIn setup time (to SCKn↑)
tSIK2
<63>
50
ns
SIn hold time (from SCKn↓)
tKSI2
<64>
50
ns
SOn output delay time from SCKn↓
tKSO2
<65>
60
Remark n = 0 to 3
<60>
<61>
SCKn (I/O)
<62>
<63>
SIn (input)
<65>
SOn (output)
Remark n = 0 to 3
32
Preliminary Data Sheet U13953EJ1V0DS00
<64>
ns
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3-Wire Variable-Length CSI Timing
(1) Master Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCK4 cycle time
tKCY1
<66>
400
ns
SCK4 high-level width
tKH1
<67>
140
ns
SCK4 low-level width
tKL1
<68>
140
ns
SI4 setup time (to SCK4↑)
tSIK1
<69>
50
ns
SI4 hold time (from SCK4↑)
tKSI1
<70>
50
ns
SO4 output delay time from SCK4↓
tKSO1
<71>
60
ns
MAX.
Unit
(2) Slave Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
SCK4 cycle time
tKCY2
<66>
400
ns
SCK4 high-level width
tKH2
<67>
140
ns
SCK4 low-level width
tKL2
<68>
140
ns
SI4 setup time (to SCK4↑)
tSIK2
<69>
50
ns
SI4 hold time (from SCK4↑)
tKSI2
<70>
50
ns
SO4 output delay time from SCK4↓
tKSO2
<71>
60
ns
<66>
<67>
SCK4 (I/O)
<68>
<69>
<70>
SI4 (input)
<71>
SO4 (output)
Preliminary Data Sheet U13953EJ1V0DS00
33
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
UART Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ASCKn cycle time
tKCY13
<72>
200
ns
ASCKn high-level width
tKH13
<73>
80
ns
ASCKn low-level width
tKL13
<74>
80
ns
Remark n = 0, 1
<72>
<73>
<74>
ASCKn (input)
Remark n = 0, 1
34
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
I C Bus Mode (Only for µPD703039Y, 703040Y, and 703041Y)
2
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Standard Mode
High-Speed Mode
Unit
MIN.
MAX.
MIN.
MAX.
0
100
0
400
kHz
SCLn clock frequency
fCLK
Bus free time
(between stop and start conditions)
tBUF
<75>
4.7
–
1.3
–
µs
Hold time
tHD : STA
<76>
4.0
–
0.6
–
µs
SCLn clock low-level width
tLOW
<77>
4.7
–
1.3
–
µs
SCLn clock high-level width
tHIGH
<78>
4.0
–
0.6
–
µs
Setup time of start/restart conditions
tSU : STA
<79>
4.7
–
0.6
–
µs
CBUS-compatible master tHD : DAT
<80>
5.0
–
–
–
µs
Note 1
Data hold
time
Note 2
2
0
I C mode
Data setup time
tSU : DAT
Rising time of SDAn and SCLn signals
tR
<81>
<82>
Note 2
Note 4
100
–
–
1000
0.9
0
–
250
Note 3
µs
–
ns
Note 5
300
ns
Note 5
300
ns
20 + 0.1Cb
20 + 0.1Cb
Falling time of SDAn and SCLn signals
tF
<83>
–
300
Setup time of stop condition
tSU : STO
<84>
4.0
–
0.6
–
µs
Pulse width of spike suppressed by
input filter
tSP
<85>
–
–
0
50
ns
Load capacitance of bus lines
Cb
–
400
–
400
pF
Notes 1. The first clock pulse in the start condition is generated after the hold time.
2. The system must internally provide at least 300 ns hold time for the SDAn signal (at VIHmin. of the SCLn
signal) in order to fill the undefined area that appears at the SCLn falling edge.
3. If the system does not extend the low hold time (tLOW), it is required to satisfy only the maximum data
hold time (tHD: DAT).
2
2
4. The high-speed I C bus is available in the standard mode I C bus system. In this case, following
conditions should be satisfied.
• When the system does not extend the low-state hold time of the SCLn signal
tSU: DAT ≥ 250 ns
• When the system extends the low-state hold time of the SCLn signal
Before the SCLn line is released (tRmax. + tSU:
DAT
= 1000 + 250 = 1250 ns: Standard mode I2C bus
specification), send the next data bit to the SDAn line.
5. Cb: Total capacitance of one bus line (Unit: pF)
Remark n = 0, 1
Preliminary Data Sheet U13953EJ1V0DS00
35
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
I C Bus Mode (Only for µPD703039Y, 703040Y, and 703041Y)
2
<77>
<82>
SCLn
<78>
<80>
<76>
<83>
<84>
<85>
<79>
<76>
<81>
SDAn
<75>
Restart
condition
Stop
Start
condition condition
Stop
condition
Remark n = 0, 1
A/D Converter (TA = –40 to +85°C, VDD = AVDD = AVREF = 2.7 to 3.6 V, AVSS = VSS = 0 V, Output Pin Load
Capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
Resolution
MIN.
TYP.
MAX.
Unit
10
10
10
bit
±0.8
%FSR
100
µs
±0.4
%FSR
±0.4
%FSR
±4.0
LSB
±4.0
LSB
2.7
3.6
V
AVSS
AVREF
V
Note 1
Overall error
Conversion time
Zero-scale error
Full-scale error
tCONV
5
Note 1
Note 1
Integral linearity error
Note 2
Differential linearity error
Note 2
Analog reference voltage
AVREF
AVREF = AVDD
Analog input voltage
VIAN
AVREF current
AIREF
240
360
µA
Supply current
AIDD
1
3
mA
Notes 1. Excluding quantization error (±0.05%FSR)
2. Excluding quantization error (±0.5LSB)
Remark
LSB: Least Significant Bit
FSR: Full Scale Range
36
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3.
PACKAGE DRAWING
176-PIN PLASTIC LQFP (FINE PITCH) (24x24)
A
B
132
133
89
88
detail of lead end
S
P
C
T
D
R
L
U
Q
176
1
45
44
F
G
H
I
J
M
K
S
N
S
M
NOTE
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
26.0±0.2
B
24.0±0.2
C
24.0±0.2
D
26.0±0.2
F
1.25
G
H
1.25
0.22±0.05
I
0.08
J
0.5 (T.P.)
K
L
0.5
1.0±0.2
M
0.17 +0.03
−0.07
N
0.08
P
1.4
Q
0.1±0.05
R
3° +4°
−3°
S
1.5±0.1
S176GM-50-UEU
Preliminary Data Sheet U13953EJ1V0DS00
37
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
4.
RECOMMENDED SOLDERING CONDITIONS
The µPD703039, 703039Y, 703040, 703040Y, 703041, and 703041Y should be soldered and mounted under the
following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 4-1. Surface Mounting Type Soldering Conditions
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
×××-UEU:
×××
µPD703039GM-×××
×××-UEU: 176-pin plastic LQFP (fine pitch) (24 × 24 mm)
µPD703040GM-×××
×××
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher),
Note
Count: Twice or less, Exposure limit: 3 days (after that, prebake at 125°C for 10
Recommended
Condition Symbol
IR35-103-2
hours)
VPS
Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher),
Note
Count: Twice or less, Exposure limit: 3 days (after that, prebake at 125°C for 10
VP15-103-2
hours)
Partial heating
Pin temperature: 300°C Max., Time 3 sec. Max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Cautions 1. Do not use different soldering methods together (except for partial heating).
2. Soldering conditions for µPD703039Y, 703040Y, 703041, and 703041Y are undetermined.
38
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
[MEMO]
Preliminary Data Sheet U13953EJ1V0DS00
39
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
[MEMO]
40
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
[MEMO]
Preliminary Data Sheet U13953EJ1V0DS00
41
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
2
2
2
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C
2
system, provided that the system conforms to the I C Standard Specification as defined by Philips.
Related document
Reference document
µPD70F3040, 70F3040Y Data Sheet (U14622E)
Electrical Characteristics for Microcomputer (IEI-601)
Note
Note This document number is that of the Japanese version.
The documents indicated in this publication may include preliminary versions.
versions are not marked as such.
V850 Family and V850/SV1 are trademarks of NEC Corporation.
42
Preliminary Data Sheet U13953EJ1V0DS00
However, preliminary
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Preliminary Data Sheet U13953EJ1V0DS00
43
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8