DATA SHEET MOS INTEGRATED CIRCUIT µPD78P058F 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78P058F is an Electro Magnetic Interference (EMI) noise reduction version of the µPD78P058. The µPD78P058F is a member of the µPD78058F Subseries of the 78K/0 Series, in which the on-chip mask ROM of the µPD78058F is replaced with one-time programmable (OTP) ROM. Because this device can be programmed by users, it is suited for applications involving the small-scale production of many different products, and for rapid development and time-to-market of new products. Details are given in the following User’s Manuals. Be sure to read them before starting design. µPD78058F, 78058FY Subseries User’s Manual : U12068E 78K/0 Series User’s Manual Instructions : U12326E FEATURES • EMI noise reduction version (overall peak level reduced by 5 to 10 dB) • Pin compatible with mask ROM versions (except the VPP pin) • Internal PROM : 60 KbytesNote 1 Programmable once only (ideal for small-scale production) • Internal high-speed RAM : 1024 bytes • Internal expansion RAM : 1024 bytesNote 2 • Buffer RAM : 32 bytes • Operable in the same supply voltage range as mask ROM versions (VDD = 2.7 to 6.0 V) • One of the QTOPTM Microcontrollers Notes 1. The internal PROM capacity can be changed with the memory size switching register (IMS). 2. The internal expansion RAM capacity can be changed with the internal expansion RAM size switching register (IXS). Remarks 1. For the difference between PROM and mask ROM versions, see 1. DIFFERENCES BETWEEN µPD78P058F AND MASK ROM VERSIONS. 2. QTOP Microcontroller is the general name of the microcontrollers with on-chip one-time PROM that are totally supported by the NEC writing service (from writing to marking, screening and testing). The information in this document is subject to change without notice. Document No. U11796EJ2V0DS00 (2nd edition) Date Published September 1997 N Printed in Japan The mark shows major revised points. © 1996 µPD78P058F ORDERING INFORMATION Part Number Package Internal ROM µPD78P058FGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) One-time PROM µPD78P058FGC-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) One-time PROM Caution The µPD78P058FGC contains two types of packages (see 8. PACKAGE DRAWINGS). For the packages which can be supplied, consult your local NEC sales representative. 2 µPD78P058F 78K/0 SERIES PRODUCT DEVELOPMENT These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin µPD78075B µ PD78075BY 100-pin µPD78078 µPD78078Y A timer was added to the µ PD78054, and the external interface function was enhanced. 100-pin µPD78070A µPD78070AY ROM-less versions of the µ PD78078. 80-pin µPD780058 µPD780018AY µPD780058YNote Serial I/O of the µ PD78078Y was enhanced, and only selected functions are provided. Serial I/O of the µ PD78054 was enhanced, EMI noise reduction version. 80-pin 80-pin µPD78058F µPD78054 µPD78058FY µPD78054Y EMI noise reduction version of the µ PD78054. UART and D/A converter were added to the µPD78014, and I/O was enhanced. 64-pin µPD780034 µPD780034Y An A/D converter of the µ PD780024 was enhanced. 64-pin 64-pin µPD780024 µPD78014H µPD780024Y 100-pin EMI noise reduction version of the µ PD78078. Serial I/O of the µ PD78018F was enhanced, EMI noise reduction version. EMI noise reduction version of the µPD78018F. 64-pin µPD78018F µPD78018FY Low-voltage (1.8 V) operation versions of the µ PD78014 with several ROM and RAM capacities available. 64-pin 64-pin µPD78014 µPD780001 µPD78014Y An A/D converter and 16-bit timer were added to the µPD78002. An A/D converter was added to the µPD78002. 64-pin µPD78002 µPD78002Y Basic subseries for control. 42/44-pin µPD78083 On-chip UART, capable of operating at a low voltage (1.8 V). Inverter control 64-pin µPD780988 An inverter control, timer, and SIO of the µ PD780964 were enhanced, and ROM and RAM were expanded. 64-pin µPD780964 An A/D converter of the µPD780924 was enhanced. 64-pin µPD780924 On-chip inverter control circuit and UART, EMI noise reduction version. FIPTM drive 78K/0 Series 100-pin µPD780208 The I/O and FIP C/D of the µ PD78044F were enhanced, Display output total: 53 100-pin µ PD780228 The I/O and FIP C/D of the µ PD78044H were enhanced, Display output total: 48 80-pin µPD78044H N-ch open-drain input/output was added to the µ PD78044F, Display output total: 34 80-pin µPD78044F Basic subseries for driving FIP, Display output total: 34 LCD drive 100-pin µPD780308 100-pin µPD78064B 100-pin µPD78064 µPD780308Y SIO of the µPD78064 was enhanced, and ROM and RAM were expanded. EMI noise reduction version of the µ PD78064. µPD78064Y Basic subseries for driving LCDs, On-chip UART. IEBusTM supported 80-pin µPD78098B EMI noise reduction version of the µ PD78098. 80-pin µPD78098 The IEBus controller was added to the µ PD78054. Meter control 80-pin µPD780973 On-chip automobile meter driving controller/driver. LV 64-pin µPD78P0914 On-chip PWM output, LV digital code decoder, Hsync counter. Note Under planning 3 µPD78P058F The major functional differences among the subseries are shown below. Function Subseries Name Control Timer ROM Capacity 8-bit 16-bit Watch WDT A/D µPD78075B 32 K to 40 K µPD78078 8-bit 10-bit 8-bit 4ch 1ch 1ch 1ch 8ch A/D D/A – 2ch 3ch (UART: 1ch) VDD External I/O MIN. Expansion Value 88 1.8 V Available 48 K to 60 K µPD78070A – µPD780058 24 K to 60 K 61 2.7 V 2ch µPD78058F 48 K to 60 K µPD78054 Serial Interface 3ch (time-division UART: 1ch) 68 1.8 V 3ch (UART: 1ch) 69 2.7 V 3ch (UART: 1ch, time-division 3-wire: 1ch) 51 1.8 V 2ch 53 16 K to 60 K 2.0 V µPD780034 8 K to 32 K µPD780024 – 8ch 8ch – – µPD78014H µPD78018F 8 K to 60 K µPD78014 8 K to 32 K 2.7 V µPD780001 8 K µPD78002 – 8 K to 16 K µPD78083 Inverter control µPD780988 32 K to 60 K 3ch Note 1 µPD780964 8 K to 32 K – 1ch 1ch – – 8ch – 1ch 8ch – Note 2 µPD780208 32 K to 60 K 2ch 1ch 1ch µPD780228 48 K to 60 K 3ch – – µPD78044H 32 K to 48 K 2ch 1ch 1ch 1ch 8ch – 8ch – – µPD780308 48 K to 60 K 2ch – 3ch (UART: 2ch) 47 4.0 V Available 2.7 V 2ch 74 2.7 V 1ch 72 4.5 V – 1ch 1ch 1ch 8ch – – 3ch (time-division UART: 1ch) 57 2.0 V – 2ch (UART: 1ch) 16 K to 32 K IEBus µPD78098B 40 K to 60 K supported µPD78098 32 K to 60 K 2ch 1ch 1ch 1ch 8ch – 2ch 3ch (UART: 1ch) 69 2.7 V Available Meter control µPD780973 24 K to 32 K 3ch 1ch 1ch 1ch 5ch – – 2ch (UART: 1ch) 56 4.5 V LV µPD78P0914 32 K 6ch – – 1ch 8ch – – 2ch 54 4.5 V Available Notes 1. 16-bit timer : 2 channels 10-bit timer : 1 channel 2. 10-bit timer : 1 channel 4 Available 33 1.8 V 2ch µPD78064B 32 K µPD78064 53 68 2.7 V µPD78044F 16 K to 40 K LCD drive – 1ch (UART: 1ch) 2ch (UART: 2ch) µPD780924 FIP drive – 39 – µPD78P058F FUNCTION DESCRIPTION Item Internal memory Function • PROM • RAM High-speed RAM Expansion RAM Buffer RAM : 60 KbytesNote 1 : 1024 bytes : 1024 bytesNote 2 : 32 bytes Memory space 64 Kbytes General register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time Minimum instruction execution time is variable. When main system clock is selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0-MHz operation) When subsystem 122 µs (@ 32.768-kHz operation) clock is selected Instruction set • • • • I/O port Total • CMOS input • CMOS input/output • N-ch open-drain input/output A/D converter 8-bit resolution × 8 ch D/A converter 8-bit resolution × 2 ch Serial interface • 3-wire serial I/O, SBI, or 2-wire serial I/O mode selectable : 1 ch • 3-wire serial I/O mode (with on-chip max. 32-byte automatic transmit/receive function) : 1 ch • 3-wire serial I/O or UART mode selectable : 1 ch Timer • • • • Timer output 3 pins (14-bit PWM output: 1 pin) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and 5.0 MHz (@ 5.0-MHz operation with main system clock) 32.768 kHz (@ 32.768-kHz operation with subsystem clock) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz and 9.8 kHz (@ 5.0-MHz operation with main system clock) Vectored interrupt source 16-bit operation Multiply/divide (8-bit × 8-bit, 16-bit ÷ 8-bit) Bit manipulation (set, reset, test, Boolean operation) BCD adjust, etc. 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer Maskable Internal: 13, external: 7 Non-maskable Internal: 1 Software : : : : : : : : 1 2 1 1 69 2 63 4 ch ch ch ch 1 Test input Internal: 1, external: 1 Supply voltage VDD = 2.7 to 6.0 V Operating ambient temperature TA = –40 to +85°C Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Notes 1. The internal PROM capacity can be changed with the memory size switching register (IMS). 2. The internal expansion RAM capacity can be changed with the internal expansion RAM size switching register (IXS). 5 µPD78P058F PIN CONFIGURATIONS (Top View) (1) Normal operating mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µPD78P058FGC-3B9 P00/INTP0/TI00 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 VDD X2 X1 VPP XT2 XT1/P07 AVDD AVREF0 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 µPD78P058FGC-8BT P01/INTP1/TI01 • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P15/ANI5 1 60 RESET P16/ANI6 2 59 P127/RTP7 P17/ANI7 3 58 P126/RTP6 AVSS 4 57 P125/RTP5 P130/ANO0 5 56 P124/RTP4 P131/ANO1 6 55 P123/RTP3 AVREF1 7 54 P122/RTP2 P70/SI2/RXD 8 53 P121/RTP1 P71/SO2/TXD 9 52 P120/RTP0 P72/SCK2/ASCK 10 51 P37 P20/SI1 11 50 P36/BUZ P21/SO1 12 49 P35/PCL P22/SCK1 13 48 P34/TI2 42 P66/WAIT 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P65/WR P64/RD P63 19 P41/AD1 P62 P40/AD0 P61 P67/ASTB P60 43 P57/A15 18 VSS P27/SCK0 P56/A14 P30/TO0 P55/A13 44 P54/A12 17 P53/A11 P26/SO0/SB1 P51/A9 P31/TO1 P52/A10 45 P50/A8 16 P47/AD7 P25/SI0/SB0 P46/AD6 P32/TO2 P45/AD5 P33/TI1 46 P44/AD4 47 15 P43/AD3 14 P42/AD2 P23/STB P24/BUSY Cautions 1. Connect the VPP pin to VSS. 2. The AVDD pin functions as both an A/D converter power supply and a port power supply. When the µPD78P058F is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AVDD pin to another power supply which has the same potential as VDD. 3. The AVSS pin functions as both grounds of an A/D converter and D/A converter and of a port. When the µPD78P058F is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AVSS pin to a ground line other than VSS. 6 µPD78P058F A8 to A15 : Address Bus PCL : Programmable Clock AD0 to AD7 : Address/Data Bus RD : Read Strobe ANI0 to ANI7 : Analog Input RESET : Reset ANO0, ANO1 : Analog Output RTP0 to RTP7 : Real-Time Output Port ASCK : Asynchronous Serial Clock RXD : Receive Data ASTB : Address Strobe SB0, SB1 : Serial Bus AVDD : Analog Power Supply SCK0 to SCK2 : Serial Clock AVREF0, AVREF1 : Analog Reference Voltage SI0 to SI2 : Serial Input AVSS : Analog Ground SO0 to SO2 : Serial Output BUSY : Busy STB : Strobe BUZ : Buzzer Clock TI00, TI01 : Timer Input INTP0 to INTP6 : Interrupt from Peripherals TI1,TI2 : Timer Input P00 to P07 : Port 0 TO0 to TO2 : Timer Output P10 to P17 : Port 1 T XD : Transmit Data P20 to P27 : Port 2 VDD : Power Supply P30 to P37 : Port 3 VPP : Programming Power Supply P40 to P47 : Port 4 VSS : Ground P50 to P57 : Port 5 WAIT : Wait P60 to P67 : Port 6 WR : Write Strobe P70 to P72 : Port 7 X1, X2 : Crystal (Main System Clock) P120 to P127 : Port 12 XT1, XT2 : Crystal (Subsystem Clock) P130, P131 : Port 13 7 µPD78P058F (2) PROM programming mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µPD78P058FGC-3B9 1 (L) VSS (L) 60 RESET 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 D7 11 50 D6 12 49 D5 13 48 D4 14 47 D3 15 46 D2 16 45 D1 17 44 D0 (L) (L) CE OE (L) A15 A14 VSS A13 A12 A11 A10 A8 A16 A7 A6 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A5 A1 A4 42 A3 43 19 A2 18 A0 : Individually connect to VSS via a pull-down resistor. Cautions 1. (L) 8 A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 (L) VDD (L) PGM (L) VDD Open (L) VPP Open (L) VSS (L) µPD78P058FGC-8BT VDD • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) 2. VSS : Connect to GND. 3. RESET : Set to low level. 4. Open : No connection A0 to A16 : Address Bus RESET : Reset CE : Chip Enable VDD : Power Supply D0 to D7 : Data Bus VPP : Programming Power Supply OE : Output Enable VSS : Ground PGM : Program µPD78P058F BLOCK DIAGRAM TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01 to P06 P07 8-bit TIMER/ EVENT COUNTER 1 PORT1 P10 to P17 8-bit TIMER/ EVENT COUNTER 2 PORT2 P20 to P27 PORT3 P30 to P37 PORT4 P40 to P47 PORT5 P50 to P57 PORT6 P60 to P67 PORT7 P70 to P72 PORT12 P120 to P127 PORT13 P130, P131 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SERiAL INTERFACE 0 78K/0 CPU CORE PROM 60 K Bytes SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 SERIAL INTERFACE 1 BUSY/P24 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 ANI0/P10 to ANI7/P17 RAM 2080 Bytes SERIAL INTERFACE 2 A/D CONVERTER REAL-TIME OUTPUT PORT AVREF0 ANO0/P130, ANO1/P131 AVREF1 D/A CONVERTER INTP0/P00 to INTP6/P06 INTERRUPT CONTROL BUZ/P36 AD0/P40 to AD7/P47 A8/P50 to A15/P57 EXTERNAL ACCESS BUZZER OUTPUT CLOCK OUTPUT CONTROL RD/P64 WR/P65 WAIT/P66 ASTB/P67 SYSTEM CONTROL PCL/P35 RTP0/P120 to RTP7/P127 VDD VSS AVDD AVSS VPP RESET X1 X2 XT1/P07 XT2 9 µPD78P058F CONTENTS 1. DIFFERENCES BETWEEN µPD78P058F AND MASK ROM VERSIONS ..................................... 11 2. PIN FUNCTIONS ................................................................................................................................ 12 2.1 2.2 Pins in Normal Operating Mode ............................................................................................................ 12 Pins in PROM Programming Mode ....................................................................................................... 16 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins .................................. 17 3. MEMORY SIZE SWITCHING REGISTER (IMS) ............................................................................... 21 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ............................................. 22 5. PROM PROGRAMMING .................................................................................................................... 23 5.1 Operating Modes ..................................................................................................................................... 23 5.2 5.3 PROM Write Procedure .......................................................................................................................... 25 PROM Read Procedure .......................................................................................................................... 29 6. SCREENING OF ONE-TIME PROM VERSIONS ............................................................................. 30 7. ELECTRICAL SPECIFICATIONS ..................................................................................................... 31 8. PACKAGE DRAWINGS ..................................................................................................................... 63 9. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 65 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................. 67 APPENDIX B. RELATED DOCUMENTS ................................................................................................ 71 10 µPD78P058F 1. DIFFERENCES BETWEEN µPD78P058F AND MASK ROM VERSIONS The µPD78P058F is a single-chip microcontroller with an on-chip one-time PROM. Setting the memory size switching register (IMS) and internal expansion RAM size switching register (IXS) enables identical functions to mask ROM versions (µPD78056F and 78058F) except the functions of PROM specifications and of mask options for P60 to P63. Differences between the µPD78P058F and mask ROM versions are shown in Table 1-1. Table 1-1. Differences between µPD78P058F and Mask ROM Versions µPD78P058F Item Mask ROM Versions Internal ROM structure One-time PROM Mask ROM Internal ROM capacity 60 Kbytes µPD78056F : 48 Kbytes µPD78058F : 60 Kbytes Internal expansion RAM capacity 1024 bytes µPD78056F : None µPD78058F : 1024 bytes Change of internal ROM capacity by Can be changedNote memory size switching register (IMS) Cannot be changed Change of internal expansion RAM capacity by internal expansion RAM size switching register (IXS) Can be changedNote Cannot be changed IC pin None Provided VPP pin Provided None Pull-up resistor on-chip mask option of P60 to P63 pins None Provided Electrical specifications, recommended soldering conditions See each Data Sheet. Note The RESET input sets the internal PROM capacity and internal expansion RAM capacity to 60 Kbytes and 1024 bytes, respectively. Caution The PROM version and mask ROM version differ in noise tolerance and noise emission. When replacing a PROM version with a mask ROM version when switching from experimental production to mass production, make a thorough evaluation with a CS version (not ES version) of the mask ROM version. 11 µPD78P058F 2. PIN FUNCTIONS 2.1 Pins in Normal Operating Mode (1) Port pins (1/2) Pin Name Input/Output P00 Input P01 Input/output P02 P03 Function Port 0 8-bit input/output port After Reset Alternate Function Input only Input INTP0/TI00 Input/output is specifiable bit-wise. When used as the input port, it is possible to use an on-chip pull-up resistor by software. Input INTP1/TI01 INTP2 INTP3 P04 INTP4 P05 INTP5 P06 INTP6 P07 Note 1 Input XT1 P10 to P17 Input/output Input Port 1 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to use an on-chip pull-up resistor by software.Note 2 Input ANI0 to ANI7 P20 Input/output Port 2 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to use an on-chip pull-up resistor by software. Input SI1 P21 P22 Input only SO1 SCK1 P23 STB P24 BUSY P25 SI0/SB0 P26 SO0/SB1 P27 SCK0 P30 P31 P32 Input/output Port 3 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to use an on-chip pull-up resistor by software. Input TO0 TO1 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 — Notes 1. When the P07/XT1 pins are used as the input ports, set the processor clock control register (PCC) bit 6 (FRC) to 1, and be sure not to use the feedback resistor of the subsystem clock oscillation circuit. 2. When the P10/ANI0 to P17/ANI7 pins are used as the analog inputs for A/D converter, set port 1 to input mode. The on-chip pull-up resistors are automatically disabled. Caution For pins which also function as port pins, do not perform the following operations during A/D conversion. If these operations are performed, the total error ratings cannot be kept. <1> Rewrite the output latch while the pin is used as a port pin. <2> Change the output level of the pin used as an output pin, even if it is not used as a port pin. 12 µPD78P058F (1) Port pins (2/2) Pin Name Input/Output P40 to P47 Input/output P50 to P57 P60 After Reset Alternate Function Port 4 8-bit input/output port Input/output is specifiable as 8-bit unit. When used as the input port, it is possible to use an on-chip pull-up resistor by software. Set test input flag (KRIF) to 1 by falling edge detection. Input AD0 to AD7 Input/output Port 5 8-bit input/output port It is possible to directly drive LEDs. Input/output is specifiable bit-wise. When used as the input port, it is possible to use an on-chip pull-up resistor by software. Input A8 to A15 Input/output Port 6 8-bit input/output port Input/output is specifiable bit-wise. N-ch open-drain input/output port. It is possible to directly drive LEDs. Input — When used as the input port, it is possible to use an on-chip pull-up resistor by software. Input RD P61 Function P62 P63 P64 P65 WR P66 WAIT P67 ASTB P70 Input/output P71 P72 Port 7 3-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to use an on-chip pull-up resistor by software. Input SI2/RXD SO2/TXD SCK2/ASCK P120 to P127 Input/output Port 12 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to use an on-chip pull-up resistor by software. Input RTP0 to RTP7 P130, P131 Input/output Port 13 2-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to use an on-chip pull-up resistor by software. Input ANO0, ANO1 Caution For pins which also function as port pins, do not perform the following operations during A/D conversion. If these operations are performed, the total error ratings cannot be kept. <1> Rewrite the output latch while the pin is used as a port pin. <2> Change the output level of the pin used as an output pin, even if it is not used as a port pin. 13 µPD78P058F (2) Non-port pins (1/2) Pin Name Input/Output INTP0 Input INTP1 Function External interrupt request inputs, with specifiable valid edges (rising edge, falling edge, and both rising and falling edges) After Reset Input P00/TI00 P01/TI01 INTP2 P02 INTP3 P03 INTP4 P04 INTP5 P05 INTP6 SI0 P06 Input Serial data input of the serial interface Input SI1 P70/RXD Output Serial data output of the serial interface Input SO1 P71/TXD Input/output Serial data input/output of the serial interface Input SB1 SCK0 P26/SB1 P21 SO2 SB0 P25/SB0 P20 SI2 SO0 P25/SI0 P26/SO0 Input/output Serial clock input/output of the serial interface Input P27 SCK1 P22 SCK2 P72/ASCK STB Output Automatic transmitting/receiving strobe output of the serial interface Input P23 BUSY Input Automatic transmitting/receiving busy input of the serial interface Input P24 R XD Input Serial data input for asynchronous serial interface Input P70/SI2 TX D Output Serial data output for asynchronous serial interface Input P71/SO2 ASCK Input Serial clock input for asynchronous serial interface Input P72/SCK2 TI00 Input External count clock input to 16-bit timer (TM0) Input P00/INTP0 TI01 Capture trigger signal input to capture register (CR00) P01/INTP1 TI1 External count clock input to 8-bit timer (TM1) P33 TI2 External count clock input to 8-bit timer (TM2) P34 TO0 14 Alternate Function Output 16-bit timer (TM0) output (Can be used together with 14-bit PWM output.) Input P30 TO1 8-bit timer (TM1) output P31 TO2 8-bit timer (TM2) output P32 µPD78P058F (2) Non-port pins (2/2) Pin Name Input/Output PCL Output BUZ RTP0 to RTP7 Function After Reset Alternate Function Clock output (for trimming main system clock and subsystem clock) Input P35 Output Buzzer output Input P36 Output Real-time output port which outputs data in synchronization with trigger Input P120 to P127 Low-order address/data bus when expanding memory externally Input P40 to P47 AD0 to AD7 Input/output A8 to A15 Output High-order address bus when expanding memory externally Input P50 to P57 RD Output Strobe signal output for the external memory read operation Input P64 Strobe signal output for the external memory write operation Input P65 WR WAIT Input Wait insertion when accessing external memory Input P66 ASTB Output Strobe output to externally latches address information which is output to ports 4 and 5 for accessing external memory Input P67 ANI0 to ANI7 Input Analog input of A/D converter Input P10 to P17 ANO0, ANO1 Output Analog output of D/A converter Input P130, P131 AVREF0 Input Reference voltage input of A/D converter — — AVREF1 Input Reference voltage input of D/A converter — — AVDD — Analog power supply of A/D converter (shared with the port power supply) — — AVSS — Ground potential of A/D converter and D/A converter (shared with the port ground potential) — — RESET Input System reset input — — X1 Input Main system clock oscillation crystal connection X2 — XT1 Input Subsystem clock oscillation crystal connection — — — — Input P07 XT2 — — — VDD — Positive power supply (except for port) — — VPP — High-voltage applied during program write/verify. Connected to VSS in normal operating mode. — — VSS — Ground potential (except for port) — — Cautions 1. The AVDD pin functions as both an A/D converter power supply and a port power supply. When the µPD78P058F is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AVDD pin to another power supply which has the same potential as VDD. 2. The AVSS pin functions as both grounds of an A/D converter and D/A converter and of a port. When the µPD78P058F is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AVSS pin to a ground line other than VSS. 15 µPD78P058F 2.2 16 Pins in PROM Programming Mode Pin Name Input/Output Function RESET Input PROM programming mode setting When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, this chip is set in the PROM programming mode. VPP Input PROM programming mode setting and high-voltage applied during program write/ verification A0 to A16 Input Address bus D0 to D7 Input/output CE Input PROM enable input/program pulse input OE Input Read strobe input to PROM PGM Input Program/program inhibit input in PROM programming mode VDD — Positive power supply VSS — Ground potential Data bus µPD78P058F 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins Types of input/output circuits of the pins and recommended connection of unused pins are shown in Table 2-1. For the configuration of each type of input/output circuit, see Figure 2-1. Table 2-1. Pin Input/Output Circuit Type (1/2) Input/Output Circuit Type Input/Output P00/INTP0/TI00 2 Input P01/INTP1/TI01 8-D Input/output 16 Input P10/ANI0 to P17/ANI7 11-C Input/output P20/SI1 8-D P21/SO1 5-J P22/SCK1 8-D P23/STB 5-J P24/BUSY 8-D P25/SI0/SB0 10-C Pin Name Recommended Connection when Unused Connect to VSS. Independently connect to VSS through resistor. P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 Connect to VDD. Independently connect to VDD or VSS through resistor. P26/SO0/SB1 P27/SCK0 P30/TO0 5-J P31/TO1 P32/TO2 P33/TI1 8-D P34/TI2 P35/PCL 5-J P36/BUZ P37 P40/AD0 to P47/AD7 5-O Independently connect to VDD through resistor. 17 µPD78P058F Table 2-1. Pin Input/Output Circuit Type (2/2) Pin Name P50/A8 to P57/A15 P60 to P63 P64/RD Input/Output Circuit Type Input/Output Recommended Connection when Unused 5-J Input/output Independently connect to VDD or VSS through resistor. 13-H Independently connect to VDD through resistor. 5-J Independently connect to VDD or VSS through resistor. P65/WR P66/WAIT P67/ASTB P70/SI2/RxD 18 8-D P71/SO2/TxD 5-J P72/SCK2/ASCK 8-D P120/RTP0 to P127/RTP7 5-J P130/ANO0, P131/ANO1 12-B Independently connect to VSS through resistor. RESET 2 Input XT2 16 — AVREF0 — — Leave open. Connect to VSS. AVREF1 Connect to VDD. AVDD Connect to another power supply which has the same potential as VDD. AVSS Connect to another ground line which has the same potential as VSS. VPP Connect to VSS. µPD78P058F Figure 2-1. Pin Input/Output Circuits (1/2) Type 2 Type 8-D AVDD pullup enable P-ch AVDD IN data P-ch IN/OUT output disable N-ch Schmitt-Triggered Input with Hysteresis Characteristic Type 5-J AVSS Type 10-C AVDD pullup enable AVDD pullup enable P-ch P-ch AVDD data AVDD data P-ch IN/OUT output disable N-ch AVSS P-ch IN/OUT open drain output disable N-ch AVSS input enable Type 11-C Type 5-O AVDD AVDD pullup enable pullup enable P-ch P-ch AVDD data P-ch AVDD IN/OUT data P-ch IN/OUT output disable N-ch output disable P-ch Comparator N-ch AVSS AVSS + - VREF (Threshold Voltage) N-ch AVSS input enable 19 µPD78P058F Figure 2-1. Pin Input/Output Circuits (2/2) Type 12-B Type 16 AVDD pullup enable feedback cut-off P-ch P-ch AVDD data P-ch IN/OUT output disable N-ch AVSS input enable Analog P-ch Output Voltage N-ch XT1 AVSS Type 13-H IN/OUT data output disable N-ch AVSS AVDD RD P-ch Middle-High Voltage Input Buffer 20 XT2 µPD78P058F 3. MEMORY SIZE SWITCHING REGISTER (IMS) This is a register to disable use of part of internal memories by software. By setting this memory size switching register (IMS), it is possible to get the same memory mapping as that of a mask ROM version having different internal memories (ROM). The IMS register is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 3-1. Memory Size Switching Register Format Symbol IMS 7 6 5 4 3 2 1 0 Address After Reset R/W RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 FFF0H CFH R/W ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity 1 1 0 0 48 Kbytes 1 1 1 0 56 KbytesNote 1 1 1 1 60 Kbytes Others Setting prohibited RAM2 RAM1 RAM0 1 1 0 Others Selection of Internal High-Speed RAM Capacity 1024 bytes Setting prohibited Note Set the internal ROM capacity to 56 Kbytes or less when external device expansion function is used. Table 3-1 shows the setting values of IMS which make the memory mapping the same as that of the mask ROM versions. Table 3-1. Memory Size Switching Register Setting Values Target Mask ROM Version IMS Setting Value µPD78056F CCH µPD78058F CFH 21 µPD78P058F 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) This is a register to set the internal expansion RAM capacity by software. By setting this internal expansion RAM size switching register (IXS), it is possible to get the same memory mapping as that of a mask ROM version having different internal expansion RAM. The IXS register is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0AH. Figure 4-1. Internal Expansion RAM Size Switching Register Format Symbol 7 6 5 4 IXS 0 0 0 0 3 2 1 0 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Address After Reset R/W FFF4H 0AH W IXRAM3 IXRAM2 IXRAM1 IXRAM0 Selection of Internal Expansion RAM Capacity 1 1 0 0 0 byte 1 0 1 0 1024 bytes Others Setting prohibited Table 4-1 shows the setting values of IXS which make the memory mapping the same as that of the mask ROM versions. Table 4-1. Internal Expansion RAM Size Switching Register Setting Values Target Mask ROM Version IXS Setting Value µPD78056F 0CH µPD78058F 0AH Remark Even if a µPD78P058F program that includes "MOV IXS, #0CH" is implemented on the µPD78056F, its operation will not be affected. 22 µPD78P058F 5. PROM PROGRAMMING The µPD78P058F has an on-chip 60-Kbyte PROM as a program memory. For programming, set the PROM programming mode by the VPP and RESET pins. For connecting unused pins, refer to PIN CONFIGURATIONS (Top View) (2) PROM programming mode. Caution Program writing should be performed in the address range 0000H to EFFFH (the last address, EFFFH, should be specified). Writing cannot be performed with a PROM programmer that cannot specify the write addresses. 5.1 Operating Modes When +5 V or +12.5 V is applied to the VPP pin and a low level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 5-1 when the CE, OE and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM. Table 5-1. Operating Modes of PROM Programming Pin RESET VPP VDD CE OE PGM D0 to D7 L +12.5 V +6.5 V H L H Data input Page write H H L High-impedance Byte write L H L Data input Program verify L L H Data output Program inhibit × H H High-impedance × L L L L H Data output Output disable L H × High-impedance Standby H × × High-impedance Operating Mode Page data latch Read +5 V +5 V Remark × : L or H 23 µPD78P058F (1) Read mode Read mode is set if CE = L, OE = L are set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, if OE = H is set. Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µPD78P058Fs are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data outputs become high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode. In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can be performed, if CE = L, OE = L are set. If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations should be executed repeatedly. (6) Byte write mode Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Then, program verification can be performed if OE = L is set. If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations should be executed repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if a write operation is performed correctly after the write. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin, and D0 to D7 pins of multiple µPD78P058Fs are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device which has the PGM pin driven high. 24 µPD78P058F 5.2 PROM Write Procedure Figure 5-1. Page Program Mode Flowchart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X=X+1 X = 10? 0.1-ms program pulse Verify 4 bytes Yes Fail Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass End of writing Defective product Remark G = Start address N = Program last address 25 µPD78P058F Figure 5-2. Page Program Mode Timing Page Data Latch Page Program Program Verify A2 to A16 A0, A1 D0 to D7 Data Input VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL 26 Data Output µPD78P058F Figure 5-3. Byte Program Mode Flowchart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 X=X+1 No X = 10? 0.1-ms program pulse Yes Address = Address + 1 Fail Verify Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass End of writing Defective product Remark G = Start address N = Program last address 27 µPD78P058F Figure 5-4. Byte Program Mode Timing Program Program Verify A0 to A16 Data Input D0 to D7 Data Output VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. VDD should be applied before VPP, and removed after VPP. 2. VPP must not exceed +13.5 V including overshoot. 3. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being applied to VPP. 28 µPD78P058F 5.3 PROM Read Procedure The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown below. (1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in PIN CONFIGURATIONS (Top View) (2) PROM programming mode. (2) Supply +5 V to the VDD and VPP pins. (3) Input address of read data into the A0 to A16 pins. (4) Read mode (5) Output data to D0 to D7 pins. The timings of the above steps (2) to (5) are shown in Figure 5-5. Figure 5-5. PROM Read Timings Address Input A0 to A16 CE (Input) OE (Input) D0 to D7 Hi-Z Data Output Hi-Z 29 µPD78P058F 6. SCREENING OF ONE-TIME PROM VERSIONS The one-time PROM version (µPD78P058FGC-3B9, 78P058FGC-8BT) cannot be tested completely by NEC before it is shipped, because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and performing high-temperature storage under the conditions below. Storage Temperature Storage Time 125°C 24 hours NEC offers for a fee one-time PROM writing, marking, screening and verify services for products designated as "QTOP Microcontrollers". For details, contact an NEC sales representative. 30 µPD78P058F 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Input voltage Symbol Test Conditions Rating Unit VDD –0.3 to +7.0 V VPP –0.3 to +13.5 V AVDD –0.3 to VDD + 0.3 V AVREF0 –0.3 to VDD + 0.3 V AVREF1 –0.3 to VDD + 0.3 V AVSS –0.3 to +0.3 V –0.3 to VDD + 0.3 V –0.3 to +16 V –0.3 to +13.5 V –0.3 to VDD + 0.3 V AVSS – 0.3 to AVREF0 + 0.3 V VI1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, X1, X2, XT2, RESET VI2 P60 to P63 N-ch open-drain VI3 A9 PROM programming mode Output voltage VO Analog input voltage VAN P10 to P17 Output current, high IOH Per pin –10 mA Total for P01 to P06, P30 to P37, P56, P57, P60 to P67, P120 to P127 –15 mA Total for P10 to P17, P20 to P27, P40 to P47, P50 to P55, P70 to P72, P130, P131 –15 mA Per pin peak value 30 mA r.m.s. value 15 mA peak value 100 mA r.m.s. value 70 mA peak value 100 mA r.m.s. value 70 mA Total for P10 to P17, P20 to P27, P40 to P47, P70 to P72, peak value 50 mA P130, P131 r.m.s. value 20 mA Total for P01 to P06, P30 to P37, P64 to P67, P120 to P127 peak value 50 mA r.m.s. value 20 mA Output current, low IOL Note Analog input pins Total for P50 to P55 Total for P56, P57, P60 to P63 Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note r.m.s. values should be calculated as follows: [r.m.s. value] = [peak value] x √ Duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics. 31 µPD78P058F Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.7 to 6.0 V) Recommended Circuit Resonator Ceramic resonator X2 X1 C2 Crystal resonator X2 VPP C1 X1 C2 VPP C1 Parameter Test Conditions Oscillation frequency (fX)Note 1 VDD = Oscillation voltage range Oscillation stabilization timeNote 2 After VDD has reached MIN. of oscillation voltage range Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 MIN. TYP. MAX. Unit 1.0 1.0 VDD = 4.5 to 6.0 V 5.0 MHz 4 ms 5.0 MHz 10 ms 30 External clock X2 µ PD74HCU04 X1 X1 input frequency (fX)Note 1 1.0 5.0 MHz X1 input high-/low-level width (tXH/tXL) 85 500 ns Notes 1. Only the oscillator characteristics are shown. See the AC characteristics for instruction execution times. 2. This is the time required for oscillation to stabilize after a reset or STOP mode release. Cautions 1. When the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by broken lines to prevent the influence of wiring capacitance, etc. • The wiring should be kept as short as possible. • No other signal lines should be crossed. • Keep away from lines carrying a high fluctuating current. • The oscillator capacitor grounding point should always be at the same potential as VSS. • Do not connect to a ground pattern carrying a high current. • A signal should not be taken from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 32 µPD78P058F Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.7 to 6.0 V) Recommended Circuit Resonator Crystal resonator VPP XT2 XT1 Parameter Test Conditions Oscillation frequency (fXT)Note 1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s R1 C4 C3 Oscillation stabilization timeNote 2 VDD = 4.5 to 6.0 V 10 External clock XT2 XT1 XT1 input frequency (fXT)Note 1 32 100 kHz XT1 input high-/low-level width (tXTH/tXTL) 5 15 µs Notes 1. Only the oscillator characteristics are shown. See the AC characteristics for instruction execution times. 2. This is the time required for oscillation to stabilize after power (VDD) is turned on. Cautions 1. When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by broken lines to prevent the influence of wiring capacitance, etc. • The wiring should be kept as short as possible. • No other signal lines should be crossed. • Keep away from lines carrying a high fluctuating current. • The oscillator capacitor grounding point should always be at the same potential as VSS. • Do not connect to a ground pattern carrying a high current. • A signal should not be taken from the oscillator. 2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. 33 µPD78P058F Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz, Unmeasured pins returned to 0 V 15 pF Input/output capacitance CIO f = 1 MHz Unmeasured pins returned to 0 V P01 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 15 pF P60 to P63 20 pF Remark Unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics. 34 µPD78P058F DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 6.0 V) Parameter Symbol Input voltage, high VIH1 P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47, 0.7 VDD P50 to P57, P64 to P67, P71, P120 to P127, P130, P131 VDD V VIH2 P00 to P06, P20, P22, P24 to P27, P33, P34, P70, P72, RESET 0.8 VDD VDD V VIH3 P60 to P63 (N-ch open-drain) 0.7 VDD 15 V VIH4 X1, X2 VDD – 0.5 VDD V VIH5 XT1/P07, XT2 0.8 VDD VDD V 0.9 VDD VDD V Input voltage, low Output voltage, high Output voltage, low Test Conditions VDD = 4.5 to 6.0 V TYP. MAX. Unit VIL1 P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P64 to P67, P71, P120 to P127, P130, P131 0 0.3 VDD V VIL2 P00 to P06, P20, P22, P24 to P27, P33, P34, P70, P72, RESET 0 0.2 VDD V VIL3 P60 to P63 0 0.3 VDD V 0 0.2 VDD V 0 0.4 V 0 0.2 VDD V 0 0.1 VDD V VIL4 X1, X2 VIL5 XT1/P07, XT2 VOH VOL1 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V, IOH = – 1 mA VDD – 1.0 V IOH = –100 µA VDD – 0.5 V P50 to P57, P60 to P63 VDD = 4.5 to 6.0 V, IOL = 15 mA 2.0 V 0.4 V 0.2 VDD V 0.5 V P00 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P72, P120 to P127, P130, P131, RESET 3 µA X1, X2, XT1/P07, XT2 20 µA P60 to P63 80 µA P01 to P06, P10 to P17, P20 VDD = 4.5 to 6.0 V, to P27, P30 to P37, P40 to IOL = 1.6 mA P47, P64 to P67, P70 to P72, P120 to P127, P130, P131 Input leakage current, high MIN. VOL2 SB0, SB1, SCK0 VOL3 IOL = 400 µA ILIH1 VIN = VDD ILIH2 ILIH3 VIN = 15 V VDD = 4.5 to 6.0 V, N-ch open-drain at pull-up time (R = 1 kΩ) 0.4 Remark Unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics. 35 µPD78P058F DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 6.0 V) Parameter Input leakage current, low Symbol Test Conditions MIN. TYP. MAX. Unit P00 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, RESET –3 µA ILIL2 X1, X2, XT1/P07, XT2 –20 µA ILIL3 P60 to P63 –3Note µA ILIL1 VIN = 0 V ILOH VOUT = VDD 3 µA Output leakage current, low ILOL VOUT = 0 V –3 µA Software pull-up resistor R 90 kΩ 500 kΩ Output leakage current, high VIN = 0 V, P01 to P06, P10 VDD = 4.5 to 6.0 V to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 15 20 40 Note In P60 to P63, a –200-µA (MAX.) low-level input leakage current passes only during the 1.5-clock interval (no wait) when the read instruction to port 6 (P6) and port mode register 6 (PM6) is executed. Other than the 1.5clock interval, –3 µA (MAX.) is passed. Remark Unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics. 36 µPD78P058F DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 6.0 V) Parameter Symbol Supply currentNote 1 IDD1 Test Conditions TYP. MAX. Unit VDD = 5.0 V ±10%Note 5 5 15 mA VDD = 3.0 V ±10%Note 6 0.7 2.1 mA 5.0-MHz crystal oscillation operating VDD = 5.0 V ±10% Note 5 9.0 27.0 mA mode (fXX = 5.0 MHz)Note 3 VDD = 3.0 V ±10%Note 6 1.0 3.0 mA 5.0-MHz crystal oscillation HALT VDD = 5.0 V ±10% 1.4 4.2 mA VDD = 3.0 V ±10% 0.5 1.5 mA VDD = 5.0 V ±10% 1.6 4.8 mA VDD = 3.0 V ±10% 0.65 1.95 mA 5.0-MHz crystal oscillation operating mode (fXX = 2.5 MHz) IDD2 mode (fXX = 2.5 MHz) Note 2 Note 2 5.0-MHz crystal oscillation HALT mode (fXX = 5.0 MHz) IDD3 IDD4 Note 3 VDD = 5.0 V ±10% 135 270 µA crystal oscillation operating modeNote 4 VDD = 3.0 V ±10% 95 190 µA VDD = 5.0 V ±10% 25 55 µA VDD = 3.0 V ±10% 5 15 µA XT1 = VDD STOP mode Feedback resistor used VDD = 5.0 V ±10% 1 30 µA VDD = 3.0 V ±10% 0.5 10 µA XT1 = VDD STOP mode Feedback resistor not used VDD = 5.0 V ±10% 0.1 30 µA VDD = 3.0 V ±10% 0.05 10 µA 32.768-kHz 32.768-kHz crystal oscillation HALT mode IDD5 IDD6 MIN. Note 4 Notes 1. Passed through the VDD and AVDD pins. Does not include the current which is passed through the A/D converter, D/A converter, and on-chip pull-up resistor. 2. fXX = fX/2 operation (when the oscillation mode selection register (OSMS) is set to 00H) 3. fXX = fX operation (when OSMS is set to 01H) 4. When the main system clock is stopped 5. High-speed mode operation (when the processor clock control register (PCC) is set to 00H) 6. Low-speed mode operation (when PCC is set to 04H) Remarks 1. fXX : Main system clock frequency (fX or fX/2) 2. fX : Main system clock oscillation frequency 37 µPD78P058F AC Characteristics (1) Basic Operation (TA = –40 to +85°C, VDD = 2.7 to 6.0 V) Parameter Symbol Cycle time TCY (minimum instruction Test Conditions Operating on fXX = fX/2Note 1 main system clock fXX = fXNote 2 MIN. VDD = 4.5 to 6.0 V execution time) Operating on subsystem clock TYP. MAX. Unit 0.8 64 µs 0.4 32 µs 0.8 32 µs 125 µs 40 122 2/fsam + 0.1Note 3 µs tTIL00 2/fsam + 0.2Note 3 µs TI01 input tTIH01, 10 µs high-/low-level width tTIL01 TI00 input tTIH00, high-/low-level width TI1, TI2 input fTI1 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V frequency TI1, TI2 input tTIH1, high-/low-level width tTIL1 Interrupt input tINTH, high-/low-level width tINTL VDD = 4.5 to 6.0 V 4 MHz 0 275 kHz 100 ns µs 1.8 INTP0 Note 3 µs 2/fsam + 0.2Note 3 µs 10 µs 10 µs VDD = 4.5 to 6.0 V 2/fsam + 0.1 INTP1 to INTP6, KR0 to KR7 RESET low-level width 0 tRSL Notes 1. When oscillation mode selection register (OSMS) is set to 00H. 2. When OSMS is set to 01H. 3. fsam can be selected as fXX/2N, fXX/32, fXX/64, or fXX/128 (N = 0 to 4) by bits 0 and 1 (SCS0 and SCS1) of the sampling clock selection register (SCS). Remarks 38 1. fXX : Main system clock frequency (fX or fX/2) 2. fX : Main system clock oscillation frequency µPD78P058F TCY vs VDD (Main System Clock, fXX = fX/2) TCY vs VDD (Main System Clock, fXX = fX) 60 Cycle Time TCY [µ s] Cycle Time TCY [µ s] 60 10 Guaranteed Operation Range 2.0 10 Guaranteed Operation Range 2.0 1.0 1.0 0.5 0.4 0.5 0.4 0 1 2 3 4 5 Supply Voltage VDD [V] 6 0 1 2 3 4 5 6 Supply Voltage VDD [V] 39 µPD78P058F (2) Read/Write Operations (a) When MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 4.5 to 6.0 V) Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.85tCY – 50 ns Address setup time tADS 0.85tCY – 50 ns Address hold time tADH 50 ns Data input time from address tADD1 (2.85 + 2n)tCY – 80 ns tADD2 (4 + 2n)tCY – 100 ns tRDD1 (2 + 2n)tCY – 100 ns tRDD2 (2.85 + 2n)tCY – 100 ns Data input time from RD↓ Read data hold time tRDH 0 ns RD low-level width tRDL1 (2 + 2n)tCY – 60 ns tRDL2 (2.85 + 2n)tCY – 60 ns WAIT↓ input time from RD↓ WAIT↓ input time from WR↓ tRDWT1 0.85tCY – 50 ns tRDWT2 2tCY – 60 ns tWRWT 2tCY – 60 ns (2 + 2n)tCY ns WAIT low-level width tWTL (1.15 + 2n)tCY Write data setup time tWDS (2.85 + 2n)tCY – 100 ns Write data hold time tWDH 20 ns WR low-level width tWRL1 (2.85 + 2n)tCY – 60 ns RD↓ delay time from ASTB↓ tASTRD 25 ns WR↓ delay time from ASTB↓ tASTWR 0.85tCY + 20 ns ASTB↑delay time from RD↑ in external fetch tRDAST 0.85tCY – 10 1.15tCY + 20 ns Address hold time from RD↑ in external fetch tRDADH 0.85tCY – 50 1.15tCY + 50 ns Write data output time from RD↑ tRDWD 40 Write data output time from WR↓ tWRWD 0 50 ns Address hold time from WR↑ tWRADH 0.85t CY 1.15tCY + 40 ns RD↑ delay time from WAIT↑ tWTRD 1.15tCY + 40 3.15tCY + 40 ns WR↑ delay time from WAIT↑ tWTWR 1.15tCY + 30 3.15tCY + 30 ns Remarks 40 1. MCS: Bit 0 of the oscillation mode selection register (OSMS) 2. PCC2 to PCC0: Bit 2 to bit 0 of the processor clock control register (PCC) 3. tCY = TCY/4 4. n indicates the number of waits. ns µPD78P058F (b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 2.7 to 6.0 V) Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width tASTH tCY – 80 ns Address setup time tADS tCY – 80 ns Address hold time tADH 0.4tCY – 10 ns Data input time from address tADD1 (3 + 2n)tCY – 160 ns tADD2 (4 + 2n)tCY – 200 ns tRDD1 (1.4 + 2n)tCY – 70 ns tRDD2 (2.4 + 2n)tCY – 70 ns Data input time from RD↓ Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.4 + 2n)tCY – 20 ns tRDL2 (2.4 + 2n)tCY – 20 ns WAIT↓ input time from RD↓ WAIT↓ input time from WR↓ tRDWT1 tCY – 100 ns tRDWT2 2tCY – 100 ns tWRWT 2tCY – 100 ns (2 + 2n)tCY ns WAIT low-level width tWTL (1 + 2n)tCY Write data setup time tWDS (2.4 + 2n)tCY – 60 ns Write data hold time tWDH 20 ns WR low-level width tWRL1 (2.4 + 2n)tCY – 20 ns RD↓ delay time from ASTB↓ tASTRD 0.4tCY – 30 ns WR↓ delay time from ASTB↓ tASTWR 1.4tCY – 30 ns ASTB↑delay time from RD↑ in external fetch tRDAST tCY – 10 tCY + 20 ns Address hold time from RD↑ in external fetch tRDADH tCY – 50 tCY + 50 ns Write data output time from RD↑ tRDWD 0.4tCY – 20 Write data output time from WR↓ tWRWD 0 60 ns Address hold time from WR↑ tWRADH tCY tCY + 60 ns RD↑ delay time from WAIT↑ tWTRD 0.6tCY + 180 2.6tCY + 180 ns WR↑ delay time from WAIT↑ tWTWR 0.6tCY + 120 2.6tCY + 120 ns Remarks 1. MCS: Bit 0 of the oscillation mode selection register (OSMS) 2. PCC2 to PCC0: Bit 2 to bit 0 of the processor clock control register (PCC) 3. tCY = TCY/4 4. n indicates the number of waits. ns 41 µPD78P058F (3) Serial Interface (TA = –40 to +85°C, VDD = 2.7 to 6.0 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0 ... internal clock output) Parameter SCK0 cycle time SCK0 high-/low-level width Symbol tKCY1 tKH1, Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKL1 SI0 setup time (to SCK0↑) tSIK1 SI0 hold time (from SCK0↑) tKSI1 SO0 output delay time from SCK0↓ tKSO1 MIN. TYP. MAX. Unit 800 ns 1600 ns tKCY1/2 – 50 ns tKCY1/2 – 100 ns 100 ns 150 ns 400 ns VDD = 4.5 to 6.0 V C = 100 pFNote 300 ns MAX. Unit Note C is the SCK0 and SO0 output line load capacitance. (ii) 3-wire serial I/O mode (SCK0 ... external clock input) Parameter SCK0 cycle time Symbol TYP. ns 1600 ns 400 ns tKL2 800 ns SI0 setup time (to SCK0↑) tSIK2 100 ns SI0 hold time (from SCK0↑) tKSI2 400 ns SO0 output delay time from SCK0↓ tKSO2 C = 100 pFNote 300 ns SCK0 rise, fall time tR2, tF2 When using external device expansion function 160 ns When not using external device expansion function 1000 ns tKH2, VDD = 4.5 to 6.0 V MIN. 800 SCK0 high-/low-level width tKCY2 Test Conditions VDD = 4.5 to 6.0 V Note C is the SO0 output line load capacitance. 42 µPD78P058F (iii) SBI mode (SCK0 ... internal clock output) Parameter SCK0 cycle time SCK0 high-/low-level width Symbol tKCY3 tKH3, Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKL3 SB0, SB1 setup time (to SCK0↑) tSIK3 SB0, SB1 hold time (from SCK0↑) tKSI3 SB0, SB1 output delay time from tKSO3 VDD = 4.5 to 6.0 V R = 1 kΩ, VDD = 4.5 to 6.0 V C = 100 pFNote SCK0↓ MIN. TYP. MAX. Unit 800 ns 3200 ns tKCY3/2 – 50 ns tKCY3/2 – 150 ns 100 ns 300 ns tKCY3/2 ns 0 250 ns 0 1000 ns SB0, SB1↓ from SCK0↑ tKSB tKCY3 ns SCK0↓ from SB0, SB1↓ tSBK tKCY3 ns SB0, SB1 high-level width tSBH tKCY3 ns SB0, SB1 low-level width tSBL tKCY3 ns Note R and C are the SCK0, SB0, and SB1 output line load resistance and load capacitance. (iv) SBI mode (SCK0 ... external clock input) Parameter SCK0 cycle time SCK0 high-/low-level width Symbol tKCY4 tKH4, Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKL4 SB0, SB1 setup time (to SCK0↑) tSIK4 SB0, SB1 hold time (from SCK0↑) tKSI4 SB0, SB1 output delay time from tKSO4 VDD = 4.5 to 6.0 V R = 1 kΩ, VDD = 4.5 to 6.0 V Note SCK0↓ C = 100 pF MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 300 ns tKCY4/2 ns 0 300 ns 0 1000 ns SB0, SB1↓ from SCK0↑ tKSB tKCY4 ns SCK0↓ from SB0, SB1↓ tSBK tKCY4 ns SB0, SB1 high-level width tSBH tKCY4 ns SB0, SB1 low-level width tSBL tKCY4 ns SCK0 rise, fall time tR4, tF4 When using external device expansion function When not using external device expansion function 160 ns 1000 ns Note R and C are the SB0 and SB1 output line load resistance and load capacitance. 43 µPD78P058F (v) 2-wire serial I/O mode (SCK0 ... internal clock output) Parameter SCK0 cycle time Symbol Test Conditions tKCY5 R = 1 kΩ, SCK0 high-level width tKH5 C = 100 pFNote SCK0 low-level width tKL5 SB0, SB1 setup time (to SCK0↑) VDD = 4.5 to 6.0 V tSIK5 VDD = 4.5 to 6.0 V MIN. TYP. MAX. Unit 1600 ns tKCY5/2 – 160 ns tKCY5/2 – 50 ns tKCY5/2 – 100 ns 300 ns 350 ns ns SB0, SB1 hold time (from SCK0↑) tKSI5 600 SB0, SB1 output delay time from SCK0↓ tKSO5 0 300 ns MAX. Unit Note R and C are the SCK0, SB0, and SB1 output line load resistance and load capacitance. (vi) 2-wire serial I/O mode (SCK0 ... external clock input) Parameter Symbol Test Conditions MIN. TYP. SCK0 cycle time tKCY6 1600 ns SCK0 high-level width tKH6 650 ns SCK0 low-level width tKL6 800 ns SB0, SB1 setup time (to SCK0↑) tSIK6 100 ns SB0, SB1 hold time (from SCK0↑) tKSI6 tKCY6/2 ns SB0, SB1 output delay time tKSO6 VDD = 4.5 to 6.0 V 0 300 ns 0 500 ns When using external device expansion function 160 ns When not using external device expansion function 1000 ns Note from SCK0↓ SCK0 rise, fall time R = 1 kΩ, C = 100 pF tR6, tF6 Note R and C are the SB0 and SB1 output line load resistance and load capacitance. 44 µPD78P058F (b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 ... internal clock output) Parameter SCK1 cycle time SCK1 high-/low-level width Symbol tKCY7 tKH7, Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKL7 SI1 setup time (to SCK1↑) SI1 hold time (from SCK1↑) SO1 output delay time from SCK1↓ tSIK7 VDD = 4.5 to 6.0 V tKSI7 tKSO7 C = 100 pF MIN. TYP. MAX. Unit 800 ns 1600 ns tKCY7/2 – 50 ns tKCY7/2 – 100 ns 100 ns 150 ns 400 ns Note 300 ns MAX. Unit Note C is the SCK1 and SO1 output line load capacitance. (ii) 3-wire serial I/O mode (SCK1 ... external clock input) Parameter SCK1 cycle time SCK1 high-/low-level width Symbol tKCY8 tKH8, Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. 800 ns 1600 ns 400 ns tKL8 800 ns SI1 setup time (to SCK1↑) tSIK8 100 ns SI1 hold time (from SCK1↑) tKSI8 400 ns Note SO1 output delay time from SCK1↓ tKSO8 C = 100 pF SCK1 rise, fall time tR8, tF8 When using external device expansion function When not using external device expansion function 300 ns 160 ns 1000 ns Note C is the SO1 output line load capacitance. 45 µPD78P058F (iii) Automatic transmission/reception function 3-wire serial I/O mode (SCK1 ... internal clock output) Parameter SCK1 cycle time SCK1 high-/low-level width Symbol tKCY9 tKH9, Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKL9 SI1 setup time (to SCK1↑) tSIK9 SI1 hold time (from SCK1↑) tKSI9 SO1 output delay time from SCK1↓ tKSO9 STB↑ from SCK1↑ tSBD Strobe signal high-level width Busy signal setup time VDD = 4.5 to 6.0 V MIN. TYP. MAX. Unit 800 ns 1600 ns tKCY9/2 – 50 ns tKCY9/2 – 100 ns 100 ns 150 ns 400 ns C = 100 pFNote 300 ns tKCY9/2 – 100 tKCY9/2 + 100 ns tSBW tKCY9 – 30 tKCY9 + 30 ns tBYS 100 ns 100 ns 150 ns (to busy signal detection timing) Busy signal hold time tBYH VDD = 4.5 to 6.0 V (from busy signal detection timing) SCK1↓ from busy inactive Note tSPS 2tKCY9 ns C is the SCK1 and SO1 output line load capacitance. (iv) Automatic transmission/reception function 3-wire serial I/O mode (SCK1 ... external clock input) Parameter SCK1 cycle time Symbol TYP. MAX. Unit ns 1600 ns 400 ns tKL10 800 ns SI1 setup time (to SCK1↑) tSIK10 100 ns SI1 hold time (from SCK1↑) tKSI10 400 ns SO1 output delay time from SCK1↓ tKSO10 C = 100 pFNote 300 ns SCK1 rise, fall time tR10, tF10 When using external device expansion function 160 ns When not using external device expansion function 1000 ns tKH10, VDD = 4.5 to 6.0 V MIN. 800 SCK1 high-/low-level width tKCY10 Test Conditions VDD = 4.5 to 6.0 V Note C is the SO1 output line load capacitance. 46 µPD78P058F (c) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2 ... internal clock output) Parameter SCK2 cycle time SCK2 high-/low-level width Symbol tKCY11 tKH11, Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKL11 SI2 setup time (to SCK2↑) SI2 hold time (from SCK2↑) SO2 output delay time from SCK2↓ tSIK11 VDD = 4.5 to 6.0 V tKSI11 tKSO11 C = 100 pF MIN. TYP. MAX. Unit 800 ns 1600 ns tKCY11/2 – 50 ns tKCY11/2 – 100 ns 100 ns 150 ns 400 ns Note 300 ns MAX. Unit 78125 bps 39063 bps MAX. Unit Note C is the SCK2 and SO2 output line load capacitance. (ii) UART mode (Dedicated baud rate generator output) Parameter Symbol Transfer rate Test Conditions MIN. TYP. VDD = 4.5 to 6.0 V (iii) UART mode (External clock input) Parameter ASCK cycle time Symbol tKCY12 ASCK high-/low-level tKH12, width tKL12 Transfer rate ASCK rise, fall time Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tR12, tF12 VDD = 4.5 to 6.0 V, when not using external device expansion function MIN. TYP. 800 ns 1600 ns 400 ns 800 ns 39063 bps 19531 bps 1000 ns 160 ns 47 µPD78P058F AC Timing Test Point (Excluding X1, XT1 Inputs) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD Clock Timing 1/fX tXL tXH VDD – 0.5 V 0.4 V X1 Input 1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.) XT1 Input TI Timing tTIL00, tTIL01 tTIH00, tTIH01 TI00, TI01 1/fTI1 tTIL1 TI1, TI2 48 tTIH1 µPD78P058F Read/Write Operations External fetch (no wait): A8 to A15 High-Order 8-Bit Address Low-Order 8-Bit Address tADD1 Hi-Z AD0 to AD7 tADS tASTH Operation Code tRDD1 tADH tRDADH tRDAST ASTB RD tRDL1 tASTRD tRDH External fetch (wait insertion): A8 to A15 High-Order 8-Bit Address Low-Order 8-Bit Address t ADD1 Hi-Z AD0 to AD7 t ADS t ADH Operation Code t RDD1 tRDADH tRDAST t ASTH ASTB RD t ASTRD t RDH t RDL1 WAIT t RDWT1 t WTL t WTRD 49 µPD78P058F External data access (no wait): A8 to A15 High-Order 8-Bit Address Low-Order 8-Bit Address tADD2 Hi-Z AD0 to AD7 tADS Hi-Z Read Data Hi-Z Write Data tRDD2 tADH tASTH tRDH ASTB RD tASTRD tRDWD tRDL2 tWDH t WRADH tWDS tWRWD WR tWRL1 tASTWR External data access (wait insertion): Low-Order 8-Bit Address A8 to A15 High-Order 8-Bit Address tADD2 Hi-Z AD0 to AD7 Read Data Hi-Z Hi-Z Write Data tADS tASTH tADH tRDD2 tRDH ASTB tASTRD RD tRDWD tRDL2 tWDS tWDH tWRWD WR tASTWR tWRADH tWRL1 WAIT tRDWT2 50 tWTL tWTRD tWRWT tWTL tWTWR µPD78P058F Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKHm tKLm tRn tFn SCK0 to SCK2 tSIKm SI0 to SI2 tKSIm Input Data tKSOm SO0 to SO2 Output Data Remark m = 1, 2, 7, 8, 11 n = 2, 8 SBI mode (bus release signal transfer): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 SB0, SB1 tKSO3, 4 SBI mode (command signal transfer): tKL3, 4 tKCY3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBK tSIK3, 4 tKSI3, 4 SB0, SB1 tKSO3, 4 51 µPD78P058F 2-wire serial I/O mode: tKCY5, 6 tKL5, 6 tKH5, 6 tR6 tF6 SCK0 tSIK5, 6 tKSI5, 6 tKSO5, 6 SB0, SB1 Automatic transmission/reception function 3-wire serial I/O mode: SO1 D2 SI1 D2 D1 D0 D1 D7 D0 t SIK9, 10 D7 t KSI9, 10 t KH9, 10 t KSO9, 10 t F10 SCK1 t R10 t KL9, 10 t SBD t SBW t KCY9, 10 STB Automatic transmission/reception function 3-wire serial I/O mode (busy processing): 7 SCK1 8 9Note 10Note t BYS 10+n Note t BYH BUSY (Active high) Note 52 The signal is not actually low here, but is represented this way to show the timing. 1 t SPS µPD78P058F UART mode (external clock input): tKCY12 tKH12 tKL12 t R12 t F12 ASCK 53 µPD78P058F A/D Converter Characteristics (TA = –40 to +85°C, AVDD = VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions Resolution Total error MIN. TYP. MAX. Unit 8 8 8 bit 1.4 % 200 µs 2.7 V ≤ AVREF0 ≤ AVDD Note Conversion time tCONV 19.1 Sampling time tSAMP 12/fXX Analog input voltage VIAN AVSS Reference voltage AVREF0 2.7 AVREF0 to AVSS resistance RAIREF0 4 Note µs AVREF0 AVDD 14 V V kΩ Excluding quantization error (±1/2LSB). Shown as a percentage of the full scale value. Caution For pins which also function as port pins (see 2.1 Pins in Normal Operating Mode (1) Port pins), do not perform the following operations during A/D conversion. If these operations are performed, the total error ratings cannot be kept. <1> Rewrite the output latch while the pin is used as a port pin. <2> Change the output level of the pin used as an output pin, even if it is not used as a port pin. Remarks 1. fXX : Main system clock frequency (fX or fX/2) 2. fX : Main system clock oscillation frequency D/A Converter Characteristics (TA = –40 to +85°C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 8 bit R = 2 MΩNote 1 1.2 % Note 1 0.8 % Resolution Total error R = 4 MΩ R = 10 MΩ Settling time Output resistance RO Analog reference voltage AVREF1 AVREF1 to AVSS resistance RAIREF1 Note 1 0.6 % C = 30 pFNote 1 4.5 V ≤ AVREF1 ≤ 6.0 V 10 µs 2.7 V ≤ AVREF1 < 4.5 V 15 µs Note 2 10 2.0 DACS0, DACS1 = 55HNote 2 4 8 Notes 1. R and C are the D/A converter output pin load resistance and load capacitance. 2. Value for one D/A converter channel Remark DACS0, DACS1 : D/A conversion value setting register 0, 1 54 kΩ VDD V kΩ µPD78P058F Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal setup time tSREL Oscillation stabilization wait time tWAIT Test Conditions MIN. TYP. 1.8 VDDDR = 1.8 V Subsystem clock stopped, feedback resistor disconnected 0.1 MAX. Unit 6.0 V 10 µA µs 0 Release by RESET 217/fX ms Release by interrupt Note ms 212/fXX, or 214/fXX through 217/fXX can be selected by bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization Note time selection register (OSTS). Remark fXX : Main system clock frequency (fX or fX/2) fX : Main system clock oscillation frequency Data Retention Timing (STOP mode release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby release signal: STOP mode release by interrupt signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 55 µPD78P058F Interrupt Input Timing t INTL INTP0 to INTP6 RESET Input Timing t RSL RESET 56 t INTH µPD78P058F PROM PROGRAMMING CHARACTERISTICS DC Characteristics (1) PROM Write Mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Symbol SymbolNote Input voltage, high VIH VIH Input voltage, low VIL VIL Output voltage, high VOH VOH IOH = –1 mA Output voltage, low VOL VOL IOL = 1.6 mA ILI ILI 0 ≤ VIN ≤ VDD Parameter Input leakage current Test Conditions MIN. TYP. MAX. Unit 0.7 VDD VDD V 0 0.3 VDD V 0.4 V +10 µA VDD – 1.0 V –10 VPP supply voltage VPP VPP 12.2 12.5 12.8 V VDD supply voltage VDD VCC 6.25 6.5 6.75 V VPP supply current IPP IPP 50 mA VDD supply current IDD ICC 50 mA PGM = VIL (2) PROM Read Mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V) Symbol SymbolNote MAX. Unit Input voltage, high VIH VIH 0.7 VDD VDD V Input voltage, low VIL VIL 0 0.3 VDD V Parameter Output voltage, high Output voltage, low Input leakage current Test Conditions MIN. TYP. VOH1 VOH1 IOH = –1 mA VDD – 1.0 V VOH2 VOH2 IOH = –100 µA VDD – 0.5 V VOL VOL IOL = 1.6 mA ILI ILI 0 ≤ VIN ≤ VDD 0 ≤ VOUT ≤ VDD, OE = VIH –10 0.4 V +10 µA Output leakage current ILO ILO +10 µA VPP supply voltage VPP VPP VDD – 0.6 VDD VDD + 0.6 V VDD supply voltage VDD VCC 4.5 5.0 5.5 V VPP supply current IPP IPP VDD supply current IDD ICCA1 Note –10 VPP = VDD 100 µA CE = VIL, VIN = VIH 50 mA Corresponding symbols for the µPD27C1001A. 57 µPD78P058F AC Characteristics (1) PROM Write Mode (a) Page program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Symbol SymbolNote Address setup time (to OE↓) tAS tAS 2 µs OE setting time tOES tOES 2 µs CE setup time (to OE↓) tCES tCES 2 µs Input data setup time (to OE↓) tDS tDS 2 µs Address hold time (from OE↑) tAH tAH 2 µs Parameter Input data hold time (from OE↑) Test Conditions MIN. TYP. MAX. Unit tAHL tAHL 2 µs tAHV tAHV 0 µs tDH tDH 2 µs Data output float delay time from OE↑ tDF tDF 0 VPP setup time (to OE↓) tVPS tVPS 1.0 250 ms VDD setup time (to OE↓) tVDS tVCS 1.0 ms Program pulse width tPW tPW 0.095 0.1 ns 0.105 ms 1 µs Valid data delay time from OE↓ tOE tOE OE pulse width during data latching tLW tLW 1 µs PGM setting time tPGMS tPGMS 2 µs CE hold time tCEH tCEH 2 µs OE hold time tOEH tOEH 2 µs (b) Byte program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Symbol SymbolNote Address setup time (to PGM↓) tAS tAS 2 µs OE setting time tOES tOES 2 µs CE setup time (to PGM↓) tCES tCES 2 µs Input data setup time (to PGM↓) tDS tDS 2 µs Address hold time (from OE↑) tAH tAH 2 µs Input data hold time (from PGM↑) tDH tDH 2 Data output float delay time from OE↑ tDF tDF 0 VPP setup time (to PGM↓) tVPS tVPS 1.0 VDD setup time (to PGM↓) tVDS tVCS 1.0 Program pulse width tPW tPW 0.095 Valid data delay time from OE↓ tOE tOE OE hold time tOEH — Parameter Note 58 Corresponding symbols for the µPD27C1001A. Test Conditions MIN. 2 TYP. MAX. Unit µs 250 ns ms ms 0.1 0.105 ms 1 µs µs µPD78P058F (2) PROM Read Mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V) Symbol SymbolNote Data output delay time from address tACC tACC Data output delay time from CE↓ tCE Data output delay time from OE↓ Data output float delay time from OE↑ Data hold time from address Parameter Note Test Conditions MIN. TYP. MAX. Unit CE = OE = VIL 800 ns tCE OE = VIL 800 ns tOE tOE CE = VIL tDF tDF CE = VIL 0 tOH tOH CE = OE = VIL 0 200 ns 60 ns ns Corresponding symbols for the µPD27C1001A. (3) PROM Programming Mode Setting (TA = 25°C, VSS = 0 V) Parameter Symbol PROM programming mode setup time tSMA Test Conditions MIN. 10 TYP. MAX. Unit µs 59 µPD78P058F PROM Write Mode Timing (page program mode) Page Data Latch Program Verify Page Program A2 to A16 tAS tAHL tAHV tDS tDH tDF A0, A1 D0 to D7 Hi-Z Hi-Z Data Input tVPS Hi-Z tPGMS tOE Data Output tAH VPP VPP VDD tVDS VDD+1.5 VDD VDD tCES tOEH VIH CE VIL tCEH tPW VIH PGM VIL tLW tOES VIH OE VIL 60 µPD78P058F PROM Write Mode Timing (byte program mode) Program Program Verify A0 to A16 tAS D0 to D7 Hi-Z tDF Hi-Z Page Data Data Input Latch tDS Hi-Z Data Output tDH tAH VPP VPP VDD tVPS VDD+1.5 VDD VDD tVDS tOEH VIH CE VIL tCES tPW VIH PGM VIL tOES tOE VIH OE VIL Cautions 1. VDD should be applied before VPP, and removed after VPP. 2. VPP must not exceed +13.5 V including overshoot. 3. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being applied to VPP. PROM Read Mode Timing Effective Address A0 to A16 VIH CE VIL tCE VIH OE VIL tACC D0 to D7 Note 1 Hi-Z tOE tDF Note 2 Note 1 tOH Data Output Hi-Z Notes 1. If you want to read within the tACC range, make the OE input delay time from the fall of CE a maximum of tACC – tOE. 2. tDF is the time from when either OE or CE first reaches VIH. 61 µPD78P058F PROM Programming Mode Setting Timing VDD VDD 0 RESET VDD VPP 0 tSMA A0 to A16 62 Effective Address µPD78P058F 8. PACKAGE DRAWINGS Package Drawing of µPD78P058FGC-3B9 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end C D S R Q 21 20 80 1 F J G I H M K P M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2±0.4 0.677±0.016 B 14.0±0.2 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.4 0.677±0.016 F 0.825 0.032 G 0.825 0.032 H 0.30±0.10 0.012 +0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6±0.2 L 0.8±0.2 0.063±0.008 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1±0.1 0.004±0.004 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S80GC-65-3B9-4 Remark The dimensions and materials of ES product are the same as those of mass-production products. 63 µPD78P058F Package Drawing of µPD78P058FGC-8BT 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end C S D R Q 80 1 21 20 F G H I M J P K M N NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 17.20±0.20 0.677±0.008 B 14.00±0.20 0.551 +0.009 –0.008 C 14.00±0.20 0.551 +0.009 –0.008 D 17.20±0.20 0.677±0.008 F 0.825 0.032 G 0.825 0.032 H 0.32±0.06 0.013 +0.002 –0.003 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.60±0.20 0.063±0.008 L 0.80±0.20 0.031 +0.009 –0.008 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N 0.10 0.004 P 1.40±0.10 0.055±0.004 Q 0.125±0.075 0.005±0.003 R 3° +7° –3° 3° +7° –3° S 1.70 MAX. 0.067 MAX. P80GC-65-8BT 64 µPD78P058F 9. RECOMMENDED SOLDERING CONDITIONS The µPD78P058F should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. Table 9-1. Surface Mount Type Soldering Conditions (1/2) (1) µPD78P058FGC-3B9 : 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235°C, Reflow time: 30 seconds or below (210°C or higher), Number of reflow processes: 3 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125°C for 20 hours) IR35-207-3 VPS Package peak temperature: 215°C, Reflow time: 40 seconds or below (200°C or higher), Number of reflow processes: 3 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125°C for 20 hours) VP15-207-3 Wave soldering Solder temperature: 260°C or below, Flow time: 10 seconds or below, Number of flow processes: 1, Preheating temperature: 120°C or below (package surface temperature), Exposure limit: 7 daysNote (after that, prebaking is necessary at 125°C for 20 hours) WS60-207-1 Pin partial heating Pin temperature: 300°C or below, Time: 3 seconds or below (per side of device) Note — The number of days for storage after the dry pack has been opened. Storage conditions are 25°C and 65% RH max. Caution Use of more than one soldering method should be avoided (except the pin partial heating method). 65 µPD78P058F Table 9-1. Surface Mount Type Soldering Conditions (2/2) (2) µPD78P058FGC-8BT : 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235°C, Reflow time: 30 seconds or below (210°C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125°C for 10 hours) IR35-107-2 VPS Package peak temperature: 215°C, Reflow time: 40 seconds or below (200°C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125°C for 10 hours) VP15-107-2 Wave soldering Solder temperature: 260°C or below, Flow time: 10 seconds or below, Number of flow processes: 1, Preheating temperature: 120°C or below (package surface temperature), Exposure limit: 7 daysNote (after that, prebaking is necessary at 125°C for 10 hours) WS60-107-1 Pin partial heating Pin temperature: 300°C or below, Time: 3 seconds or below (per side of device) Note — The number of days for storage after the dry pack has been opened. Storage conditions are 25°C and 65% RH max. Caution 66 Use of more than one soldering method should be avoided (except the pin partial heating method). µPD78P058F APPENDIX A. DEVELOPMENT TOOLS The following support tools are available for system development using the µPD78P058F. Language Processing Software RA78K/0Notes 1, 2, 3, 4 CC78K/0 78K/0 Series common assembler package Notes 1, 2, 3, 4 78K/0 Series common C compiler package µPD78054 Subseries common device file DF78054Notes 1, 2, 3, 4 CC78K/0-L Notes 1, 2, 3, 4 78K/0 Series common C compiler library source file PROM Writing Tools PG-1500 PROM programmer PA-78P054GC Programmer adapter connected to a PG-1500 PG-1500 controller Notes 1, 2 PG-1500 control program Debugging Tools IE-78000-R 78K/0 Series common in-circuit emulator IE-78000-R-A 78K/0 Series common in-circuit emulator (for integrated debugger) IE-78000-R-BK IE-78064-R-EM 78K/0 Series common break board Note 8 Emulation board common to µPD78064 Subseries IE-780308-R-EM Emulation board common to µPD780308 Subseries IE-78000-R-SV3 Interface adapter and cable (for IE-78000-R-A) when using EWS as a host machine IE-70000-98-IF-B Interface adapter (for IE-78000-R-A) when using PC-9800 Series (except notebook type computer) as a host machine IE-70000-98N-IF Interface adapter and cable (for IE-78000-R-A) when using PC-9800 Series notebook type computer as a host machine IE-70000-PC-IF-B Interface adapter (for IE-78000-R-A) when using IBM PC/AT™ and its compatibles as a host machine EP-78230GC-R Emulation probe common to µPD78234 Subseries EV-9200GC-80 (see Figure A-1) Socket for mounting on target system board created for 80-pin plastic QFP (GC-3B9, GC-8BT type) SM78K0Notes 5, 6, 7 78K/0 Series common system simulator ID78K0 Notes 4, 5, 6, 7 SD78K/0 Notes 1, 2 DF78054Notes 1, 2, 4, 5, 6, 7 Integrated debugger for IE-78000-R-A Screen debugger for IE-78000-R Device file common to µPD78054 Subseries 67 µPD78P058F Real-Time OS RX78K/0Notes 1, 2, 3, 4 MX78K0 Notes 1, 2, 3, 4 78K/0 Series real-time OS 78K/0 Series OS Fuzzy Inference Development Support System FE9000Note 1/FE9200Note 6 Fuzzy knowledge data input tool FT9080Note 1/FT9085Note 2 Translator FI78K0 Notes 1, 2 FD78K0 Fuzzy inference module Notes 1, 2 Fuzzy inference debugger Notes 1. PC-9800 Series (MS-DOSTM) based 2. IBM PC/AT and its compatibles (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 Series 300TM (HP-UXTM) based 4. HP9000 Series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS4800 Series (EWS-UX/V) based 5. PC-9800 Series (MS-DOS + WindowsTM) based 6. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based 8. Maintenance product Remarks 1. For third party development tools, see 78K/0 Series Selection Guide (U11126E). 2. The RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with the DF78054. 68 µPD78P058F Drawing of Conversion Socket (EV-9200GC-80) and Recommended Footprint Figure A-1. Drawing of EV-9200GC-80 (for Reference only) A E M B N O L K S J C D R F EV-9200GC-80 Q 1 No.1 pin index P G H I EV-9200GC-80-G1E ITEM MILLIMETERS INCHES A 18.0 0.709 B 14.4 0.567 C 14.4 0.567 D 18.0 0.709 E 4-C 2.0 4-C 0.079 F 0.8 0.031 G 6.0 0.236 H 16.0 0.63 I 18.7 0.736 J 6.0 0.236 K 16.0 0.63 L 18.7 0.736 M 8.2 0.323 N 8.0 0.315 O 2.5 0.098 P 2.0 0.079 Q 0.35 0.014 R φ 2.3 φ 0.091 S φ 1.5 φ 0.059 69 µPD78P058F Figure A-2. Recommended Footprint of EV-9200GC-80 (for Reference only) G J H D E F K I L C B A EV-9200GC-80-P1E ITEM MILLIMETERS A 19.7 B 15.0 0.776 0.591 C 0.65±0.02 × 19=12.35±0.05 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026 +0.001 –0.002 × 0.748=0.486 –0.002 0.026+0.001 –0.002 × 0.748=0.486 +0.003 –0.002 E 15.0 0.591 F 19.7 0.776 G 6.0 ± 0.05 0.236 +0.003 –0.002 H 6.0 ± 0.05 0.236 +0.003 –0.002 I 0.35 ± 0.02 0.014 +0.001 –0.001 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 2.3 φ 0.091 L φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution 70 INCHES Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). µPD78P058F APPENDIX B. RELATED DOCUMENTS Device Documents Document Name Document No. (English) Document No. (Japanese) µPD78058F, 78058FY Subseries User’s Manual U12068E U12068J µPD78P058F Data Sheet This document U11796J µPD78056F, 78058F Data Sheet U11795E U11795J 78K/0 Series User’s Manual Instructions U12326E U12326J 78K/0 Series Instruction Set — U10904J 78K/0 Series Instruction Table — U10903J Caution The contents of the above documents are subject to change without notice. Please ensure that the latest versions are used in design work, etc. 71 µPD78P058F Development Tool Documents (User's Manual) Document No. (English) Document Name RA78K Series Assembler Package Operation EEU-1399 EEU-809 Language EEU-1404 EEU-815 EEU-1402 U12323J Operation U11802E U11802J Assembly Language U11801E U11801J Structured Assembly Language U11789E U11789J Operation EEU-1280 EEU-656 Language EEU-1284 EEU-655 Operation U11517E U11517J Language U11518E U11518J Programming Know-how EEA-1208 EEA-618 RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package CC78K Series C Compiler CC78K0 C Compiler CC78K/0 C Compiler Application Note Document No. (Japanese) CC78K Series Library Source File — U12322J PG-1500 PROM Programmer EEU-1335 U11940J PG-1500 Controller PC-9800 Series (MS-DOS) based EEU-1291 EEU-704 PG-1500 Controller IBM PC Series (PC DOS) based U10540E EEU-5008 IE-78000-R U11376E U11376J IE-78000-R-A U10057E U10057J IE-78000-R-BK EEU-1427 EEU-867 IE-78064-R-EM EEU-1443 EEU-905 IE-780308-R-EM U11362E U11362J EP-78230 EEU-1515 EEU-985 SM78K0 System Simulator Windows based Reference U10181E U10181J SM78K Series System Simulator External Part User Open U10092E U10092J Interface Specifications ID78K0 Integrated Debugger EWS based Reference — U11151J ID78K0 Integrated Debugger PC based Reference U11539E U11539J ID78K0 Integrated Debugger Windows based Guide U11649E U11649J SD78K/0 Screen Debugger Introduction — EEU-852 PC-9800 Series (MS-DOS) based Reference — U10952J SD78K/0 Screen Debugger Introduction U10539E EEU-5024 IBM PC/AT (PC DOS) based Reference U11279E U11279J Caution The contents of the above documents are subject to change without notice. Please ensure that the latest versions are used in design work, etc. 72 µPD78P058F Embedded Software Documents (User's Manual) Document No. (English) Document Name 78K/0 Series Real-time OS Document No. (Japanese) Basics U11537E U11537J Installation U11536E U11536J Basics U12257E U12257J Fuzzy Knowledge Data Input Tools EEU-1438 EEU-829 78K/0, 78K/II, 87AD Series EEU-1444 EEU-862 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU-1441 EEU-858 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-1458 EEU-921 78K/0 Series OS MX78K0 Fuzzy Inference Development Support System Translator Other Documents Document Name Document No. (English) Document No. (Japanese) IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer Product Series Guide Caution — MEM-539 MEI-1202 C11893J — U11416J The contents of the above documents are subject to change without notice. Please ensure that the latest versions are used in design work, etc. 73 µPD78P058F NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 74 µPD78P058F Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 75 µPD78P058F FIP, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5