DATA SHEET MOS INTEGRATED CIRCUIT µPD70F3003 V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD70F3003 has a flash memory instead of the internal mask ROM of the µPD703003. This model is useful for small-scale production of a variety of application sets or early start of production since the program can be written and erased by the user even with the µPD70F3003 mounted on the board. Functions in detail are described in the following user’s manuals. Be sure to read these manuals when you design your systems. V853 User’s Manual-Hardware : U10913E V850 FamilyTM User’s Manual-Architecture : U10243E FEATURES • Compatible with µPD703003 • Can be replaced with mask ROM model for mass production of application set µPD70F3003 → µPD703003 • Internal flash memory: 128K bytes Remark For differences among the products, refer to 1. DIFFERENCES AMONG PRODUCTS. ORDERING INFORMATION Part Number µPD70F3003GC-25-7EA Package 100-pin plastic QFP (fine pitch) (14 × 14 mm) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12036EJ3V1DS00 (3rd edition) Date Published April 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1997 µPD70F3003 PIN CONFIGURATION (Top View) • 100-pin plastic QFP (fine pitch) (14 × 14 mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 ANO0 ANO1 AVREF2 AVREF3 P07/INTP113/ADTRG P06/INTP112 P05/INTP111 P04/INTP110 P03/TI11 P02/TCLR11 P01/TO111 P00/TO110 P117/INTP143 P116/INTP142 P115/INTP141 P114/INTP140 P113/TI14 P112/TCLR14 P111/TO141 P43/AD3 P42/AD2 VSS VDD P41/AD1 P40/AD0 P90/LBEN P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRO WAIT VPP MODE RESET CVDD/CKSEL X2 X1 CVSS CLKOUT VSS VDD P110/TO140 P31/TO131 P32/TCLR13 P33/TI13 P34/INTP130 P35/INTP131/SO3 P36/INTP132/SI3 P37/INTP133/SCK3 P63/A19 P62/A18 P61/A17 P60/A16 VSS VDD P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P30/TO130 P27/SCK1 P26/RXD1/SI1 P25/TXD1/SO1 P24/SCK0 P23/RXD0/SI0 P22/TXD0/SO0 P21/PWM1 P20/PWM0 NMI VDD VSS P17/INTP123/SCK2 P16/INTP122/SI2 P15/INTP121/SO2 P14/INTP120 P13/TI12 P12/TCLR12 P11/TO121 P10/TO120 AVDD AVSS AVREF1 P77/ANI7 P76/ANI6 µ PD70F3003GC-25-7EA Caution Directly connect VPP pin to VSS pin except the case that µPD70F3003 is used in flash memory programming mode. 2 Data Sheet U12036EJ3V1DS00 µPD70F3003 PIN NAMES : Address Bus P40-P47 : Port4 AD0-AD15 : Address/Data Bus P50-P57 : Port5 ADTRG : AD Trigger Input P60-P63 : Port6 ANI0-ANI7 : Analog Input P70-P77 : Port7 ANO0, ANO1 : Analog Output P90-P96 : Port9 ASTB : Address Strobe P110-P117 : Port11 AV DD : Analog V DD PWM0, PWM1 : Pulse Width Modulation AV REF1-AV REF3 : Analog Reference Voltage RESET : Reset AV SS : Analog V SS R/W : Read/Write Status CV DD : Power Supply for Clock Generator RXD0, PXD1 : Receive Data CV SS : Ground for Clock Generator SCK0-SCK3 : Serial Clock CKSEL : Clock Select SI0-SI3 : Serial Input CLKOUT : Clock Output SO0-SO3 : Serial Output DSTB : Data Strobe TO110, TO111, : Timer Output HLDAK : Hold Acknowledge TO120, TO121, HLDRQ : Hold Request TO130, TO131, A16-A19 INTP110-INTP113, : Interrupt Request from Peripherals TO140, TO141 INTP120-INTP123, TCLR11-TCLR14 : Timer Clear INTP130-INTP133, TI11-TI14 : Timer Input TXD0, TXD1 : Transmit Data : Lower Byte Enable UBEN : Upper Byte Enable MODE : Mode WAIT : Wait NMI : Non-maskable Interrupt Request X1, X2 : Crystal P00-P07 : Port 0 V DD : Power Supply P10-P17 : Port 1 V PP : Programming Power Supply P20-P27 : Port 2 V SS : Ground P30-P37 : Port 3 INTP140-INTP143 LBEN Data Sheet U12036EJ3V1DS00 3 µPD70F3003 INTERNAL BLOCK DIAGRAM Flash memory CPU NMI INTP110-INTP113 INTP120-INTP123 INTP130-INTP133 INTP140-INTP143 TO110, TO111 TO120, TO121 TO130, TO131 TO140, TO141 Instruction queue PC INTC 128 K bytes 32-bit barrel shifter Multiplier 16 × 16 → 32 System register RPU RAM TCLR11-TCLR14 TI11-TI14 4 KB BCU ASTB DSTB R/W UBEN LBEN WAIT A16-A19 AD0-AD15 HLDRQ HLDAK Generalpurpose register 32 bits × 32 ALU SIO SO0/TXD0 SI0/RXD0 SCK0 UART0/CSI0 BRG0 CSI2 Ports P110-P117 P90-P96 P70-P77 P60-P63 P50-P57 P40-P47 P30-P37 P20-P27 P10-P17 P00-P07 SO2 SI2 SCK2 D/A Converter ANO0, ANO1 BRG1 A/D Converter AVREF2, AVREF3 UART1/CSI1 ANI0-ANI7 AVREF1 AVSS AVDD ADTRG SO1/TXD1 SI1/RXD1 SCK1 CG CKSEL CLKOUT X1 X2 MODE RESET VDD VSS BRG2 CVDD 4 SO3 SI3 SCK3 CSI3 PWM0, PWM1 PWM CVSS VPP Data Sheet U12036EJ3V1DS00 µPD70F3003 CONTENTS 1. DIFFERENCES AMONG PRODUCTS ······························································································ 6 2. PIN FUNCTIONS ································································································································ 7 2.1 Port Pins ····················································································································································· 7 2.2 Pins Other Than Port Pins ························································································································ 9 2.3 I/O Circuits of Pins and Recommended Connections of Unused Pins ················································ 11 3. PROGRAMMING FLASH MEMORY ································································································· 14 3.1 Selecting Communication Mode ·············································································································· 14 3.2 Flash Memory Programming Function ···································································································· 15 3.3 Connecting Dedicated Flash Programmer ······························································································ 15 4. ELECTRICAL SPECIFICATIONS ······································································································· 16 4.1 Normal Operation Mode ···························································································································· 16 4.2 Flash Memory Programming Mode ·········································································································· 37 5. PACKAGE DRAWING ······················································································································· 39 6. RECOMMENDED SOLDERING CONDITIONS ················································································· 40 Data Sheet U12036EJ3V1DS00 5 µPD70F3003 1. DIFFERENCES AMONG PRODUCTS Parameter Internal ROM µPD703003 µPD703003A µPD703004A µPD703025A µPD70F3003 µPD70F3003A µPD70F3025A Mask ROM Flash memory 128K bytes Internal RAM Operation Normal mode operation mode 4K bytes Single chip mode Provided ROM-less mode Provided Flash memory programming mode 6 96K bytes 256K bytes 128K bytes 8K bytes None 256K bytes 4K bytes Provided 8K bytes None None Provided VPP pin None Provided CKC register value at reset 00H Electrical specifications Current consumption, etc. differs. (Refer to each product data sheets.) Others Noise immunity and noise radiation differ because circuit scale and mask layout differ. MODE = 0: 03H MODE = 1: 00H Data Sheet U12036EJ3V1DS00 00H MODE = 0: 03H MODE = 1: 00H µPD70F3003 2. PIN FUNCTIONS 2.1 Port Pins (1/2) Pin Name P00 I/O I/O Function Shared with: Port 0 TO110 P01 8-bit I/O port. TO111 P02 Can be set in input or output mode in 1-bit units. TCLR11 P03 TI11 P04 INTP110 P05 INTP111 P06 INTP112 P07 INTP113/ADTRG P10 I/O Port 1 TO120 P11 8-bit I/O port. TO121 P12 Can be set in input or output mode in 1-bit units. TCLR12 P13 TI12 P14 INTP120 P15 INTP121/SO2 P16 INTP122/SI2 P17 INTP123/SCK2 P20 I/O Port 2 PWM0 P21 8-bit I/O port. PWM1 P22 Can be set in input or output mode in 1-bit units. TXD0/SO0 P23 RXD0/SI0 P24 SCK0 P25 TXD1/SO1 P26 RXD1/SI1 P27 SCK1 P30 I/O Port 3 TO130 P31 8-bit I/O port. TO131 P32 Can be set in input or output mode in 1-bit units. TCLR13 P33 TI13 P34 INTP130 P35 INTP131/SO3 P36 INTP132/SI3 P37 INTP133/SCK3 P40-P47 I/O Port 4 AD0-AD7 8-bit I/O port. Can be set in input or output mode in 1-bit units. P50-P57 I/O Port 5 AD8-AD15 8-bit I/O port. Can be set in input or output mode in 1-bit units. Data Sheet U12036EJ3V1DS00 7 µPD70F3003 (2/2) Pin Name P60-P63 I/O I/O Function Port 6 Shared with: A16-A19 4-bit I/O port. Can be set in input or output mode in 1-bit units. P70-P77 Input Port 7 ANI0-ANI7 8-bit input port. P90 Port 9 LBEN P91 7-bit I/O port. UBEN P92 Can be set in input or output mode in 1-bit units. R/W P93 DSTB P94 ASTB P95 HLDAK P96 HLDRQ P110 8 I/O I/O Port 11 TO140 P111 8-bit I/O port. TO141 P112 Can be set in input or output mode in 1-bit units. TCLR14 P113 TI14 P114 INTP140 P115 INTP141 P116 INTP142 P117 INTP143 Data Sheet U12036EJ3V1DS00 µPD70F3003 2.2 Pins Other Than Port Pins (1/2) Pin Name TO110 I/O Output Function Pulse signal output of timer 11-14 Shared with: P00 TO111 P01 TO120 P10 TO121 P11 TO130 P30 TO131 P31 TO140 P110 TO141 P111 TCLR11 Input External clear signal of timer 11-14 P02 TCLR12 P12 TCLR13 P32 TCLR14 P112 TI11 Input External count clock of timer 11-14 P03 TI12 P13 TI13 P33 TI14 P113 INTP110 Input INTP111 External maskable interrupt reuest input and external capture P04 trigger input of timer 11 P05 INTP112 P06 INTP113 P07/ADTRG INTP120 Input INTP121 External maskable interrupt reuest input and external capture P14 trigger input of timer 12 P15/SO2 INTP122 P16/S12 INTP123 P17/SCK2 INTP130 Input INTP131 External maskable interrupt reuest input and external capture P34 trigger input of timer 13 P35/SO3 INTP132 P36/SI3 INTP133 P37/SCK3 INTP140 Input INTP141 External maskable interrupt reuest input and external capture P114 trigger input of timer 14 P115 INTP142 P116 INTP143 P117 SO0 Output Serial transmit data output of CSI0-CSI3 (3-wire) P22/TXD0 SO1 P25/TXD1 SO2 P15/INTP121 SO3 P35/INTP131 SI0 Input Serial receive data output of CSI0-CSI3 (3-wire) P23/RXD0 SI1 P26/RXD1 SI2 P16/INTP122 SI3 P36/INTP132 Data Sheet U12036EJ3V1DS00 9 µPD70F3003 (2/2) Pin Name SCK0 I/O I/O Function Serial clock I/O of CSI0-CSI3 (3-wire) Shared with: P24 SCK1 P27 SCK2 P17/INTP123 SCK3 P37/INTP133 TXD0 Output Serial transmit data output of UART0-UART1 TXD1 RXD0 P25/SO1 Input Serial receive data input of UART0-UART1 RXD1 PWM0 P23/SI0 P26/SI1 Output Pulse signal output of PWM PWM1 AD0-AD7 P22/SO0 P20 P21 I/O 16-bit multiplexed address/data bus when external memory is connected AD8-AD15 P40-P47 P50-P57 A16-A19 Output High-order address bus when external memory is connected P60-P63 LBEN Output Low-order byte enable signal output of external data bus P90 High-order byte enable signal output of external data bus P91 External read/write status output P92 DSTB External data strobe signal output P93 ASTB External address strobe signal output P94 Bus hold acknowledge output P95 UBEN R/W Output HLDAK Output HLDRQ Input Bus hold request input P96 ANI0-ANI7 Input Analog input to A/D converter P70-P77 ANO0, ANO1 NMI CLKOUT Output Input Output Analog output of D/A converter — Non-maskable interrupt request input — System clock output — CKSEL Input Input specifying operation mode of clock generator CVDD WAIT Input Control signal input inserting wait state in bus cycle — MODE Input Operation mode specification — RESET Input System reset input — X1 Input System clock resonator connection. Input external clock to X1 to — X2 — supply external clock. — ADTRG Input A/D converter external trigger input AVREF1 Input Reference voltage input for A/D converter — AVREF2 Input Reference voltage input for D/A converter — AVREF3 P07/INTP113 — AVDD — Positive power supply for A/D converter — AVSS — Ground potential for A/D converter — CVDD — Positive power supply for internal clock generator CVSS — Ground potential for internal clock generator — VDD — Positive power supply — VSS — Ground potential — VPP — High voltage application pin when program is written/verified — 10 Data Sheet U12036EJ3V1DS00 CKSEL µPD70F3003 2.3 I/O Circuits of Pins and Recommended Connections of Unused Pins Table 2-1 shows the I/O circuit type of each pin, and the recommended connections of the unused pins. Figure 2-1 shows a partially simplified diagram of each circuit. When connecting a pin to V DD or V SS via resistor, use of a resistor of 1 to 10 kΩ is recommended. Table 2-1. I/O Circuit Types of Each Pin and Recommended Connections of Unused Pins (1/2) Pin I/O Circuit Type Recommended Connections P00/TO110, P01/TO111 5 Input : Individually connect to VDD or VSS via resistor. P02/TCLR11, P03/TI11, 8 Output : Leave unconnected. P04/INTP110-P07/INTP113/ADTRG P10-TO120, P11/TO121 5 P12/TCLR12, P13/TI12 8 P14/INTP120 P15/INTP121/SO2 P16/INTP122/SI2 P17/INTP123/SCK2 P20/PWM0, P21/PWM1 5 P22/TXD0/SO0 P23/RXD0/SI0, P24/SCK0 8 P25/TXD1/SO1 5 P26/RXD1/SI1, P27/SCK1 8 P30/TO130, P31/TO131 5 P32/TCLR13, P33/TI13 8 P34/INTP130 P35/INTP131/SO3 10-A P36/INTP132/SI3 P37/INTP133/SCK3 P40/AD0-P47/AD7 5 P50/AD8-P57/AD15 P60/A16-P63/A19 P70/ANI0-P77/ANI7 9 Directly connect to VSS. P90/LBEN 5 Input: Individually connect to VDD or VSS via resistor. P91/UBEN Output: Leave unconnected. P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRQ P110/TO140, P111/TO141 P112/TCLR14, P113/TI14 8 P114/INTP140-P117/INTP143 Data Sheet U12036EJ3V1DS00 11 µPD70F3003 Table 2-1. I/O Circuit Types of Each Pin and Recommended Connections of Unused Pins (2/2) Pin I/O Circuit Type Recommended Connections ANO0, ANO1 12 Leave unconnected. NMI 2 Directly connect to VSS. CLKOUT 3 Leave unconnected. WAIT 1 Directly connect to VDD. MODE 2 — RESET CVDD/CKSEL — AVREF1-AVREF3, AVSS — Directly connect to VSS. AVDD — Directly connect to VDD. VPP — Directly connect to VSS. 12 Data Sheet U12036EJ3V1DS00 µPD70F3003 Figure 2-1. I/O Circuits of Pins Type 1 Type 8 VDD Data VDD P-ch IN/OUT P-ch Output disable IN N-ch N-ch Type 9 Type 2 P-ch N-ch IN Comparator + – IN VREF (Threshold voltage) Input enable Schmitt trigger input with hysteresis characteristics Type 3 Type 10-A VDD Pullup enable VDD P-ch VDD Data P-ch P-ch OUT IN/OUT Open drain Output disable N-ch N-ch Type 12 Type 5 VDD Data P-ch IN/OUT Analog output voltage Output disable P-ch N-ch OUT N-ch Input enable Data Sheet U12036EJ3V1DS00 13 µPD70F3003 3. PROGRAMMING FLASH MEMORY There are the following two methods for writing a program to the flash memory. (1) On-board programming Write a program to the flash memory using a dedicated flash programmer after the µPD70F3003 has been mounted on the target board. Also mount a connector, etc. on the target board to communicate with the dedicated flash programmer. (2) Off-board programming Write a program using a dedicated adapter before the µPD70F3003 has been mounted on the target board. 3.1 Selecting Communication Mode To write the flash memory, use a dedicated flash programmer and serial communication. Select a serial communication mode from those listed in Table 3-1 in the format shown in Figure 3-1. Each communication mode is selected by the number of V PP pulses shown in Table 3-1. Table 3-1. Communication Modes Communication Mode CSI Pins Used SCK0 (serial clock input) SO0 (serial data output) Number of VPP Pulses 0 SI0 (serial data input) UART TXD0 (serial data output) RXD0 (serial data input) 8 Figure 3-1. Communication Mode Selecting Format 10 V VPP VDD VSS VDD RESET VSS 14 Data Sheet U12036EJ3V1DS00 µPD70F3003 3.2 Flash Memory Programming Function The flash memory is written by transferring or receiving commands and data in a selected communication mode. The major functions of flush memory programming are listed in Table 3-2. Table 3-2. Major Functions of Flash Memory Programming Function Description Batch erasure Erases all contents of memory. Batch blank check Checks erased status of entire memory. Data write Writes flash memory based on write start address and number of data to be written (in bytes). Batch verify Compares all contents of memory with input data. 3.3 Connecting Dedicated Flash Programmer The dedicated flash programmer and µ PD70F3003 are connected differently depending on the selected communication mode. Figures 3-2 through 3-3 show the connections in the respective communication modes. Figure 3-2. Connection of Dedicated Flash Programmer in UART Mode Dedicated flash programmer µ PD70F3003 CLK CLK VPP VPP VDD VDD RESET RESET TxD RXD0 RxD TXD0 VSS VSS Figure 3-3. Connection of Dedicated Flash Programmer in CSI Mode Dedicated flash programmer µ PD70F3003 CLK CLK VPP VPP VDD VDD RESET SCK RESET SCK0 SO SI0 SI SO0 VSS VSS Data Sheet U12036EJ3V1DS00 15 µPD70F3003 4. ELECTRICAL SPECIFICATIONS 4.1 Normal Operation Mode Absolute Maximum Ratings (TA = 25 °C) Parameter Supply voltage Input voltage Symbol Condition Ratings Unit –0.5 to +7.0 V VDD VDD pin CVDD CVDD pin –0.5 to VDD + 0.3 V CVSS CVSS pin –0.5 to +0.5 V AVDD AVDD pin –0.5 to VDD + 0.3 V AVSS AVSS pin VI1 Note, VDD = 5.0 V ± 10 % VI2 VPP pin in flash memory programming mode, –0.5 to +0.5 V –0.5 to VDD + 0.3 V –0.5 to +11.0 V –0.5 to VDD + 1.0 V 4.0 mA VDD = 5.0 V ± 10 % Clock input voltage VK X1 pin, VDD = 5.0 V ± 10 % Output current, low ICL 1 pin Output current, high ICH Total of all pins 100 mA 1 pin –4.0 mA Total of all pins –100 mA Output voltage VO VDD = 5.0 V ± 10 % Analog input voltage VIAN P70/ANI0-P77/ANI7 Analog reference input voltage AVREF AVREF1-AVREF3 –0.5 to VDD + 0.3 V AVDD > VDD –0.5 to VDD + 0.3 V VDD ≥ AVDD –0.5 to AVDD + 0.3 V AVDD > VDD –0.5 to VDD + 0.3 V VDD ≥ AVDD –0.5 to AVDD + 0.3 V Operating ambient temperature TA –40 to +70 °C Storage temperature Tstg –40 to +100 °C Note Except X1, P70/AN0-P77/AN7, AVREF1-AVREF3 Cautions 1. Do not directly connect the output (or I/O) pins of two or more IC products, and do not directly connect them to VDD, VCC, or GND pin. Open-drain pins and open-collector pins may be directly connected to one another however. Moreover, an external circuit that is designed to prevent contention of output can be connected to pins that go into a high-impedance state. 2. Should the absolute maximum rating of even one of the above parameters be exceeded even momentarily, the quality of the program may be degraded. The absolute maximum ratings are, therefore, the values exceeding which the product may be physically damaged. Use the product so that these values are never exceeded. The normal operating ranges of ratings and conditions in which the quality of the product is guaranteed are specified in the following DC Characteristics and AC Characteristics. 16 Data Sheet U12036EJ3V1DS00 µPD70F3003 Capacitance (TA = 25 °C, VDD = VSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Input capacitance CI fc = 1 MHz 15 pF I/O capacitance CIO Pins other than tested pin: 0 V 15 pF Output capacitance CO 15 pF Operating Conditions Operation Mode Direct mode PLL mode Internal Operating Clock Frequency (φ) Operating Temperature (TA) Supply Voltage (VDD) 20 to 25 MHz –40 to +70 °C 5.0 V ± 5 % Self oscillation frequency to 25 MHz –40 to +70 °C 5.0 V ± 5 % Remark The internal operating clock frequency range in the PLL mode means the range in which the functional operation is guaranteed, and the frequency in the PLL lock status is specified by tCYX. Data Sheet U12036EJ3V1DS00 17 µPD70F3003 Recommended Oscillation Circuit (a) Ceramic resonator connection (TDK, Murata Mfg.: TA = –40 to +85 °C, Kyocera: TA = –20 to +80 °C) X1 X2 Rd C1 Manufacturer Oscillation Frequency fXX (MHz) C1(pF) C2 (pF) Rd (Ω) MIN. (V) CCR5.0MC3 5.0 Provided Provided – 4.5 5.5 0.42 FCR5.0MC5 5.0 Provided Provided – 4.5 5.5 0.38 Murata Mfg. CSA5.00MG040 5.0 100 100 – 4.5 5.5 0.51 Co. Ltd. CST5.00MGW040 5.0 Provided Provided – 4.5 5.5 0.51 5.0 Provided Provided 680 4.5 5.5 0.20 TDK Corp. Part Number C2 Kyocera Corp. KBR-5.0MKS Recommended Circuit Constants Oscillation Voltage Range Oscillation Stabilization Time (MAX.) MAX. (V) TOST (ms) Cautions 1. Connect the oscillation circuit as closely to X1 and X2 pins as possible. 2. Do not route any other signal lines in the range indicated by the broken line in the above figure. 3. Thoroughly evaluate the matching between the µPD70F3003 and resonator. (b) External clock input X1 X2 Open High-speed CMOS inverter External clock Cautions 1. Connect the high-speed CMOS inverter as closely to X1 pin as possible. 2. Thoroughly evaluate the matching between the µPD70F3003 and high-speed CMOS inverter. 18 Data Sheet U12036EJ3V1DS00 µPD70F3003 DC Characteristics (TA = –40 to +70 °C, VDD = 5.0 V ± 5 %, VSS = 0 V) Parameter Symbol Input voltage, high VIH Condition MAX. Unit 2.2 VDD + 0.3 V 0.8 VDD VDD + 0.3 V Except X1 and Note –0.5 +0.8 V Note –0.5 0.2 VDD V Except X1 and Note Note Input voltage, low VIL MIN. TYP. Clock input voltage, high VXH X1 0.8 VDD VDD + 0.5 V Clock input voltage, low VXL X1 –0.5 +0.6 V Schmitt trigger input threshold voltage VT + VT – + Schmitt trigger input hysteresis width VT – VT Output voltage, high VOH – Note, rising 3.0 V Note, falling 2.0 V Note 0.5 V IOH = –2.5 mA 0.7 VDD V IOH = –100 µA VDD – 0.5 V Output voltage, low VOL IOC = 2.5 mA 0.45 V Input leakage current, high ILIH VI = VDD 10 µA Input leakage current, low ILIL VI = 0 V –10 µA Output leakage current, high ILOH VO = VDD 10 µA Output leakage current, low ILOL VO = 0 V –10 µA Software pull-up resistor R P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3 40 90 kΩ IDD1 Direct mode 2.6 × φ + 7.5 2.9 × φ + 22 mA PLL mode 2.7 × φ + 9.5 3.0 × φ + 25 mA Direct mode 1.4 × φ + 7.5 1.5 × φ + 18 mA PLL mode 1.5 × φ + 9.5 1.6 × φ + 20 mA Direct mode 18.6 × φ + 100 22 × φ + 200 µA Supply current Operating In HALT mode In IDLE mode IDD2 IDD3 15 0.05 × φ + 4 0.1 × φ + 8 mA –40 °C ≤ TA ≤ +50 °C 2 50 µA 50 °C < TA ≤ 70 °C 2 200 µA PLL mode In STOP mode IDD4 Note P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/ TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE Remarks 1. TYP. value is a value for your reference at TA = 25 °C and VDD = 5.0 V. The supply current does not include AVREF1-AVREF3 and the current running through the software pull-up resistor. 2. φ : Internal system clock frequency Data Sheet U12036EJ3V1DS00 19 µPD70F3003 Data Retention Characteristics (TA = –40 to +70 °C) Parameter Symbol Condition MIN. Data hold voltage VDDDR STOP mode Data hold current IDDDR VDD = VDDDR –40 °C ≤ TA ≤ +50 °C TYP. MAX. Unit 5.5 V 0.2 VDDDR 50 µA 0.2 VDDDR 200 µA 1.5 50 °C < TA ≤ 70 °C Supply voltage rise time tRVD 200 µs Supply voltage fall time tFVD 200 µs Supply voltage hold time (vs. STOP mode setting) tHVD 0 ms STOP mode release signal input time tDREL 0 ns Data hold input voltage, high VIHDR Note 0.9 VDDDR VDDDR V Data hold input voltage, low VILDR Note 0 0.1 VDDDR V Note P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/ TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/ TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE, X1 Remark TYP. value is a value for your reference at TA = 25 °C and VDD = 5.0 V. STOP mode is set (at fifth clock after PSC register has been set). VDD VDD VDD VDDDR tHVD RESET (input) NMI (input) (Release by falling edge) tFVD tRVD VIHDR VIHDR NMI (input) (Release by rising edge) VILDR 20 Data Sheet U12036EJ3V1DS00 tDREL µPD70F3003 AC Characteristics (TA = –40 to +70 °C, VDD = 5.0 V ± 5 %, VSS = 0 V) AC test input wave (a) P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/ TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112,TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE, X1 VDD 0.8 VDD 0.8 VDD Test point 0V 0.2 VDD 0.2 VDD (b) Other than (a) 2.4 V 2.2 V 2.2 V Test point 0.4 V 0.8 V 0.8 V AC test output test point 2.2 V 2.2 V Test point 0.8 V 0.8 V Load condition DUT (tested device) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, decrease the load capacitance of this device to less then 50 pF by using a buffer. Data Sheet U12036EJ3V1DS00 21 µPD70F3003 (1) Clock timing Parameter X1 input cycle X1 input width, high X1 input width, low X1 input rise time X1 input fall time CPU operating frequency Symbol <1> <2> <3> <4> <5> tCYX tWXH tWXL tXR tXF φ — Condition MIN. MAX. Unit Direct mode 20 25 ns PLL mode (PLL lock status) 200 227 ns Direct mode 7 ns PLL mode 80 ns Direct mode 7 ns PLL mode 80 ns Direct mode 7 ns PLL mode 15 ns Direct mode 7 ns PLL mode 15 ns 20 25 MHz Note 25 MHz 50 ns Direct mode PLL mode CLKOUT output cycle <6> tCYK 40 CLKOUT width, high <7> tWKH 0.5 T – 5 ns CLKOUT width, low <8> tWKL 0.5 T – 5 ns CLKOUT rise time <9> tXR 5 ns CLKOUT fall time <10> tXF 5 ns X1 ↓→ CLKOUT delay time <11> tDXK 17 ns Note Direct mode 3 Self oscillation frequency. Remark T = tCYK Parameter Self oscillation frequency Symbol — φP Condition PLL mode TYP. Unit 5 MHz <1> <2> <3> X1 (input) <4> <11> <5> <6> <11> <7> <8> CLKOUT (output) <9> 22 Data Sheet U12036EJ3V1DS00 <10> µPD70F3003 (2) Input wave (a) P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/ TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE Parameter Symbol Condition MIN. MAX. Unit Input rise time <12> tIR2 20 ns Input fall time <13> tIF2 20 ns VDD 0.8 VDD 0.8 VDD Input signal 0.2 VDD 0V 0.2 VDD < 13 > < 12 > (b) Other than (a) Parameter Symbol Condition MIN. MAX. Unit Input rise time <14> tIR1 10 ns Input fall time <15> tIF1 10 ns 2.4 V 2.2 V 2.2 V Input signal 0.4 V 0.8 V < 15 > Data Sheet U12036EJ3V1DS00 0.8 V < 14 > 23 µPD70F3003 (3) Output wave (other than CLKOUT) Parameter Symbol Condition MIN. MAX. Unit Output rise time <16> tOR 12 ns Output fall time <17> tOF 12 ns 2.2 V 2.2 V Output signal 0.8 V 0.8 V < 16 > < 17 > (4) Reset timing Parameter Symbol RESET width, high <18> tWRSH RESET width, low <19> tWRSL Condition On power application, or on releasing STOP mode Except on power application, or except on releasing STOP mode MIN. RESET (input) 24 Data Sheet U12036EJ3V1DS00 Unit 500 ns 500 + TOST ns 500 ns Remark TOST: oscillation stabilization time < 18 > MAX. < 19 > µPD70F3003 (5) Read timing (1/2) Parameter MIN. MAX. Unit tDKA 3 20 ns CLKOUT ↑→ R/W, UBEN, LBEN, delay time <78> tDKA2 –2 +13 ns CLKOUT ↑→ address float delay time <21> tFKA 3 15 ns CLKOUT ↓→ ASTB delay time <22> tDKST –2 +13 ns CLKOUT ↓→ DSTB delay time <23> tDKD –2 +13 ns Data input setup time (vs. CLKOUT ↑) <24> tSIDK 7 ns Data input hold time (vs. CLKOUT ↑) <25> tHKID 5 ns WAIT setup time (vs. CLKOUT ↓) <26> tSWTK 8 ns WAIT hold time (vs. CLKOUT ↓) <27> tHKWT 5 ns Address hold time (vs. CLKOUT ↑) <28> tHKA 0 ns Address setup time (vs. ASTB ↓) <29> tSAST 0.5 T – 10 ns Address hold time (vs. ASTB ↓) <30> tHSTA 0.5 T – 10 ns CLKOUT ↑→ address delay time Symbol <20> Condition DSTB ↓→ address float delay time <31> tFDA 0 ns Data input setup time (vs. address) <32> tSAID (2 + n) T – 20 ns Data input setup time (vs. DSTB ↓) <33> tSDID (1 + n) T – 20 ns ASTB ↓→ DSTB ↓ delay time <34> tDSTD 0.5 T – 10 ns Data input hold time (vs. DSTB ↑) <35> tHDID 0 ns DSTB ↑→ address output delay time <36> tDDA (1 + i) T – 3 ns DSTB ↑→ ASTB ↑ delay time <37> tDDSTH 0.5 T – 10 ns DSTB ↑→ ASTB ↓ delay time <38> tDDSTL (1.5 + i) T – 10 ns DSTB width, low <39> tWDL (1 + n) T – 10 ns ASTB width, high <40> tWSTH T – 10 ns WAIT setup time (vs. address) <41> tSAWT1 <42> tSAWT2 <43> tHAWT1 <44> tHAWT2 <45> tSSTWT1 <46> tSSTWT2 <47> tHSTWT1 <48> tHSTWT2 WAIT hold time (vs. address) WAIT setup time (vs. ASTB ↓) WAIT hold time (vs. ASTB ↓) n≥1 n≥1 1.5 T – 20 ns (1.5 + n) T – 20 ns (0.5 + n) T ns (1.5 + n) T ns n≥1 n≥1 T – 15 ns (1 + n) T – 15 ns nT ns (1 + n) T ns Remarks 1. T = tCYK 2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when the programmable wait state is inserted. 3. i indicates the number of idle states (0 or 1) t be inserted in the read cycle. 4. Be sure to observe at least one of data input hold times tHKID (<25>) and tHDID (<35>). Data Sheet U12036EJ3V1DS00 25 µPD70F3003 (5) Read Timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output) < 78 > < 20 > < 28 > A16-A19 (output) Note < 32 > < 21 > AD0-AD15 (I/O) < 24 > A0-A15 (output) D0-D15 (input) < 22 > < 29 > < 25 > < 35 > < 30 > < 22 > ASTB (output) < 40> < 37 > < 34 > < 31 > < 23 > < 23 > < 33 > < 36 > DSTB (output) < 38 > < 39 > < 45 > < 26 > < 27 > < 26 > < 27 > < 47 > < 46 > < 48 > WAIT (input) < 41 > < 43 > < 42 > < 44 > Note R/W (output), UBEN (output), LBEN (output) Remark The broken line indicates the high-impedance state. 26 Data Sheet U12036EJ3V1DS00 µPD70F3003 (6) Write timing (1/2) Parameter CLKOUT ↑→ address delay time Symbol MIN. MAX. Unit tDKA 3 20 ns CLKOUT ↑→ R/W, UBEN, LBEN delay time <78> tDKA2 –2 +13 ns CLKOUT ↓→ ASTB delay time <22> tDKST –2 +13 ns CLKOUT ↑→ DSTB delay time <23> tDKD –2 +13 ns WAIT setup time (vs. CLKOUT ↓) <26> tSWTK 8 ns WAIT hold time (vs. CLKOUT ↓) <27> tHKWT 5 ns Address hold time (vs. CLKOUT ↑) <28> tHKA 0 ns Address setup time (vs. ASTB ↓) <29> tSAST 0.5 T – 10 ns Address hold time (vs. ASTB ↓) <30> tHSTA 0.5 T – 10 ns ASTB ↓→ DSTB ↓ delay time <34> tDSTD 0.5 T – 10 ns DSTB ↑→ ASTB ↑ delay time <37> tDDSTH 0.5 T – 10 ns DSTB width, low <39> tWDL (1 + n) T – 10 ns ASTB width, high <40> tWSTH T – 10 ns WAIT setup time (vs. address) <41> tSAWT1 <42> tSAWT2 <43> tHAWT1 <44> tHAWT2 <45> tSSTWT1 <46> tSSTWT2 <47> tHSTWT1 <48> tHSTWT2 CLKOUT ↑→ data output delay time <49> tDKOD 20 ns DSTB ↓→ data output delay time <50> tDDOD 10 ns Data output hold time (vs. CLKOUT ↑) <51> tHKOD 0 ns Data output setup time (vs. DSTB ↑) <52> tSODD (1 + n) T – 15 ns Data output hold time (vs. DSTB ↑) <53> tHDOD T – 10 ns WAIT hold time (vs. address) WAIT setup time (vs. ASTB ↓) WAIT hold time (vs. ASTB ↓) <20> Condition n≥1 n≥1 ns (1.5 + n) T – 20 ns (0.5 + n) T ns (1.5 + n) T ns n≥1 n≥1 1.5 T – 20 T – 15 ns (1 + n) T – 15 ns nT ns (1 + n) T ns Remarks 1. T = tCYK 2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when the programmable wait state is inserted. Data Sheet U12036EJ3V1DS00 27 µPD70F3003 (6) Write timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output) < 78 > < 20 > < 28 > A16-A19 (output) Note < 49 > AD0-AD15 (I/O) < 51 > A0-A15 (output) D0-D15 (output) < 22 > < 29 > < 30 > < 22 > ASTB (output) < 23 > < 23 > < 40 > < 34 > < 50 > < 53 > < 52 > DSTB (output) < 39 > < 45 > < 26 > < 27 > < 26 > < 27 > < 47 > < 46 > < 48 > WAIT (input) < 41 > < 43 > < 42 > < 44 > Note R/W (output), UBEN (output), LBEN (output) Remark The broken line indicates the high-impedance state. 28 Data Sheet U12036EJ3V1DS00 < 37 > µPD70F3003 (7) Bus hold timing (1/2) Parameter HLDRQ setup time (vs. CLKOUT ↓) Symbol Condition MIN. MAX. Unit <54> tSHOK 8 ns HLDRQ hold time (vs. CLKOUT ↓) <55> tHKHQ 5 ns CLKOUT ↑→ HLDAK delay time <56> tDKHA HLDRQ width, high <57> tWHQH T + 10 ns HLDAK width, low <58> tWHAL T – 10 ns CLKOUT↑ → Bus float delay time <59> tDKF HLDAK ↑→ bus output delay time <60> tDHAC HLDRQ ↓→ HLDAK ↓ delay time <61> tDHQHA1 HLDRQ ↑→ HLDAK ↑ delay time <62> tDHQHA2 20 20 –3 0.5 T ns ns ns (2 n + 7.5) T + 20 ns 1.5 T + 20 ns Remarks 1. T = tCYK 2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when the programmable wait state is inserted. Data Sheet U12036EJ3V1DS00 29 µPD70F3003 (7) Bus hold timing (2/2) TH TH TH TH TI CLKOUT (output) < 54 > < 54 > < 55 > < 57 > HLDRQ (input) < 56 > < 56 > < 61 > < 62 > HLDAK (output) < 58 > < 60 > < 59 > A16-A19 (output) Note AD0-AD15 (I/O) D0-D15 (input or output) ASTB (output) DSTB (output) R/W (output) Note UBEN (output), LBEN (output) Remark The broken line indicates the high-impedance state. 30 Data Sheet U12036EJ3V1DS00 µPD70F3003 (8) Interrupt timing Parameter Symbol Condition MIN. MAX. Unit NMI width, high <63> tWNIH 500 ns NMI width, low <64> tWNIL 500 ns INTPn width, high <65> tWITH n = 110-113, 120-123, 130-133, 140-143 3 T + 10 ns INTPn width, low <66> tWITL n = 110-113, 120-123, 130-133, 140-143 3 T + 10 ns Remark T = tCYK < 63 > < 64 > < 65 > < 66> NMI (input) INTPn (input) Remark n = 110-113, 120-123, 130-133, 140-143 Data Sheet U12036EJ3V1DS00 31 µPD70F3003 (9) CSI timing (1/2) (a) Master mode (i) CSI0-CSI2 timing Parameter Symbol Condition MIN. MAX. Unit SCKn cycle <67> tCYSK1 Output 160 ns SCKn width, high <68> tWSKH1 Output 0.5 tCYSK1 – 20 ns SCKn width, low <69> tWSKL1 Output 0.5 tCYSK1 – 20 ns SIn setup time (vs. SCKn ↑) <70> tSSISK1 50 ns SIn hold time (vs. SCKn ↑) <71> tHSKSI1 0 ns SOn output delay time (vs. SCKn ↓) <72> tDSKSO1 SOn output hold time (vs. SCKn ↑) <73> tHSKSO1 18 0.5 tCYSK1 – 5 ns ns Remark n = 0-2 (ii) CSI3 timing Parameter SCK3 cycle Symbol <67> SCK3 width, high <68> tCYSK3 Condition Output tWSKH3 Output Output MIN. RL = 1.5 kΩ CL = 50 pF MAX. Unit 500 ns 0.5 tCYSK3 – 150 ns SCK3 width, low <69> tWSKL3 0.5 tCYSK3 – 70 ns SI3 setup time (vs. SCK3 ↑) <70> tSSISK3 100 ns SI3 hold time (vs. SCK3 ↑) <71> tHSKSI3 50 ns SO3 output delay time (vs. SCK3 ↓) <72> tDSKSO3 SO3 output hold time (vs. SCK3 ↑) <73> tHSKSO3 RL = 1.5 KΩ CL = 50 pF 150 tWSKH3 ns ns Remark R L and C L are the load resistance and load capacitance respectively of the SCK3 and SO3 output lines. (b) Slave mode (i) CSI0-CSI2 timing Parameter Symbol Condition MIN. MAX. Unit SCKn cycle <67> tCYSK2 Input 160 ns SCKn width, high <68> tWSKH2 Input 50 ns SCKn width, low <69> tWSKL2 Input 50 ns SIn setup time (vs. SCKn ↑) <70> tSSISK2 10 ns SIn hold time (vs. SCKn ↑) <71> tHSKSI2 10 ns SOn output delay time (vs. SCKn ↓) <72> tDSKSO2 SOn output hold time (vs. SCKn ↑) <73> tHSKSO2 Remark n = 0-2 32 Data Sheet U12036EJ3V1DS00 45 tWSKH2 ns ns µPD70F3003 (9) CSI timing (2/2) (ii) CSI3 timing Parameter Symbol Condition MIN. MAX. Unit SCK3 cycle <67> tCYSK4 Input 500 ns SCK3 width, high <68> tWSKH4 Input 100 ns SCK3 width, low <69> tWSKL4 Input 180 ns SI3 setup time (vs. SCK3 ↑) <70> tSSISK4 100 ns SI3 hold time (vs. SCK3 ↑) <71> tHSKSI4 50 ns SO3 output delay time (vs. SCK3 ↓) <72> tDSKSO4 RL = 1.5 kΩ SO3 output hold time (vs. SCK3 ↑) <73> tHSKSO4 CL = 50 pF 150 tWSKH4 ns ns Remark R L and C L are the load resistance and load capacitance respectively of the SCK3 and SO3 output lines. < 67 > < 69 > < 68 > SCKn (I/O) < 70 > SIn (input) < 71 > Input data < 72 > < 73 > SOn (output) Output data Remark 1. The broken line indicates the high-impedance state. 2. n = 0-3 Data Sheet U12036EJ3V1DS00 33 µPD70F3003 (10) RPU timing Parameter Symbol Condition MIN. MAX. Unit TI1n width, high <74> tWTIH 3 T + 10 ns TI1n width, low <75> tWTIL 3 T + 10 ns TCLR1n width, high <76> tWTCH 3 T + 10 ns TCLR1n width, low <77> tWTCL 3 T + 10 ns Remark T = tCYK <74> <75> <76> <77> TI1n (input) TCLR1n (input) Remark n = 1-4 34 Data Sheet U12036EJ3V1DS00 µPD70F3003 A/D Converter Characteristics (TA = –40 to +70 °C, VDD = AVDD = 5 V ±5 %, VSS = VSS = 0 V) Parameter Resolution Overall error Symbol Conditions — Note 1 Quantize error TYP. Sampling time Zero-scale error Note 1 Note 1 Non-linear error Note 1 Analog input voltageNote 2 MAX. 10 Unit bit — 4.5 V ≤ AVREF1 ≤ AVDD ±0.55 %FSR — 3.5 V ≤ AVREF1 ≤ AVDD ±0.7 %FSR ±1/2 LSB — Conversion time Full-scale error MIN. 4.5 V ≤ AVREF1 ≤ AVDD 48 tCYK 3.5 V ≤ AVREF1 ≤ AVDD 48 tCYK tSAMP 4.5 V ≤ AVREF1 ≤ AVDD 8 tCYK — 3.5 V ≤ AVREF1 ≤ AVDD 8 tCYK — 4.5 V ≤ AVREF1 ≤ AVDD ±3.0 ±4.5 LSB — 3.5 V ≤ AVREF1 ≤ AVDD ±3.0 ±5.5 LSB — 4.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±2.5 LSB — 3.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±4.5 LSB — 4.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±3.5 LSB — 3.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±4.5 LSB tCONV VIAN –0.3 AVDD +0.3 V Reference voltage AVREF1 3.5 AVDD V AVREF1 current AIREF1 1.2 3.0 mA AIDD 2.3 6.0 mA AVDD supply current Notes 1. Except quantize error 2. The conversion result is 000H when VIAN = 0. Converted with 10-bit resolution when 0 < VIAN < AVREF1. The conversion result is 3FFH when AVREF1 ≤ VIAN ≤ AVDD. Data Sheet U12036EJ3V1DS00 35 µPD70F3003 D/A Converter Characteristics (TA = –40 to + 70 °C, VDD = AVDD = 5 V ±5 %, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 bit Resolution — Overall error — Load conditions: 2 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 0.8 % — Load conditions: 2 MΩ, 30 pF AVREF2 = 0.75 VDD AVREF3 = 0.25 VDD 1.0 % — Load conditions: 4 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 0.6 % — Load conditions: 4 MΩ, 30 pF AVREF2 = 0.75 VDD AVREF3 = 0.25 VDD 0.8 % — Load conditions: 2 MΩ, 30 pF 10 µs Settling time Output resistance RO AVREF2 input voltage AVREF2 0.75 VDD VDD V AVREF3 input voltage AVREF3 0 0.25 VDD V AVREF2-AVREF3 resistance value RAIREF 36 10 DACS0, DACS1 = 55H 2 Data Sheet U12036EJ3V1DS00 5 kΩ kΩ µPD70F3003 4.2 Flash Memory Programming Mode Basic Characteristics (TA = 10 to 40 °C (When overwritten), TA = –40 to +70 °C (When not overwritten), VDD = 5 V ±5 %, VSS = 0 V, VPP = 10 V ± 0.3 V) Parameter Symbol Operating frequency fX Supply voltage VDD Conditions MIN. TYP. MAX. Unit 20 25 MHz 4.75 5.25 V VPPL VPP low level detection –0.5 0.2 VDD V VPPM VPP, VDD level detection 0.8 VDD 1.2 VDD V VPPH VPP high voltage detection 9.7 10.3 V 3.0 × φ + 25 mA 100 mA 5 times VDD supply current IDO VPP supply current IPP Number of rewrite CWRT Write time tWRT Note 1 200 500 µs Erasure time tERASE Note 2 20 40 s VPP = 10 V Notes 1. When retried 10 times with 50 µs write time. 2. When retried 20 times with 2 s erasure time. Remark φ: Internal system clock frequency. Data Sheet U12036EJ3V1DS00 37 µPD70F3003 Serial Write Operation Characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD ↑→ RESET ↑ setup time <101> tDRRR 10 ms VPP ↑→ RESET ↑ setup time <102> tPSRR 1.0 µs RESET ↑→ VPP count start time <103> tRRCF 5T + 500 ns Count end time <104> tCOUNT VPP counter width, high <105> tCH 1.0 µs VPP counter width, low <106> tCL 1.0 µs Remark 10 T = t CYK VDD VDD <104> 0V <103> <105> VPPH VPP VPPM <106> VPPL VDD <102> RESET (input) 0V <101> 38 Data Sheet U12036EJ3V1DS00 ms µPD70F3003 5. PACKAGE DRAWING 100 PIN PLASTIC QFP (FINE PITCH) ( 14) A B 75 76 51 50 detail of lead end S C D R Q 26 25 100 1 F G H I J M K P N S L S M NOTE 1. Controlling dimension ITEM millimeter. 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 16.0±0.2 B 14.0±0.2 0.630±0.008 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 16.0±0.2 0.630±0.008 F G 1.0 1.0 0.039 0.039 H 0.22 +0.05 –0.04 0.009±0.002 I 0.10 0.004 J 0.5 (T.P.) 0.020 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N 0.10 0.004 P 1.45±0.05 0.057 +0.003 –0.002 Q 0.125±0.075 0.005±0.003 R S 5°±5° 1.7 MAX. 5°±5° 0.067 MAX. P100GC-50-7EA-3 Data Sheet U12036EJ3V1DS00 39 µPD70F3003 6. RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Table 6-1. Soldering Conditions of Surface Mount Type Soldering Method(s) Soldering Conditions Recommended Conditions Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 secs. max. (210 °C min.), Number of times: twice max., Number of days: 7Note (after that, prebaking is necessary at 125 °C for 10 hours) <Precaution> Products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. IR35-107-2 VPS Package peak temperature: 215 °C, Time: 40 secs. max. (200 °C min.), Number of times: twice max., Number of days: 7Note (after that, prebaking is necessary at 125 °C for 10 hours) <Precaution> Products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. VP15-107-2 Partial pin heating Pin temperature: 300 °C max., Time: 3 seconds max. (per device side) — Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25 °C, 65% RH MAX. Caution 40 Do not use two or more soldering methods in combination. (except partial heating). Data Sheet U12036EJ3V1DS00 µPD70F3003 [MEMO] Data Sheet U12036EJ3V1DS00 41 µPD70F3003 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 42 Data Sheet U12036EJ3V1DS00 µPD70F3003 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U12036EJ3V1DS00 43 µPD70F3003 Related document : µ PD703003 Data Sheet (U12261E) µ PD703003A, 703004A, 703025A Data Sheet (U13188J) (Japanese version) µ PD70F3003A, 70F3025A Data Sheet (U13189E) V850 Family Instruction Table (U10229E) Reference document : Concept of Electrical Characteristics - Microcomputers (IEI-601) (Japanese version) Some of the related documents are preliminary editions but are not so specified here. V850 Family and V853 are trademarks of NEC Corporation. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8