NJM3517 STEPPER MOTOR CONTROLLER / DRIVER ■ GENERAL DESCRIPTION ■ PACKAGE OUTLINE NJM3517 is a stepper motor controller/driver, which requires minimum of external components and drive currents up to 500mA. The NJM3517 is suited for applications requiring least-possible RFI. Operating in a bi-level drive mode can increase motor performance; high voltage pulse is applied to the motor winding at the beginning of a step, in order to give a rapid rise of current. ■ FEATURES • Internal complete driver and phase logic • Continuous-output current NJM3517D2 NJM3517E2 2 x 350mA • Half- and full-step mode generation • LS-TTL-compatible inputs • Bi-level drive mode for high step rates • Voltage-doubling drive possibilities • Half-step position-indication output • Minimal RFI • Packages DIP16 / EMP16 ■ BLOCK DIAGRAM VCC VSS NJM3517 POR RC LA Mono F-F LB STEP DIR HSM Phase Logic PA PB2 PB PB1 INH PA2 OA PA1 OB GND Figure 1. Block diagram NJM3517 ■ PIN CONFIGURATIONS PB2 1 16 VCC PB1 2 15 VSS GND 3 PA1 4 PA2 5 14 LB NJM 3517D2 13 LA 12 RC PB2 1 16 VCC PB1 2 15 VSS GND 3 PA1 4 PA2 5 NJM 3517E2 DIR 6 DIR 6 STEP 7 ØB 8 11 INH 10 HSM STEP 7 ØB 8 14 LB 13 LA 12 RC 11 INH 10 HSM 9 ØA 9 ØA Fugure 2.Pin configurations ■ PIN DESCRIPTION DIP EMP-pack. Symbol Description 1 1 PB2 Phase output 2, phase B. Open collector output capable of sinking max 500 mA. 2 2 PB1 Phase output 1, phase B. Open collector output capable of sinking max 500 mA. 3 3 GND Ground and negative supply for both VCC and VSS. 4 4 PA1 Phase output 1, phase A. 5 5 PA2 Phase output 2, phase A. 6 6 DIR Direction input. Determines in which rotational direction steps will be taken. 7 7 STEP Stepping pulse. One step is generated for each negative edge of the step signal. 8 8 ØB Zero current half step position indication output for phase B. 9 9 ØA Zero current half step position indication output for phase A. 10 10 HSM Half-step mode. Determines whether the motor will be operated in half or full-step mot. When pulled low, one step pulse will correspond to a half step of the motor. 11 11 INH A high level on the inhibit input turns all phase output off. 12 12 RC Bi-level pulse timing pin. Pulse time is approximately ton = 0.55 • RT • CT 13 13 LA Second level (bi-level) output, phase A. 14 14 LB Second level (bi-level) output, Phase B. 15 15 VSS Second level supply voltage, +10 to +40 V. 16 16 VCC Logic supply voltage, nominally +5 V. NJM3517 ■ FUNCTIONAL DESCRIPTION The circuit, NJM3517, is a high performance motor driver, intended to drive a stepper motor in a unipolar, bi-level way. Bi-level means that during the first time after a phase shift, the voltage across the motor is increased to a second voltage supply, VSS, in order to obtain a more-rapid rise of current, see figure 25. The current starts to rise toward a value which is many times greater than the rated winding current. This compensates for the loss in drive current and loss of torque due to the back emf of the motor. After a short time, tOn, set by the monostable, the bi-level output is switched off and the winding current flows from the VMM supply, which is chosen for rated winding current. How long this time must be to give any increase in performance is determined by VSS voltage and motor data, the L/R time-constant. In a low-voltage system, where high motor performance is needed, it is also possible to double the motor voltage by adding a few external components, see figure 4. The time the circuit applies the higher voltage to the motor is controlled by a monostable flip-flop and determined by the timing components RT and CT. The circuit can also drive a motor in traditional unipolar way. An inhibit input (INH) is used to switch off the current completely. ■ LOGIC INPUTS All inputs are LS-TTL compatible. If any of the logic inputs are left open, the circuit will accept it as a HIGH level. NJM3517 contains all phase logic necessary to control the motor in a proper way. STEP — Stepping pulse One step is generated for each negative edge of the STEP signal. In half-step mode, two pulses will be required to move one full step. Notice the set up time, ts, of DIR and HSM signals. These signals must be latched during the negative edge of STEP, see timing diagram, figure 6. VSS D3 VMM + 5V + + VCC NJM3517 + C3 C4 C5 VCC VSS 16 15 D2 D1 R11 R10 PQR RC 12 CMOS, TTL-LS Input / Output-Device R9 R8 RT CT STEP STEP DIR CW / CCW HALF / FULL STEP Mono F-F 6 Phase Logic MOTOR D3-D6 PA 1 PB2 2 PB1 11 5 PA2 9 4 PA1 3 GND 10 INH OA OB 8 (Optional Sensor) LA LB 7 HSM NORMAL /INHIBIT 13 14 PB D3-D6 are UF 4001 or BYV 27 trr < 100 ns GND GND (VCC) GND (VMM,VSS) Figure 3. Typical application VMM + 5V + VCC R1 + C3 NJM3517 D1 C4 VCC VSS 16 15 R10 PQR Q1 12 R9 R8 Mono F-F 13 LA 14 LB + RC CMOS, TTL-LS Input / Output-Device C1 RT CT Q3 R2 STEP CW / CCW HALF / FULL STEP NORMAL /INHIBIT (Optional Sensor) STEP DIR 7 6 Phase Logic PA 1 PB2 2 PB1 11 5 PA2 OA 9 4 PA1 OB 8 HSM 10 INH PB Equal to Phase A 1/2 MOTOR R12 R13 R4 Q5 Q6 R5 3 GND GND GND (VCC) GND (VMM,VSS) Figure 4. Voltage doubling with external transistors NJM3517 DIR — Direction DIR determines in which direction steps will be taken. Actual direction depends on motor and motor connections. DIR can be changed at any time, but not simultaneously with STEP, see timing diagram, figure 6. HSM determines whether the motor will be controlled in full-step or half-step mode. When pulled low, a steppulse will correspond to a half step of the motor. HSM can be changed at any time, but not simultaneously with STEP, see timing diagram, figure 6. INH — Inhibit A HIGH level on the INH input,turns off all phase outputs to reduce current consumption. ■ RESET An internal Power-On Reset circuit connected to Vcc resets the phase logic and inhibits the outputs during power up, to prevent false stepping. ■ OUTPUT STAGES The output stage consists of four open-collector transistors. The second high-voltage supply contains Darlington transistors. ■ PHASE OUTPUT The phase outputs are connected directly to the motor as shown in figure 3. ■ BI-LEVEL TECHNIQUE The bi-level pulse generator consists of two monostables with a common RC network. The internal phase logic generates a trigger pulse every time the phase changes state. The pulse triggers its own monostable which turns on the output transistors for a precise period of time: tOn = 0.55 • CT • RT. See pulse diagrams, figures 7 through 11. ■ BIPOLAR PHASE LOGIC OUTPUT The ØA and ØB outputs are generated from the phase logic and inform an external device if the A phase or the B phase current is internally inhibited. These outputs are intended to support if it is legal to correctly go from a halfstep mode to a full-step mode without loosing positional information. The NJM3517 can act as a controller IC for 2 driver ICs, the NJM3770A. Use PA1 and PB1 for phase control, and ØA and ØB for I0 and I1 control of current turnoff. NJM3517 ■ ABSOLUTE MAXIMUM RATINGS Parameter Pin No. Symbol Min Max Unit Voltage Logic supply 16 VCC 0 7 V Second suppl 15 VSS 0 45 V Logic input 6, 7, 10, 11 VI -0.3 6 V Phase output 1, 2, 4, 5 IP 0 500 mA Second-level output 13, 14 IL -500 0 mA Current Logic input 6, 7, 10, 11 II -10 The zero output 8, 9 IΟ - 6 mA mA Temperature Tj -40 +150 °C TStg -55 +150 °C Power dissipation at Ta = 25°C, DIP package. Note 2. PD - 1.6 W Power dissipation, EMP package. Note 3. PD - 1.3 W Min Typ Max Unit 4.75 10 0 -350 -20 400 800 5 - 5.25 40 350 0 +125 - V V mA mA °C ns ns Operating junction temperature Storage temperature Power Dissipation (Package Data) ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Logic supply voltage Second-level supply voltage Phase output current Second-level output current Operating junction temperature Set up time Step pulse duration VCC VSS IP IL TJ ts tp tr ISS tf VI ICC NJM3517 VCC VSS 16 15 VLCE Sat HSM or DIR t POR RC 12 Mono F-F 13 LA IL 14 LB ILL STEP VSS VCC STEP 7 DIR 6 II IIL IIH VI Phase Logic PA 1 PB2 2 PB1 HSM 10 INH 11 5 PA2 OA 9 4 PA1 OB 8 3 GND PB VIL IP IPL VPCE Sat VIH t IP VP VL ts t tp VOCE Sat td Figure 5. Definition of symbols Figure 6. Timing diagram NJM3517 ■ ELECTRICAL CHARACTERISTICS Electrical characteristics at Tj = +25°C, VCC = +5.0 V, VMM = +40 V, VSS = +40 V unless otherwise specified. Parameter Supply current Symbol ICC Min Typ Max Unit INH = LOW Conditions - 45 60 mA INH = HIGH - 12 - mA Phase outputs Saturation voltage VPCE Sat IP = 350 mA - - 0.85 V Leakage current IPL VP = 0 V - - 500 µA Turn on, turn off td +70°C - - 3 µs td +125°C - - 6 µs Saturation voltage VLCE Sat IL = -350 mA - - 2.0 V Leakage current ILL VL = 0 V -500 - - µA On time tOn (note 4) 220 260 300 µs - 2.0 - V Second-level outputs Logic inputs Voltage level, HIGH VIH Voltage level, LOW VIL - - 0.8 V Input current, LOW IIL VI = 0.4 V -400 - - µA Input current, HIGH IIH VI = 2.4 V - - 20 µA VØCE Sat IØ = 1.6 mA - - 0.4 V Logic outputs Saturation voltage Notes 1. All voltages are with respect to ground. Current are positive into, negative out of specified terminal. 2 Derates at 12,8 mW/°C above +25°C. 3. Derates at 10.4 mW/°C above +25°C. 4. RT = 47 kΩ, CT = 10 nF. NJM3517 ■ PURPOSE OF EXTERNAL COMPONENTS For figures 3 and 4. Note that “Larger than …” is normally the vice versa of “Smaller than … .” Component Purpose Value Larger than value Smaller than value D1, D2 Passes low power to motor and prevents high power from shorting through low power supply I f = 1A Increases price Decreases max current capability Inductive current supressor I f = 1A Increases price Decreases current turn-off capability trr = 100nS Slows down turnoff time. Voltage at anode might exceed voltage breakdown Speeds up turnoff time. 2 Slows down Q1’s turn-on and Q4’s turn-off time. Speeds up Q1’s turn-on and Q4’s turn-off time. 2 Slows down Q1’s turn-off and Q4’s turn-on time. Speeds up Q1’s turn-off and Q4’s turn-on time. Decreases ext. transistor IC max. Lowers 3517 power dissipation. Increases ext. transistor IC max. Increases 3517 power dissipation. Increases noise sensitivity, worse logic-level definition Increases noise immunity, better logic-level definition. D3 … D6 1N4001, UF4001 e.g. R1 Base drive current limitter BYV27 UF4001 RGPP10G RGPP30D R = 20ohm ( Vmm P = R1 R2, R3 Base discharge resistor R = 240ohm ( Vmm P = R1 R4 … R7 ) R1 + R2 ) R1 + R2 External transistor base Vmm- Vbe- V ce R= driver Vbe I4 R12 2 P > (I 4) • R4 ( ) Check hfe. R8, R9 ØA, ØB pull-up resistors R = 5kohm @ pull-up voltage = 5V. P= R10, R11 2 (VCC) R Less stress on ØA, Stress on ØA, ØB output ØB output transistors. transistors Vmm-VMotor -VCESat Decreases motor Limit max. motor current. Resistors may R = current. I Motor max be omitted. (Check motor specifications first.) Vbe R12 … R15 External transistor base R= = 15 Ω discharge. I12 Slows down external transistor turn-off time. Lowers 3517 power dissipation P > Vbe• I12 RT, CT Sets LA and LB on time R = 47kohm, C = 10nf when triggered by P < 250mW STEP. C1, C2 Stores the doubling voltage. C3 … C5 Increases on time. Decreases on time. VC ≥ 45V Increases price, better filtering, decreases risk of IC breakdown VRated >V ,V or Vcc Increases price mm ss Activation transistor of voltage doubling. Q3, Q4 Charging of voltage doubling capacitor Q5 … Q8 Motor current drive transistor. Speeds up external transistor turn-off time. Increases 3517 power dissipation Increases effective Decreases effective on-time on-time during during voltage voltage doubling doubling. C = 100µ F C ≥ 10 µ F Filtering of supplyvoltage ripple and takeup of energy feedback from D3 … D6 Q1, Q2 Increases motor current. IC as motor requires. I C= IC as motor requires. PNP power trans. Increases price. Decreases price, more compact solution. Risk for capacitor breakdown. Decreases max Im during voltage doubling. (Vmm - Vf -VCE ) • C1 ( ) 1 - 0.55 • RT • CT fStep Increases max Decreases max current capability. current capability. NJM3517 DIR INH HSM STEP H L H P DIR INT HSM STEP L L H P OB LB PB1 PB2 PA1 PA2 LA OA L P P P P P P L OB LB PB1 PB2 PA1 PA2 LA OA L P P P P P P L Figure 7. Full-step mode, forward. 4-step sequence. Gray-code Figure 8. Full-step mode, reverse. 4-step sequence. Gray+90° phase shift. code -90° phase shift. DIR INH HSM STEP H L L P OB LB PB1 PB2 PA1 PA2 LA OA P P P P P P P P DIR INH HSM STEP L L L P OB LB PB1 PB2 PA1 PA2 LA OA P P P P P P P P C C Figure 9. Half-step mode, forward. 8-step sequence. DIR INH HSM STEP L H L P OB LB PB1 PB2 PA1 PA2 LA OA P P H H H H P P Figure 10. Half-step mode, reverse. 8-step sequence. C Figure 11. Half-step mode, inhibit. ■ APPLICATIONS INFORMATION Logic inputs If any of the logic inputs are left open, the circuit will treat it as a high-level input. Unused inputs should be connected to proper voltage levels in order to get the highest noise immunity. Phase outputs Phase outputs use a current-sinking method to drive the windings in a unipolar way. A common resistor in the center tap will limit the maximum motor current. Fast free-wheeling diodes must be used to protect output transistors from inductive spikes. Series diodes in VMM supply, prevent VSS voltage from shorting through the VMM power supply. However, these may be omitted if no bi-level is used. The VSS pin must not be connected to a lower voltage than VMM, but can be left unconnected. Zero outputs ØA and ØB, “zero A” and “zero B,” are open-collector outputs, which go high when the corresponding phase output is inhibited by the half-step-mode circuitry. A pull-up resistor should be used and connected to a suitable supply voltage (5 kohms for 5V logic). See “Bipolar phase logic output.” Interference To avoid interference problems, a good idea is to route separate ground leads to each power supply, where the only common point is at the NJM3517’s GND pin. Decoupling of VSS and VMM will improve performance. A 5 kohm pull-up resistor at logic inputs will improve level definitions, especially when driven by open-collector outputs. NJM3517 RExt Figure 12. Diode turn-off circuit VZ R i Figure 13. Resistance turn-off circuit V1 CS Figure 14. Zener diode turn-off circuit V2 0V Power supply Figure 15. Power return turn-off circuit Figure 16. Power return turn-off circuit for bi-level ■ INPUT AND OUTPUT SIGNALS FOR DIFFERENT DRIVE MODES The pulse diagrams, figures 7 through 10, show the necessary input signals and the resulting output signals for each drive mode. On the left side are the input and output signals, the next column shows the state of each signal at the cursor position marked “C.” STEP is shown with a 50% duty cycle, but can, of course, be with any duty cycle, as long as pulse time (tp) is within specifications. PA and PB are displayed with low level, showing current sinking. LA and LB are displayed with high level, showing current sourcing. ■ USER HINTS 1. Never disconnect ICs or PC-boards when power is supplied. 2. If second supply is not used, disconnect and leave open VSS, LA, LB, and RC. Preferably replace the VMM supply diodes (D1, D2) with a straight connection. 3. Remember that excessive voltages might be generated by the motor, even though clamping diodes are used. 4. Choice of motor. Choose a motor that is rated for the current you need to establish desired torque. A high supply voltage will gain better stepping performance. If the motor is not specified for the VMM voltage, a current limiting resistor will be necessary to connect in series with center tap. This changes the L/R time constant. 5. Never use LA or LB for continuous output at high currents. LA and LB on-time can be altered by changing the RC net. An alternative is to trigger the mono-flip-flop by taking a STEP and then externally pulling the RC pin (12Pin) low (0V) for the desired on-time. 6. Avoid VMM and VSS power supplies with serial diodes (without filter capacitor) and/or common ground with VCC. The common place for ground should be as close as possible to the IC’s ground pin (pin 3). NJM3517 7. To change actual motor rotation direction, exchange motor connections at PA1 and PA2 (or PB1 and PB2). 8. Half-stepping. in the half-step mode, the power input to the motor alternates between one or two phase windings. In half-step mode, motor resonances are reduced. In a two-phase motor, the electrical phase shift between the windings is 90 degrees. The torque developed is the vector sum of the two windings energized. Therefore, when only one winding is energized, which is the case in half-step mode for every second step, the torque of the motor is reduced by approximately 30%. This causes a torque ripple. 9. Ramping. Every drive system has inertia which must be considered in the drive scheme. The rotor and load inertia plays a big role at higher speeds. Unlike the DC motor, the stepper motor is a synchronous motor and does not change speed due to load variations. Examination of typical stepper motors’ torque versus speed curves indicates a sharp torque drop-off for the start-stop without error curve. The reason for this is that the torque requirements increase by the cube of the speed change. As it can be seen, for good motor performance, controlled acceleration and deceleration should be considered. ■ COMMON FAULT CONDITIONS • VMM supply not connected, or VMM supply not connected through diodes. • The inhibit input not pulled low or floating. Inhibit is active high. • A bipolar motor without a center tap is used. Exchange motor for unipolar version. Connect according to figure 3. • External transistors connected without proper base-current supply resistor. • Insufficient filtering capacitors used. • Current restrictions exceeded. • LA and LB used for continuous output at high currents. Use the RC network to set a proper duty cycle according to specifications, see figures 19 through 24. • A common ground wire is used for all three power supplies. If possible, use separate ground leads for each supply to minimize power interference. ■ DRIVE CIRCUITS If high performance is to be achieved from a stepper motor, the phase must be energized rapidly when turned on and also de-energize rapidly when turned off. In other words, the phase current must increase/decrease rapidly at phase shift. ■ PHASE TURN-OFF CONSIDERATIONS When the winding current is turned off the induced high voltage spike will damage the drive circuits if not properly suppressed. Different turn-off circuits are used; e. g. : Diode turn-off circuit (figure 12) — Slow current decay — Energy lost mainly in winding resistance — Potential cooling problems. Resistance T O C (figure 13) — Somewhat faster current decay — Energy lost mainly in R-Ext — Potential cooling problems Zener diode T O C (figure 14) Relatively high VZ gives: — Relatively fast current decay — Energy lost mainly in VZ — Potential cooling problems NJM3517 ■ TYPICAL CHARACTERISTICS Allowable power dissipation [W] VLCE sat [V] Output Current [A] 2.5 0.5 2.0 0.4 1.5 1.5 0.3 1.0 1.0 0.2 0,5 0,5 0.1 2.5 TA= +25° C 2.0 0 0 0.1 0.2 0.3 0.4 0.5 0 0 50 IL [A] 100 150 0 0.2 0.4 Ambient temrature [°C] Output Current [mA] Output Pulse Width [s] TA= +25° C 10 10 -1 10 -1 10 -2 M 6 t= 10 R 10 -3 t= R t= R 4 10 -4 t= R 2 1.0 1 1 TA= +25° C 0.8 Figure 19. Typical phase output saturation voltage vs. output current Output Pulse Width [s] 10 0.6 Output Voltage [V] Figure 18. Power dissipation vs. Ambient temrature. Figure 17. Typical second output saturation voltage vs. output current 8 0 TA= +25° C 0k 10 TA= +25° C 0% 10 10 -2 Du % tyc yk 50 le % k 10 10 -3 1k 10 -4 1% 25 % 10 -5 10 -5 10 -6 10 -6 0. 1% 0 0 0.2 0.4 0.6 0.8 1.0 0.01 0.1 Output Voltage [V] Figure 20. Typical IØ vs. VØCE Sat. “Zero output” saturation 10 100 1000 0.001 0.01 Output Current [A] 0.1 1 10 100 fs Step frequency [kHz] Figure 21. Typical tOn vs. CT/RT. Output pulse width vs. capacitance/resistance (IL= 0) Output Current [A] 1 Ct Capacitance [nF] Figure 22.Typical ton vs. fs/dc. Output pulse width vs.step frequency/duty (Ip = 0) -0.5 0.5 Motor Current [mA] TA= +25° C 0.4 TA= +25° C -0.4 Normal 10% 50% 100% Bilevel -0.3 0.3 Bilevel without time limit 350 0.2 -0.2 0.1 -0.1 0 0 0.2 0.4 0.6 0.8 1.0 Power Dissipation [W] Figure 23. Typical PDP vs. IP. Power dissipation without second-level supply (includes 2 active outputs = FULL STEP) 0 0 0.2 0.4 0.6 0.8 1.0 tON Time Power Dissipation [W] Figure 24. Typical PDL vs. IL. Power dissipation in the bilevel pulse when raising to the IL value. One active output Figure 25 . Motor Current IP NJM3517 Power return T O C for unipolar drive (figure 15) Relatively high VZ gives: — Relatively fast current decay — Energy returned to power supply — Only small energy losses — Winding leakage flux must be considered — Potential cooling problems Power return to T O C for bi-level drive (figure 16) — Very fast current decay — Energy returned to power supply — Only small energy losses — Winding leakage flux must be considered ■ DIAGRAMS How to use the diagrams: 1. What is the maximum motor current in the application? • The ambient temperature sets the maximum allowable power dissipation in the IC, which relates to the motor currents and the duty cycle of the Bi-level function. For NJM3517, without any measures taken to reduce the chip temperature via heatsinks, the power dissipation vs. temperature follows the curve in figure 18. • Figures 23 and 24 give the relationship between motor currents and their dissipations. The sum of these power dissipations must never exceed the previously-established value, or life expectancy will be drastically shortened. • When no Bi-level or voltage doubling is utilized, the maximum motor current can be found directly in figure 23 . 2. How to choose timing components. • Figure 21 shows the relationship between CT, RT, and tOn. Care must be taken to keep the tOn time short, otherwise the current in the winding will rise to a value many times the rated current, causing an overheated IC or motor. 3. What is the maximum tOn pulse-width at a given frequency? • Figure 22 shows the relationship between duty cycle, pulse width, and step frequency. Check specifications for the valid operating area. 4. Figures 17, 18 and 20 show typical saturation voltages vs. output current levels for different output transistors. 5. Shaded areas represent operating conditions outside the safe operating area. The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.