NJU8402 PRELIMINARY DIGITAL TO ANALOG CONVERTER FOR STEREO AUDIO ■ GENERAL DESCRIPTION ■ PACKAGE OUTLINE The NJU8402 is a 16-bit delta-sigma Digital-to-Analog Converter for stereo audio. It consists of Serial Audio Data Interface, Digital Interpolation Filter, ∆Σ Modulator, SC LPF, Buffer Amp, System Controller for status control. It operates on single +5V power supply. Furthermore, it accepts 16-bit input audio data length or 18-bit, and supports I2S serial data format and LSB justified. Therefore, the NJU8402 is suitable for CD, MD, DAT and other digital audio applications. NJU8402D ■ FEATURES ● ● ● ● ● ● ● ● NJU8402M ■ PIN CONFIGURATION ∆Σ type 1bit stereo DAC Sample Rate ( fs ) : 50kHz ( Maximum ) Signal-to-Noise Ratio : 94dB Input Audio Data Length : 16bits or 18bits Single ended Analog Output Internal SC type Low Pass Filter Operating Voltage +5V ±5% Package Outline DIP16 / DMP16 VDD 1 16 VSS MCKI 2 15 BCLK SCK 3 14 LRCK DATA 4 13 DIN REQ 5 12 RST AOUTL 6 11 AOUTR VCOML 7 10 VCOM AVDD 8 9 AVSS ■ BLOCK DIAGRAM SC LPF ∆Σ Modulator SC LPF LPF AOUTL VCOML LPF AOUTR VCOMR AVSS AVDD System Controller VSS LRCK Serial Audio Data Interface ∆Σ Modulator VDD BCLK Digital Interpolation Filter SCK REQ MCKI RST DATA DIN -1- NJU8402 ■ TERMINAL DESCRIPTION VDD VSS AVDD AVSS MCKI INPUT /OUTPUT I 13 DIN I 14 LRCK I 15 BCLK I 3 SCK I 4 DATA I 5 REQ I 12 RST I 7 VCOML 10 VCOMR 6 11 AOUTL AOUTR O O PIN No. 1 16 8 9 2 -2- SYMBOL FUNCTION Digital Power Supply, +5V Digital GND, 0V Analog Power Supply, +5V Analog GND, 0V Master Clock Input Terminal The input signal frequency is 256 times or 384 times of fs. Serial Audio Data Input Terminal L/R Channel Clock Input Terminal This clock must synchronize with MCKI. Audio Serial Data Clock Input Terminal This clock must synchronize with MCKI. Control Register Serial Data Sift Clock Input Terminal Control register leads the control data synchronizing the rising edge of SCK signal. When the control register is not used, the state of SCK terminal has to keep level ”H”. Control Register Serial Data Input Terminal Input data sets various functions. When the control register is not used, the state of DATA terminal has to keep level “H”. Control Register Serial Data Request Input Terminal The control data are latched in the control register at the rising edge of REQ signal. When the control register is not used, the state of REQ terminal has to keep level “H”. Reset “L” level signal into reset terminal initializes the system. Left channel Analog Signal Common Terminal for Connecting Smooth Capacitor A chemical capacitor should be connected between this terminal and AVSS for stabilizing. Right Channel Analog Signal Common Terminal for Connecting Smooth Capacitor A chemical capacitor should be connected between this terminal and AVSS for stabilizing. L-Channel Analog Signal Output Terminal R-Channel Analog Signal Output Terminal NJU8402 ■ FUNCTION DESCRIPTION (1-1) Analog Audio Signal Output Analog signal output is biased in the chip and the maximum amplitude is 0.56 × AVDD. The internal switched capacitor Low Pass Filter is so effective that the external Low Pass Filters are required only 2pole LPF or 3-pole. (1-2) Serial Data Interface DIN (Data Input), BCLK (Bit Clock) and LRCK (L/R Clock) are the serial data interface terminals. BCLK is the bit clock of audio data and IO data are leaded at raising edge of the BCLK. The signal into LRCK terminal represents the signal for distinguishing between Lch and Rch, and the signal for starting data. The frequency of LRCK is sampling rate of system ( fs ). The MCIK must be synchronized with LRCK and is 256 times or 384 of fs. The serial data format is complement of 2, MSB-first and compatible with I2S serial data protocol or LSB justified. This serial data format is set by the control register. LRCK Right Channel Left BCLK DIN 151413 1 0 151413 1 0 I2S serial data format LRCK Right Channel Left BCLK DIN 0 1514 2 1 0 1514 2 1 0 LSB justified serial data format (1-3) System Clock System Clock into the MCIK terminal must be 256 times or 384 times of fs and synchronizing with LRCK. This frequency is set by the control register. (1-4) Reset The external reset is the asynchronous reset. Reset is released at the falling edge at LRCK. Reset by command is synchronous which operates as same as the external reset function. -3- NJU8402 (1-5) Control Register The Control Register controls NJU8402 operation using the serial interface. The SCK terminal is the data sift clock, the REQ terminal is data request signal, the DATA terminal is the serial data input. The control data is loaded into the sift register at rising edge of SCK, then it is latched at the rising edge of REQ. The least 8-bit data, which order is MSB first, is valid for control. REQ SCK DATA B7 B6 B5 B4 B3 B2 B1 B0 CONTROL PORT TIMING CHART • Serial Data Format B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 ∗ DIF1 DIF0 CLKR 0 0 0 1 ∗ ∗ ∗ RST (∗: Don’t Care) *1 Don't input commands except this table. 0 1 Default System Clock CLKR 256fs 384fs 0 Data Length DIF0 16 18 0 Format DIF1 I2S LSB Justified 0 Reset RST Normal Reset *2 *2 The level becomes 0 after initial setting. -4- NJU8402 ■ ABSOLUTE MAXIMUM RATING (VSS=AVSS=0V) PARAMETER SYMBOL CONDITIONS UNIT DIGITAL VDD −0.3 to+7.0 V ANALOG AVDD −0.3 to +7.0 V VDD - AVDD ∆VAVD VDD - AVDD<0.2 V Input Voltage VIN −0.3 to VDD + 0.3 V Operating Temperature Ta −30 to +80 °C Storage Temperature Tstg −40 to +125 °C Power Consumption PD Power Supply 500（DIP16） mW 200(DMP16) ■ RECOMMENDATION OPERATION CONDITION (VSS=AVSS=0V) PARAMETER Power Supply SYMBOL MIN. CONDITIONS TYP. MAX. UNIT DIGITAL VDD 4.75 5.0 5.25 V ANALOG AVDD 4.75 5.0 5.25 V -5- NJU8402 ■ ELECTRICAL CHARACTERISTICS • ANALOG AC CHARACTERISTICS (The case without the report Ta=25℃,VDD=AVDD=5.0V,fs=44.1kHz, Input Signal Frequency=1kHz, Input Signal Level=Full Scale,MCKI=256fs,Bandwidth=22Hz to 20kHz) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Resolution 16 bit S/N S/N EIAJ, A-weight 90 94 dB Dynamic Range DR EIAJ, A-weight 94 dB THD+N THD+N Output 0dB dB −88 −82 Channel Separation EIAJ(1kHz) 90 dB Differential Gain 0.1 0.3 dB Between Channels Gain Drift 100 ppm/°C Maximum Output Voltage 0.55×AVDD 0.57×AVDD 0.59×AVDD VPP Bias V 0.50×AVDD Output Load Resistance 10 kΩ Output Load Capacitance 300 pF BLOCK DIAGRAM FOR TESTING ANALOG AC CHARACTERISTICS Digital Data Digital Audio Interface Receiver Chip NJU8402 Two-pole LPF NJU8402 Evaluation Board Two-pole LPF Filters -6- Filters THD Meter Audio Analyzer : fc=25kHz ( refer ■APPLICATION CIRCUITS ) : 22Hz HPF ＋ 20kHz Ten-pole LPF ( A-Weighting Filter is on at measuring S/N and Dynamic Range ） NJU8402 • DIGITAL INTERPOLATION FILTER CHARACTERISTICS (The case without the report. Ta=25℃,VDD=AVDD=5.0V,fs=44.1kHz) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Band Pass PB 0.02 20.0 kHz Rejection Band SB 24.10 kHz Rejection Band Quantity SA 50 dB Note :Band Pass and Rejection Band are proportioned to fs. PB=0.4535×fs,SB=0.5465×fs • DIGITAL ANALOG LOW PASS FILTER CHARACTERISTIC PARAMETER Frequency Response (The case without the report. Ta=25℃,VDD=AVDD=5.0V,fs=44.1kHz) SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE FR dB 22Hz～20kHz ±0.2 • POWER CHARACTERISTICS PARAMETER Supply Voltage VDD Supply Current AVDD (The case without the report Ta=25℃,VDD=AVDD=5.0V,fs=44.1kHz) SYMBOL CONDITIONS MIN. TYP. MAX． UNIT NOTE VDD, AVDD 4.75 5.0 5.25 V IDD No signal 12 14 mA AIDD No signal 10 18 mA • DIGITAL DC CHARACTERISTICS PARAMETER Digital Input Voltage Input Leakage Current SYMBOL VIH VIL ILK CONDITIONS (The case without the report Ta=25℃,VDD=AVDD=5.0V) MIN． TYP． MAX． UNIT NOTE ― VDD 0.7 VDD V 0.3 VDD V ― ― ― ±1 µA -7- NJU8402 • DIGITAL AC CHARACTERISTICS (The case without the report Ta=25℃,VDD=AVDD=5.0V) Master Clock & Reset PARAMETER Frequency MCKI Pulse Width High-Level Pulse Width Low-Level Reset Low Level Width SYMBOL CONDITIONS 256fs fMCKI 386fs tMCKH MIN. 1.024 9.216 20 TYP. ― ― ― MAX. 12.8 19.2 ― UNIT MHz MHz ns tMCKL 20 ― ― ns tRST 1 ― ― ns NOTE Digital Audio Signal Interface PARAMETER Audio DAC Sampling Late Audio Data Setup Time Audio Data Hold Time BLCK Period BLCK Pulse Time “H” BLCK Pulse Time “L” BCLK Rise to LRCK Edge LRCK Edge to BCLK Rise SYMBOL CONDITIONS fs tDS tDH tBCLK tBCKH tBCKL tBLR tLRB MIN. 24 50 50 1/(128fs) 20 20 40 40 TYP. ― ― ― ― ― ― ― ― MAX. 50 ― ― ― ― ― ― ― UNIT kHz ns ns ns ns ns ns ns NOTE Control Register Interface PARAMETER SCK Period SCK Pulse Time “H” SCK Pulse Time “L” Control Data Setup Time Control Data Hold Time REQ Pulse Time “H” SCK Data Setup Time REQ Hold Time SYMBOL CONDITIONS tSCK tSCH tSCL tDAS tDAH tREH tRQS tRQH MIN. 2 0.8 0.8 0.8 0.8 1.6 0.8 0.8 TYP. ― ― ― ― ― ― ― ― MAX. ― ― ― ― ― ― ― ― UNIT ns ns ns ns ns ns ns ns NOTE Input Signal Rise and Fall Time PARAMETER Input Signal Rise Time Input Signal Fall Time SYMBOL CONDITIONS tUP tDN MIN. ― ― TYP. ― ― MAX. 100 100 UNIT ns ns NOTE -8- NJU8402 • TIMING CHART 1/fMCKI Master Clock & Reset MCKI tMCKL tMCKH tRST RSTX tBCLK Digital Audio Signal Interface BCLK INPUT tBLR tLRB tBCKL tBCKH LRCK INPUT tDS tDH DIN tLRD0 Control Register Interface tRQH tREH tRQS REQ tSCL tSCH SCK tSCK DATA tDAS tDAH Input Signal Rise and Fall Time 90% 10% tUP tDN -9- NJU8402 ■ APPLICATION CIRCUITS +12 Two-pole LPF 10uF 20kΩ 2.2uF 20kΩ DIN Digital Audio Data (16 or 18 bits) 0.1uF 150pF 20kΩ AOUTL OP 680pF LRCK 10uF OP:NJM5532 BCLK 0.1uF -12V VCOML 10uF NJU8402 Two-pole LPF AOUTR SCK VCOMR 10uF AVDD(+5V) REQ AVDD MCK & 8 bits Serial Control 10uF MCKI 0.1uF AVSS VDD (+5V) RSTX AVSS (Analog GND) VDD 10uF 0.1uF VSS DATA VSS (Digital GND) [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 10 -