PCM1680 www.ti.com SLES133 – MARCH 2005 24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma, Audio Digital-to-Analog Converter FEATURES • • • • • • • • 24-Bit Resolution Analog Performance: – Dynamic Range: 105 dB Typical – SNR: 105 dB Typical – THD+N: 0.002% Typical – Full-Scale Output: 3.9 Vp-p Typical 4×/8× Oversampling Interpolation Filter: – Stop-Band Attenuation: –50 dB – Pass-Band Ripple: ±0.04 dB Sampling Frequency: 5 kHz to 200 kHz System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, or 1152 fS With Autodetect Zero Flags for Selectable Channel Combinations Serial Port (SPI/I2C) for Mode Control User-Programmable Functions: – Flexible Audio Data Formats • Right-Justified, I2S, and Left-Justified • 16-, 18-, 20-, and 24-Bit Audio Data – Digital Attenuation: Mode Selectable • 0 dB to –63 dB, 0.5 dB/step • 0 dB to –100 dB, 1 dB/step – Soft Mute – Digital De-Emphasis – Digital Filter Rolloff: Sharp or Slow • • • Single Power-Supply Operation: 5-V Analog, 5-V Digital Package: 28-Lead SSOP (150 mil) Pin-Compatible With PCM1780 APPLICATIONS • • • • • • • Integrated A/V Receivers DVD Movie and Audio Players HDTV Receivers Car Audio Systems DVD Add-On Cards for High-End PCs Digital Audio Workstations Other Multichannel Audio Systems DESCRIPTION The PCM1680 is a CMOS monolithic integrated circuit which features eight 24-bit audio digital-to-analog converters and support circuitry in a small 28-lead SSOP. The digital-to-analog converters use TI's enhanced multilevel delta-sigma architecture to achieve excellent signal-to-noise performance and a high tolerance to clock jitter. The PCM1680 accepts industry-standard audio data formats with 16- to 24-bit audio data. Sampling rates up to 200 kHz are supported. The PCM1680 provides a full set of user-programmable functions through a serial control port, SPI or I2C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated PCM1680 www.ti.com SLES133 – MARCH 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) PCM1680 Supply voltage: VCC1, VCC2, VDD –0.3 V to 6.5 V Supply voltage differences: VCC1, VCC2, VDD ±0.1 V Ground voltage differences: AGND1, AGND2, DGND ±0.1 V Input voltage to digital pins –0.3 V to VDD + 0.3 V, < 6.5 V Input voltage to analog pins –0.3 V to VCC + 0.3 V, < 6.5 V ± 10 mA Input current (any pins except supplies) Operating temperature –40°C to 110 °C Storage temperature –55°C to 150 °C 150 °C Junction temperature Lead temperature (soldering) 260°C, 5 s Package temperature (IR reflow, peak) (1) 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range MIN NOM MAX UNIT Analog supply voltage, VCC1, VCC2 4.75 5 5.25 V Digital supply voltage, VDD 4.75 5 5.25 V Digital input logic family Digital input clock frequency TTL System clock Sampling clock Analog output load resistance 8.192 36.864 MHz 32 192 kHz 5 kΩ Analog output load capacitance Digital output load capacitance Operating free-air temperature, TA –25 50 pF 20 pF 70 °C ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VCC = VDD = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP RESOLUTION MAX 24 UNIT Bits DATA FORMAT Audio data interface format Audio data bit length Audio data format fS Sampling frequency System clock frequency 2 Right-justified, I2S, left-justified 16, 18, 20, or 24 bits, selectable MSB-first, 2s complement 5 128, 192, 256, 384, 512, 768, 1152 fS 200 kHz PCM1680 www.ti.com SLES133 – MARCH 2005 ELECTRICAL CHARACTERISTICS (continued) all specifications at TA = 25°C, VCC = VDD = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family VIH 2 Input logic level VIL IIH (1) IIL TTL compatible VIN = VCC (1) IIH (2) 0.8 Input logic current VIN = 0 V IOH = –1 mA Output logic level –10 VIN = VCC VOH (3) VOL (4) 10 VIN = 0 V IIL (2) Vdc 65 100 µA –10 2.4 IOL = 1 mA 0.4 Vdc DYNAMIC PERFORMANCE (5) THD+N Total harmonic distortion + noise VOUT = 0 dB, fS = 48 kHz 0.002% VOUT = 0 dB, fS = 96 kHz, system clock = 256 fS 0.003% VOUT = 0 dB, fS = 192 kHz, system clock = 128 fS 0.004% EIAJ, A-weighted, fS = 48 kHz Dynamic range Signal-to-noise ratio 103 A-weighted, fS = 192 kHz, system clock = 128 fS 102 100 103 A-weighted, fS = 192 kHz, system clock = 128 fS 102 94 dB 105 A-weighted, fS = 96 kHz, system clock = 256 fS fS = 48 kHz Channel separation 105 A-weighted, fS = 96 kHz, system clock = 256 fS EIAJ, A-weighted, fS = 48 kHz SNR 100 0.008% dB 103 fS = 96 kHz, system clock = 256 fS 101 fS = 192 kHz, system clock = 128 fS 100 dB DC ACCURACY Gain error ±1 ±6 % of FSR Gain mismatch, channel-to-channel ±1 ±6 % of FSR ±30 ±80 mV Bipolar zero error VOUT = 0.49 VCC at BPZ input ANALOG OUTPUT Output voltage Full scale (–0 dB) Bipolar zero voltage Load impedance AC-coupled load 0.78 VCC Vp-p 0.49 VCC Vdc 5 kΩ DIGITAL FILTER PERFORMANCE Filter Characteristics (Sharp Rolloff) Pass band ±0.04 dB Stop band 0.454 fS 0.546 fS ±0.04 Pass-band ripple Stop-band attenuation (1) (2) (3) (4) (5) Stop band = 0.546 fS –50 dB dB Pins 5, 6, 7, 8, 11, 12, 13: SCK, DATA1, BCK, LRCK, DATA2, DATA3, DATA4 Pins 2, 3, 4, 14: MS/ADR, MC/SCL, MD/SDA, MSEL Pins 1, 28: ZERO1, ZERO2 Pins 1, 4, 28: ZERO1, MD/SDA, ZERO2 Analog performance characteristics are measured using the System Two™ Cascade audio measurement system by Audio Precision™. 3 PCM1680 www.ti.com SLES133 – MARCH 2005 ELECTRICAL CHARACTERISTICS (continued) all specifications at TA = 25°C, VCC = VDD = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Filter Characteristics (Slow Rolloff) Pass band ±0.5 dB 0.198 fS Stop band 0.884 fS ±0.5 Pass-band ripple Stop-band attenuation Stop band = 0.884 fS –35 dB dB Delay time 20/fS De-emphasis error ±0.1 dB ANALOG FILTER PERFORMANCE Frequency response at 20 kHz –0.02 at 44 kHz –0.07 dB POWER SUPPLY REQUIREMENTS VDD VCC Voltage range 4.75 5 5.25 4.75 5 5.25 91 110 fS = 48 kHz IDD + ICC Supply Current Power dissipation fS = 96 kHz, system clock = 256 fS 102 fS = 192 kHz, system clock = 128 fS 106 fS = 48 kHz 455 fS = 96 kHz, system clock = 256 fS 510 fS = 192 kHz, system clock = 128 fS 530 Vdc mA 605 mW TEMPERATURE RANGE Operation temperature θJA –25 Thermal resistance PCM1680 (TOP VIEW) ZERO1 MS/ADR MC/SCL MD/SDA SCK DATA1 BCK LRCK VDD DGND DATA2 DATA3 DATA4 MSEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ZERO2 VOUT1 VOUT2 VCOM AGND2 VCC2 VOUT3 VOUT4 VOUT5 VOUT6 AGND1 VCC1 VOUT7 VOUT8 P0015-01 4 70 70 °C °C/W PCM1680 www.ti.com SLES133 – MARCH 2005 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION AGND1 18 – Analog ground AGND2 24 – Analog ground BCK 7 I Shift clock input for serial audio data DATA1 6 I Serial audio data input for VOUT1 and VOUT2 (1) DATA2 11 I Serial audio data input for VOUT3 and VOUT4 (1) DATA3 12 I Serial audio data input for VOUT5 and VOUT6 (1) DATA4 13 I Serial audio data input for VOUT7 and VOUT8 (1) DGND 10 – Digital ground LRCK 8 I Left and right clock input. The frequency of this clock is equal to the sampling rate, fS. MC/SCL 3 I MD/SDA 4 I/O (1) Shift clock input for SPI, serial clock input for (1) I2C (1) (2) Serial data input for SPI, serial data input/output for I2C (1) (2) (3) I2C (1) (4) MS/ADR 2 I Select input for SPI, address input for MSEL 14 I I2C/SPI select (1)(4) SCK 5 I System clock input. Input frequency is 128, 192, 256, 384, 512, 768, or 1152 fS. VCC1 17 – Analog power supply, 5-V VCC2 23 – Analog power supply, 5-V VCOM 25 – Common voltage output. This pin should be bypassed with a 10-µF capacitor to AGND. VDD 9 – Digital power supply, 5-V VOUT1 27 O Voltage output for audio signal corresponding to L-ch on DATA1 VOUT2 26 O Voltage output for audio signal corresponding to R-ch on DATA1 VOUT3 22 O Voltage output for audio signal corresponding to L-ch on DATA2 VOUT4 21 O Voltage output for audio signal corresponding to R-ch on DATA2 VOUT5 20 O Voltage output for audio signal corresponding to L-ch on DATA3 VOUT6 19 O Voltage output for audio signal corresponding to R-ch on DATA3 VOUT7 16 O Voltage output for audio signal corresponding to L-ch on DATA4 VOUT8 15 O Voltage output for audio signal corresponding to R-ch on DATA4 ZERO1 1 O Zero-flag output 1 ZERO2 28 O Zero-flag output 2 (1) (2) (3) (4) (1) Schmitt-trigger input Pulldown in SPI mode Open-drain output in I2C mode Pulldown 5 PCM1680 www.ti.com SLES133 – MARCH 2005 Functional Block Diagram DAC BCK LRCK DAC DATA1 (1, 2) DATA2 (3, 4) Enhanced Multilevel Delta-Sigma Modulator MD/SDA Function Control I/F VOUT2 Output Amp and Low-Pass Filter VOUT3 DAC Output Amp and Low-Pass Filter VCOM DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter MS/ADR MC/SCL Output Amp and DAC DATA3 (5, 6) 8 Oversampling Digital Filter With Function Controller VOUT1 Low-Pass Filter Serial Input I/F DATA4 (7, 8) Output Amp and Low-Pass Filter MSEL VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 System Clock AGND2 VCC2 AGND1 VCC1 VDD Power Supply ZERO2 Zero Detect Manager DGND System Clock ZERO1 SCK B0033-01 6 PCM1680 www.ti.com SLES133 – MARCH 2005 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted DIGITAL FILTER (DE-EMPHASIS OFF) FREQUENCY RESPONSE (SHARP ROLLOFF) PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF) 0.05 0 0.04 −20 0.03 0.02 Amplitude – dB Amplitude – dB −40 −60 −80 0.01 0.00 −0.01 −0.02 −100 −0.03 −120 −0.04 −0.05 0.0 −140 0 1 2 3 4 Frequency [× fS] 0.1 0.2 0.3 0.4 Frequency [× fS] G001 G002 Figure 1. Figure 2. FREQUENCY RESPONSE (SLOW ROLLOFF) TRANSITION CHARACTERISTICS (SLOW ROLLOFF) 0 0.5 5 4 −20 3 2 Amplitude – dB Amplitude – dB −40 −60 −80 1 0 −1 −2 −100 −3 −120 −4 −140 0 1 2 Frequency [× fS] Figure 3. 3 −5 0.0 4 G003 0.1 0.2 0.3 Frequency [× fS] 0.4 0.5 G004 Figure 4. 7 PCM1680 www.ti.com SLES133 – MARCH 2005 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted DE-EMPHASIS FILTER DE-EMPHASIS DE-EMPHASIS ERROR 0.5 0 fS = 32 kHz −1 0.3 De-Emphasis Error – dB −2 De-Emphasis Level – dB fS = 32 kHz 0.4 −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −0.5 −10 0 2 4 6 8 10 12 0 14 2 4 6 8 10 12 G006 G005 Figure 5. Figure 6. DE-EMPHASIS DE-EMPHASIS ERROR 0.5 0 fS = 44.1 kHz −1 0.3 De-Emphasis Error – dB De-Emphasis Level – dB fS = 44.1 kHz 0.4 −2 −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −0.5 −10 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 16 18 20 G008 G007 Figure 7. 14 f – Frequency – kHz f – Frequency – kHz 8 14 f – Frequency – kHz f – Frequency – kHz Figure 8. PCM1680 www.ti.com SLES133 – MARCH 2005 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted DE-EMPHASIS FILTER (Continued) DE-EMPHASIS DE-EMPHASIS ERROR 0.5 0 fS = 48 kHz −1 0.3 De-Emphasis Error – dB −2 De-Emphasis Level – dB fS = 48 kHz 0.4 −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −0.5 −10 0 2 4 6 8 10 12 14 16 18 20 0 22 2 4 6 8 10 12 14 16 18 20 22 f – Frequency – kHz f – Frequency – kHz G010 G009 Figure 9. Figure 10. ANALOG FILTER ANALOG FILTER PERFORMANCE 10 0 Amplitude − dB −10 −20 −30 −40 −50 −60 −70 1 10 100 1k 10k f − Frequency − Hz G011 Figure 11. 9 PCM1680 www.ti.com SLES133 – MARCH 2005 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted Analog Dynamic Performance Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 0.01 THD+N − Total Harmonic Distortion + Noise − % 110 Dynamic Range – dB 108 5.00 VCC − Supply Voltage − V 102 100 96 4.75 5.25 G012 Figure 12. Figure 13. SIGNAL-TO-NOISE RATIO vs SUPPLY VOLTAGE CHANNEL SEPARATION vs SUPPLY VOLTAGE 110 110 108 108 106 104 102 100 98 96 4.75 5.00 VCC – Supply Voltage – V Channel Separation – dB SNR – Signal-to-Noise Ratio − dB 104 98 0.001 4.75 5.25 G013 106 104 102 100 98 5.00 VCC – Supply Voltage – V Figure 14. 10 106 5.25 G014 96 4.75 5.00 VCC – Supply Voltage – V Figure 15. 5.25 G015 PCM1680 www.ti.com SLES133 – MARCH 2005 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted Temperature Characteristics TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE DYNAMIC RANGE vs TEMPERATURE 0.01 THD+N − Total Harmonic Distortion + Noise − % 110 Dynamic Range – dB 108 104 102 100 98 0.001 −25 0 25 50 TA − Free-Air Temperature − °C 96 −25 75 25 50 Figure 16. Figure 17. SIGNAL-TO-NOISE RATIO vs TEMPERATURE CHANNEL SEPARATION vs TEMPERATURE 110 110 108 108 106 104 102 100 98 96 −25 0 75 TA − Free-Air Temperature − °C G016 Channel Separation – dB SNR – Signal-to-Noise Ratio − dB 106 G017 106 104 102 100 98 0 25 50 TA − Free-Air Temperature − °C Figure 18. 75 G018 96 −25 0 25 50 TA − Free-Air Temperature − °C 75 G019 Figure 19. 11 PCM1680 www.ti.com SLES133 – MARCH 2005 SYSTEM CLOCK INPUT The PCM1680 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCK (pin 5) input. Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 20 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. Texas Instruments’ PLL170x multi-clock generator is an excellent choice for providing the PCM1680 system clock source. Table 1. System Clock Frequencies for Common Audio Sampling Frequencies SAMPLING FREQUENCY 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 8 kHz 1.024 1.536 2.048 3.072 4.096 6.144 9.216 16 kHz 2.048 3.072 4.096 6.144 8.192 12.288 18.432 1152 fS 32 kHz 4.096 6.144 8.192 12.288 16.384 24.576 36.864 44.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 – (1) 48 kHz 6.144 9.216 12.288 18.432 24.576 36.864 – (1) 33.8688 – (1) – (1) – (1) – (1) – (1) – (1) – (1) 88.2 kHz (1) SYSTEM CLOCK FREQUENCY (fSCK), MHz 11.2896 16.9344 22.5792 96 kHz 12.288 18.432 24.576 36.864 – (1) 192 kHz 24.576 36.864 – (1) – (1) – (1) This system clock frequency is not supported for the given sampling frequency. t(SCKH) H 2V System Clock 0.8 V L t(SCKL) System Clock Pulse Cycle Time(1) T0005-08 (1) 1/128 fS, 1/192 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS PARAMETER MIN MAX UNIT t(SCKH) System clock pulse duration, HIGH 7 ns t(SCKL) System clock pulse duration, LOW 7 ns Figure 20. System Clock Timing 12 PCM1680 www.ti.com SLES133 – MARCH 2005 POWER-ON-RESET FUNCTION The PCM1680 includes a power-on-reset function. Figure 21 shows the operation of this function. With the system clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on-reset function is enabled. The initialization sequence requires 3072 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V). After the initialization period, the PCM1680 is set to its reset default state, as described in the Mode Control Register section of this data sheet. During the reset period (3072 system clocks), the analog output is forced to the common voltage (VCOM), or VCC/2. After the reset period, the internal registers are initialized in the next 1/fS period and if SCK, BCK, and LRCK are provided continuously, the PCM1680 provides the proper analog output with group delay corresponding to the input data. VCC 3.7 V 3V 2.2 V 0V Reset Reset Release Internal Reset Don’t Care 3072 System Clocks System Clock T0014-06 Figure 21. Power-On-Reset Timing AUDIO SERIAL INTERFACE The audio serial interface for the PCM1680 comprises a 6-wire synchronous serial port. It includes LRCK (pin 8), BCK (pin 7), and DATA1 (pin 6), DATA2 (pin 11), DATA3 (pin 12), and DATA4 (pin 13). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA1, DATA2, DATA3, and DATA4 into the audio interface serial shift register. Serial data is clocked into the PCM1680 on the rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the serial audio interface internal registers. Both LRCK and BCK must be synchronous with the system clock. Ideally, it is recommended that LRCK and BCK are derived from the system clock input, SCK. LRCK is operated at the sampling frequency, fS. BCK can be operated at 32, 48, or 64 times the sampling frequency. Internal operation of the PCM1680 is synchronized with LRCK. Accordingly, internal operation is suspended when the sampling rate clock, LRCK, is changed or when SCK and/or BCK is interrupted at least for a 3-bit clock cycle. If SCK, BCK, and LRCK are provided continuously after this suspended condition, the internal operation is resynchronized automatically within the following 3/fS period. External resetting is not required. 13 PCM1680 www.ti.com SLES133 – MARCH 2005 AUDIO DATA FORMATS AND TIMING The PCM1680 supports industry-standard audio data formats, including right-justified, I2S, and left-justified. The data formats are shown in Figure 22. Data formats are selected using the format bits, FMT[2:0], located in control register 9 of the PCM1680. The default data format is 24-bit left-justified. All formats require binary 2s complement, MSB-first audio data. Figure 23 shows a detailed timing diagram for the serial audio interface. DATA1, DATA2, DATA3, and DATA4 each carry two audio channels, designated as the left and right channels. The left-channel data always precedes the right-channel data in the serial data stream for all data formats. Table 2 shows the mapping of the digital input data to the analog output pins. Table 2. Audio Input Data to Analog Output Mapping DATA INPUT DATA1 DATA2 DATA3 DATA4 14 CHANNEL ANALOG OUTPUT Left VOUT1 Right VOUT2 Left VOUT3 Right VOUT4 Left VOUT5 Right VOUT6 Left VOUT7 Right VOUT8 PCM1680 www.ti.com SLES133 – MARCH 2005 (1) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) 16-Bit Right-Justified, BCK = 32 fS DATA 14 15 16 1 2 3 14 15 16 1 LSB MSB 2 3 14 15 16 MSB LSB 16-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 14 15 16 1 2 3 14 15 16 MSB 1 2 3 14 15 16 MSB LSB LSB 18-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 16 17 18 1 2 3 16 17 18 MSB 1 LSB 2 3 16 17 18 MSB LSB 20-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 18 19 20 1 2 3 18 19 20 MSB 1 LSB 2 3 18 19 20 MSB LSB 24-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 22 23 24 1 2 3 22 23 24 MSB 1 2 LSB 3 22 23 24 MSB LSB (2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS or 64 fS) DATA 1 2 3 N–2 N–1 MSB LSB N 1 2 3 N–2 MSB N–1 N 1 2 LSB (3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) DATA 1 2 3 N–2 N–1 MSB LSB N 1 2 3 MSB N–2 N–1 N 1 2 LSB T0009-02 Figure 22. Audio Data Input Formats 15 PCM1680 www.ti.com SLES133 – MARCH 2005 1.4 V LRCK t(BCH) t(BCL) t(LS) 1.4 V BCK t(BCY) t(LH) DATA1, DATA2, DATA3, DATA4 1.4 V t(DS) t(DH) T0010-04 PARAMETER MIN UNIT )(1) t(BCY) BCK pulse cycle time t(BCH) BCK pulse duration, HIGH 35 ns t(BCL) BCK pulse duration, LOW 35 ns t(LS) LRCK setup time to BCK rising edge 10 ns t(LH) LRCK hold time to BCK rising edge 10 ns t(DS) DATA1, DATA2, DATA3, DATA4 setup time 10 ns t(DH) DATA1, DATA2, DATA3, DATA4 hold time 10 ns (1) 1/(32 fS), 1/(48 fS), 1/(64 fS fS is the sampling frequency. Figure 23. Audio Interface Timing OVERSAMPLING RATE CONTROL The PCM1680 automatically controls the oversampling rate of the delta-sigma D/A converters using the system clock frequency. The oversampling rate is set to 64× oversampling with an 1152-fS, 768-fS, or 512-fS system clock; 32× oversampling with a 384-fS or 256-fS system clock; and 16× oversampling with a 192-fS or 128-fS system clock. ZERO FLAG The PCM1680 has two zero-flag pins, ZERO1 (pin 1) and ZERO2 (pin 28), which are assigned to the combinations A through D as shown in Table 3. Zero-flag combinations are selected using the zero-flag combination bits, AZRO[1:0], located in control register 13 of the PCM1680. If the input data of the L-channel and/or R-channel of all assigned channels remains at a logic-0 level for 1024 sampling periods (LRCK clock periods), ZERO1 and ZERO2 are set to a logic-1 state, or high level. If the input data of any of the assigned channels contains a logic-1, ZERO1 and ZERO2 are set to a logic-0 state immediately. The active polarity of the zero-flag output can be inverted by setting the ZREV bit of control register 10 to 1. The reset default is active-high output or ZREV = 0. Table 3. Zero-Flag Output Combinations 16 ZERO-FLAG COMBINATION ZERO1 (PIN 1) ZERO2 (PIN 28) A DATA1 L-ch DATA1 R-ch B N/A DATA[1:4] C DATA4 DATA[1:3] D DATA1 DATA[2:4] PCM1680 www.ti.com SLES133 – MARCH 2005 MODE CONTROL The PCM1680 has many programmable functions which can be controlled in the software control mode. The functions are controlled by programming and reading the internal registers using the SPI or I2C interface. These two interfaces for mode control can be selected by MSEL (pin 14). The functions of pins 2, 3, and 4 are changed by MSEL selection as shown in Table 4. Table 4. Interface Mode Control MSEL INTERFACE MODE PIN FUNCTION PIN 2 PIN 3 PIN 4 LOW SPI MS MC MD HIGH I2C ADR SCL SCA SPI CONTROL INTERFACE The SPI control interface of the PCM1680 is a 3-wire synchronous serial port that operates asynchronously to the serial audio interface. The SPI control interface is used to program the on-chip mode registers. The control interface includes MD (pin 4), MC (pin 3), and MS (pin 2). MD is the serial data input, used to program the mode registers. MC is the control port for the serial bit clock, used to shift in the serial data, and MS is the control port for mode control select, which is used to enable the mode control. REGISTER WRITE OPERATION All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data word format. The most significant bit is a fixed 0 for the write operation. Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure 25 shows the functional timing diagram for writing to the serial control port. MS is held at a logic-1 state until a register needs to be written. To start the register write cycle, MS is set to logic-0. Sixteen clock cycles are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the completion of the sixteenth clock cycle, MS is set to logic-1 to latch the data into the indexed mode control register. LSB MSB 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 Register Index (or Address) D4 D3 D2 D1 D0 Register Data R0001-01 Figure 24. Control Data Word Format for MD MS MC MD X 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 X X 0 IDX6 T0048-01 Figure 25. Write Operation Timing 17 PCM1680 www.ti.com SLES133 – MARCH 2005 INTERFACE TIMING REQUIREMENTS Figure 26 shows a detailed timing diagram for the serial control interface. Special attention to the setup and hold times is required. Also, t(MSS) and t(MSH), which define minimum delays between edges of the MS and MC clocks, require special attention. These timing parameters are critical for proper control port operation. t(MHH) MS t(MSS) t(MCL) t(MCH) t(MSH) MC t(MCY) LSB MD t(MDS) t(MDH) T0013-03 MIN UNIT t(MCY) MC pulse cycle time PARAMETER 100 ns t(MCL) MC pulse duration, LOW 50 ns t(MCH) MC pulse duration, HIGH 50 ns t(MHH) MS pulse duration, HIGH (1) ns t(MSS) MS falling edge to MC rising edge 20 ns t(MSH) MS hold time, MC rising edge for LSB to MS rising edge 20 ns t(MDH) MD hold time 15 ns t(MDS) MD setup time 20 ns (1) 3/(256 fS) s (minimum), fS: sampling rate Figure 26. Interface Timing I2C INTERFACE The PCM1680 supports the I2C serial bus and the data transmission protocol for standard mode as a slave device. This protocol is explained in the I2C specification 2.0. The PCM1680 does not support a board-to-board interface. Figure 27 shows the I2C framework for basic read and write operations. SLAVE ADDRESS MSB 1 LSB 0 0 1 1 0 ADR R/W The PCM1680 has seven bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to 1001 10. The next bit of the address byte is the device select bit, which can be user-defined using the ADR terminal. A maximum of two PCM1680s can be connected on the same bus at one time. Each PCM1680 responds when it receives its own slave address. 18 PCM1680 www.ti.com SLES133 – MARCH 2005 PACKET PROTOCOL A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if writing or acknowledge if reading, and stop condition. The PCM1680 supports only slave receivers and slave transmitters. SDA SCL 1−7 8 9 1−8 9 1−8 9 9 Slave Address R/W ACK DATA ACK DATA ACK ACK St R/W: Read Operation if 1; Otherwise, Write Operation ACK: Acknowledgement of a Byte if 0 DATA: 8 Bits (Byte) NACK: Not Acknowledgement if 1 Start Condition Write Operation Sp Stop Condition Transmitter M M M S M S M S S M Data Type St Slave Address W ACK DATA ACK DATA ACK ACK Sp Read Operation Transmitter M M M S S M S M M M Data Type St Slave Address R ACK DATA ACK DATA ACK NACK Sp M: Master Device S: Slave Device St: Start Condition Sp: Stop Condition W: Write R: Read T0049-01 Figure 27. Basic I2C Framework WRITE OPERATION A master can write to any PCM1680 registers using a single access. The master sends a PCM1680 slave address with a write bit, a register address, and the data. When undefined registers are accessed, the PCM1680 sends an acknowledgement, but the write operation does not occur. Figure 28 is a diagram of the write operation. Transmitter M M M S M S M S M Data Type St Slave Address W ACK Reg Address ACK Write Data ACK Sp M: Master Device S: Slave Device St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition R0002-01 Figure 28. Write Operation READ OPERATION A master can read any PCM1680 register using a single access. The master sends a PCM1680 slave address with a read bit after transferring the register address. Then the PCM1680 transfers the data in the register specified. Figure 29 is a diagram of the read operation. 19 PCM1680 www.ti.com SLES133 – MARCH 2005 Transmitter M M M S M S M M M S S M M Data Type St Slave Address W ACK Reg Address ACK Sr Slave Address R ACK Data NACK Sp M: Master Device S: Slave Device St: Start Condition Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge W: Write R: Read R0002-02 NOTE: The slave address after the repeated start condition must be the same as the previous slave address. Figure 29. Read Operation TIMING DIAGRAM Start Repeated Start Stop t(D-HD) t(BUF) t(D-SU) t(SDA-R) t(SDA-F) t(P-SU) SDA t(SCL-R) t(RS-HD) t(LOW) SCL t(S-HD) t(HI) t(RS-SU) t(SCL-F) T0050-01 PARAMETER MIN MAX UNIT 100 kHz f(SCL) SCL clock frequency t(BUF) Bus free time between a STOP and START condition 4.7 µs t(LOW) Low period of the SCL clock 4.7 µs t(HI) High period of the SCL clock 4 µs t(RS-SU) Setup time for (repeated) START condition 4.7 µs t(S-HD) t(RS-HD) Hold time for (repeated) START condition 4 µs t(D-SU) Data setup time 250 t(D-HD) Data hold time 0 900 ns t(SCL-R) Rise time of SCL signal 20 + 0.1 CB 1000 ns t(SCL-R1) Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1 CB 1000 ns t(SCL-F) Fall time of SCL signal 20 + 0.1 CB 1000 ns t(SDA-R) Rise time of SDA signal 20 + 0.1 CB 1000 ns t(SDA-F) Fall time of SDA signal 20 + 0.1 CB 1000 t(P-SU) Setup time for STOP condition CB Capacitive load for SDA and SCL lines VNH Noise margin at high level for each connected device (including hysteresis) 400 0.2 VDD ns µs 4 Figure 30. Interface Timing 20 ns pF V PCM1680 www.ti.com SLES133 – MARCH 2005 MODE CONTROL REGISTERS USER-PROGRAMMABLE MODE CONTROLS The PCM1680 includes a number of user-programmable functions which are accessed via control registers. The registers are programmed using the serial control interface which is discussed in the Mode Control section of this data sheet. Table 5 lists the available mode control functions, along with their reset default conditions and associated register index. REGISTER MAP The mode control register map is shown in Table 6. The MSB of all registers is fixed to 0. Each register also includes an index (or address) indicated by the IDX[6:0] bits. RESERVED REGISTERS Registers 0, 11, and 15 are reserved for factory use. To ensure proper operation, the user should not write to these registers. Table 5. User-Programmable Mode Controls FUNCTION RESET DEFAULT REGISTER BIT Digital attenuation control, 0 dB to –63 dB 0 dB, no attenuation in 0.5-dB steps 1–6, 16, 17 AT1[7:0], AT2[7:0], AT3[7:0], AT4[7:0], AT5[7:0], AT6[7:0], AT7[7:0], AT8[7:0] Soft mute control Mute disabled 7, 18 MUT[6:1], MUT[8:7] DAC1–DAC8 operation control DAC1–DAC8 enabled 8, 19 DAC[6:1], DAC[8:7] Audio data format control 24-bit, left-justified 9 FMT[2:0] Digital filter rolloff control Sharp rolloff 9 FLT De-emphasis all-channel function control De-emphasis of all channels disabled 10 DMC De-emphasis all-channel sample rate selection 44.1 kHz 10 DMF[1:0] Output phase select Normal phase 10 DREV Zero-flag polarity select High 10 ZREV Software reset control Reset disabled 10 SRST Oversampling rate control ×64, ×32, ×16 12 OVER Zero-flag combination select ZERO1: DATA1 Lch ZERO2: DATA1 Rch 13 AZRO[1:0] Digital attenuation mode select 0 to –63 dB, 0.5-dB step 13 DAMS Zero-detect status (read-only, I2C interface only) N/A 14 ZERO[8:1] 21 PCM1680 www.ti.com SLES133 – MARCH 2005 Table 6. Mode Control Register Map IDX (B8–B14) REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 01h 1 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 02h 2 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 03h 3 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 04h 4 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 05h 5 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 06h 6 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 07h 7 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) RSV (1) MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 08h 8 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) RSV (1) DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 09h 9 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) RSV (1) FLT RSV (1) RSV (1) FMT2 FMT1 FMT0 0Ah 10 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST ZREV DREV DMF1 DMF0 RSV (1) RSV (1) DMC OVER RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) AZRO1 AZRO0 RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) 0Ch (1) 22 12 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 0Dh 13 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 DAMS 0Eh 14 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 10h 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT77 AT76 AT75 AT74 AT73 AT72 AT71 11h 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80 12h 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) MUT8 MUT7 13h 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) DAC8 DAC7 Reserved for test operation. It should be set to 0 during normal operation. AT70 PCM1680 www.ti.com SLES133 – MARCH 2005 REGISTER DEFINITIONS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 1 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 REGISTER 2 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 REGISTER 3 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 REGISTER 4 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 REGISTER 5 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 REGISTER 6 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 REGISTER 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT77 AT76 AT75 AT74 AT73 AT72 AT711 AT70 REGISTER 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80 ATx[7:0]: Digital Attenuation Level Setting where x = 1–8, corresponding to the DAC output VOUTx. Default value: 1111 1111b ATx[7:0] DECIMAL VALUE ATTENUATION LEVEL SETTING DAMS = 0 DAMS = 1 1111 1111b 255 0 dB, no attenuation (default) 0 dB, no attenuation (default) 1111 1110b 254 –0.5 dB –1 dB 1111 1101b 253 –1 dB –2 dB : : : : 1001 1100b 156 –49.5 dB –99 dB 1001 1011b 155 –50 dB –100 dB 1001 1010b 154 –50.5 dB Mute : : : : 1000 0010b 130 –62.5 dB Mute 1000 0001b 129 –63 dB Mute 1000 0000b 128 Mute Mute : : : : 0000 0000b 0 Mute Mute Each DAC output, VOUT1 through VOUT8, has a digital attenuation function. The attenuation level can be set from 0 dB to R dB, in S-dB steps. Changes in attenuation levels are made by incrementing or decrementing by one step (S-dB) for every 8/fS time interval until the programmed attenuation setting is reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute). Range (R) and step (S) are –63 and 0.5, respectively, for DAMS = 0 and –100 and 1, respectively, for DAMS = 1. The DAMS bit is defined in register 13. The attenuation data for each channel can be set individually. The attenuation level can be calculated using the following formula: Attenuation level (dB) = S • (ATx[7:0]DEC – 255) where ATx[7:0]DEC = 0 through 255. For ATx[7:0]DEC = 0 through 128 with DAMS = 0 or for ATx[7:0]DEC = 0 through 154 with DAMS = 1, the attenuation is set to infinite attenuation (mute). 23 PCM1680 www.ti.com SLES133 – MARCH 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 7 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 REGISTER 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV MUT8 MUT7 MUTx: Soft Mute Control where x = 1–8, corresponding to the DAC output VOUTx. Default value: 0 MUTx = 0 Mute disabled (default) MUTx = 1 Mute enabled The mute bits, MUT1 through MUT8, are used to enable or disable the soft mute function for the corresponding DAC outputs, VOUT1 through VOUT8. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite-attenuation setting one attenuator step (S-dB) at a time. This provides a quiet, pop-free muting of the DAC output. On returning from soft mute, by setting MUTx = 0, the attenuator is increased one step at a time to the previously programmed attenuator level. The step size, S, is 0.5 dB for DAMS = 0 and 1 dB for DAMS = 1. B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 8 B15 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B14 B13 B12 B11 B10 B9 B8 RSV RSV DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 REGISTER 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV DAC8 DAC7 DACx: DAC Operation Control where x = 1–8, corresponding to the DAC output VOUTx. Default value: 0 DACx = 0 DAC operation enabled (default) DACx = 1 DAC operation disabled The DAC operation controls are used to enable and disable the DAC outputs, VOUT1 through VOUT8. When DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier input is switched to the dc common voltage (VCOM), equal to VCC/2. 24 PCM1680 www.ti.com SLES133 – MARCH 2005 B15 REGISTER 9 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 B6 B5 B4 B3 B2 B1 B0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0 FLT: Digital Filter Rolloff Control Default value: 0 FLT = 0 Sharp rolloff (default) FLT = 1 Slow rolloff The FLT bit allows users to select the digital filter rolloff that is best suited to their application. Two filter rolloff selections are available: sharp or slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. FMT[2:0]: Audio Interface Data Format Default value: 101b FMT[2:0] Audio Data Format Selection 000 24-bit right-justified format, standard data 001 20-bit right-justified format, standard data 010 18-bit right-justified format, standard data 011 16-bit right-justified format, standard data 100 I2S format, 16- to 24-bit 101 Left-justified format, 16- to 24-bit (default) 110 Reserved 111 Reserved The FMT[2:0] bits are used to select the data format for the serial audio interface. B15 REGISTER 10 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 B6 B5 B4 B3 B2 B1 B0 SRST ZREV DREV DMF1 DMF0 RSV RSV DMC SRST: Reset Default value: 0 SRST = 0 Reset disabled (default) SRST = 1 Reset enabled The SRST bit is used to enable or disable the soft reset function. The operation is the same as the power-on-reset function with the exception of the reset period, which is 1024 system clocks for the SRST function. All registers are initialized. ZREV: Zero-Flag Polarity Select Default value: 0 ZREV = 0 Zero-flag pins high at a zero detect (default) ZREV = 1 Zero-flag pins low at a zero detect The ZREV bit allows the user to select the polarity of the zero-flag pins. 25 PCM1680 www.ti.com SLES133 – MARCH 2005 DREV: Output Phase Select Default value: 0 DREV = 0 Normal output (default) DREV = 1 Inverted output The DREV bit is the output analog signal phase control. DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function Default value: 00b DMF[1:0] De-Emphasis Sampling Rate Selection 00 44.1 kHz (default) 01 48 kHz 10 32 kHz 11 Reserved The DMF[1:0] bits select the sampling frequency used for the digital de-emphasis function when it is enabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet. The preceding table shows the available sampling frequencies. DMC: Digital De-Emphasis All-Channel Function Control Default value: 0 DMC = 0 De-emphasis disabled for all channels (default) DMC = 1 De-emphasis enabled for all channels The DMC bit is used to enable or disable the de-emphasis function for all channels. B15 REGISTER 12 0 B14 B13 B12 B11 B10 B9 B8 B7 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER B6 B5 B4 B3 B2 B1 B0 RSV RSV RSV RSV RSV RSV RSV OVER: Oversampling Rate Control Default value: 0 System clock frequency = 512 fS, 768 fS, or 1152 fS OVER = 0 ×64 oversampling (default) OVER = 1 ×128 oversampling (applicable only if sampling clock frequency ≤ 24 kHz) System clock frequency = 256 fS or 384 fS OVER = 0 ×32 oversampling (default) OVER = 1 ×64 oversampling (applicable only if sampling clock frequency ≤ 48 kHz) System clock frequency = 128 fS or 192 fS OVER = 0 ×16 oversampling (default) OVER = 1 ×32 oversampling (applicable only if sampling clock frequency ≤ 96 kHz) The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters. Setting OVER = 1 is recommended under the following conditions: • System clock frequency = 512 fS, 768 fS, or 1152 fS and sampling clock frequency ≤ 24 kHz • System clock frequency = 256 fS or 384 fS and sampling clock frequency ≤ 48 kHz • System clock frequency = 128 fS or 192 fS and sampling clock frequency ≤ 96 kHz 26 PCM1680 www.ti.com SLES133 – MARCH 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 DAMS AZRO1 AZRO0 RSV RSV RSV RSV RSV REGISTER 13 DAMS: Digital Attenuation Mode Select Default value: 0 DAMS = 0 Fine step, 0.5 dB/step for 0 to –63 dB range (default) DAMS = 1 Wide range, 1 dB/step for 0 to –100 dB range The DAMS bit is used to select the digital attenuation mode. AZRO[1:0]: Zero-Flag Channel-Combination Select Default value: 00b AZRO[1:0] Zero-Flag Channel-Combination Select 00 Combination A (ZERO1: DATA1 L-ch, ZERO2: DATA1 R-ch) (default) 01 Combination B (ZERO1: N/A, ZERO2: DATA1–DATA4) 10 Combination C (ZERO1: DATA4, ZERO2: DATA1–DATA3) 11 Combination D (ZERO1: DATA1, ZERO2: DATA2–DATA4) The AZRO[1:0] bits are used to select the zero-flag channel combinations for ZERO1 and ZERO2. B15 REGISTER 14 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 B6 B5 B4 B3 B2 B1 B0 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 ZERO[8:1]: Zero-Detect Status (Read-Only, I2C Interface Only) Default value: N/A The ZERO[8:1] bits show the status of zero detect for each channel. The status is set to 1 by detecting a zero state without regard to the ZREV bit setting. 27 PCM1680 www.ti.com SLES133 – MARCH 2005 ANALOG OUTPUTS The PCM1680 includes eight independent output channels, VOUT1 through VOUT8. These are unbalanced outputs, each capable of driving 3.9 Vp-p typical into a 5-kΩ ac load with VCC = 5 V. The internal output amplifiers for VOUT1 through VOUT8 are biased to the dc common voltage, equal to 0.5 VCC. The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise-shaping characteristics of the PCM1680 delta-sigma D/A converters. The frequency response of this filter is shown in Figure 11. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application Information section of this data sheet. VCOM OUTPUT One unbuffered common voltage output pin, VCOM (pin 25), is brought out for decoupling purposes. This pin is nominally biased to the dc common voltage, equal to VCC/2. If this pin is to be used to bias external circuitry, a voltage follower is required for buffering purposes. Figure 31 shows an example of using the VCOM pin for external biasing applications. AV R2 R1 PCM1680 R3 2 – OPA2134 3 C2 1 R4 + R1 VOUTX VCC C1 R2 + R5 VCOM + + OPA337 C3 10 µF − To Additional Low-Pass Filter Circuits S0056-01 Figure 31. Single-Supply Filter Circuit Using VCOM for External Biasing Applications 28 PCM1680 www.ti.com SLES133 – MARCH 2005 APPLICATION INFORMATION CONNECTION DIAGRAMS A basic connection diagram is shown in Figure 32, with the necessary power supply bypassing and decoupling components. Texas Instruments’ PLL170x is used to generate the system clock input at SCK, as well as generating the clock for the audio signal processor. The use of series resistors (22 Ω to 100 Ω) is recommended for SCK, LRCK, BCK, DATA1, DATA2, DATA3, and DATA4. The series resistor combines with the stray PCB capacitance and device input capacitance to form a low-pass filter that removes high-frequency noise from the digital signal, thus reducing high-frequency emission. µC or µP 1 ZERO1 ZERO2 28 2 MS/ADR VOUT1 27 3 MC/SCL VOUT2 26 4 MD/SDA VCOM 25 5 SCK AGND2 24 R1 PLL170x 6 Audio DSP or Decoder + C2 + C12 BCK 8 LRCK VCC2 L VOUT3 C9 9 R5 R7 VDD VOUT4 VOUT5 R 23 22 PCM1680 R6 5 V Analog DATA1 7 R3 R2 C1 C11 R4 27-MHz Master Clock + 21 20 10 DGND VOUT6 19 11 DATA2 AGND1 18 12 DATA3 VCC1 17 13 DATA4 VOUT7 16 14 MSEL VOUT8 15 + C3 + C4 + C5 + C6 Output Low-Pass Filter LF RF LS RS CTR SUB C10 + C7 + C8 C13 + 0V C1 − C8: 4.7 µF − 10 µF Electrolytic Typical C9 − C11: 1 µF Ceramic Typical C12, C13: 10 µF Electrolytic Typical R1 − R7: 22 Ω − 100 Ω Typical S0057-01 Figure 32. Basic Connection Diagram 29 PCM1680 www.ti.com SLES133 – MARCH 2005 APPLICATION INFORMATION (continued) POWER SUPPLY AND GROUNDING The PCM1680 requires 5 V for the analog supply and digital supply. The 5-V supply is used to power not only the DAC analog and output filter circuitry, but also the digital filter and serial interface circuitry. For best performance, a 5-V supply using a linear regulator is recommended. Four capacitors are required for supply bypassing, as shown in Figure 32. These capacitors should be located as close as possible to the PCM1680 package. The 10-µF capacitor should be tantalum or aluminum electrolytic, while the three 1-µF capacitors are ceramic. D/A OUTPUT FILTER CIRCUITS Delta-sigma D/A converters use noise shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band noise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a combination of on-chip and external low-pass filtering. Figure 31 and Figure 33 show the recommended external low-pass active filter circuits for dual- and single-supply applications. These circuits are second-order Butterworth filters using a multiple-feedback (MFB) circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For more information regarding MFB active filter design, see Dynamic Performance Testing of Digital Audio D/A Converters (SBAA055). Because the overall system performance is defined by the quality of the D/A converters and their associated analog output circuitry, high-quality audio operational amplifiers are recommended for the active filters. Texas Instruments’ OPA2134 and OPA2353 dual operational amplifiers are shown in Figure 31 and Figure 33, and are recommended for use with the PCM1680. R2 R1 VIN C2 AV C1 R3 2 3 – OPA2134 1 R4 VOUT + R2 R1 S0053-01 Figure 33. Dual-Supply Filter Circuit PCB LAYOUT GUIDELINES A typical PCB floor plan for the PCM1680 is shown in Figure 34. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1680 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital audio interface and control signals originating from the digital section of the board. Separate power supplies are recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the PCM1680. In cases where a common 5-V supply must be used for the analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 35 shows the recommended approach for single-supply applications. 30 PCM1680 www.ti.com SLES133 – MARCH 2005 APPLICATION INFORMATION (continued) Digital Power +VD Analog Power DGND AGND +5VA VDD Digital Logic and Audio Processor +VS –VS VCC Output Circuits DGND PCM1680 Digital Ground AGND Digital Section Analog Ground Analog Section Return Path for Digital Signals B0031-02 Figure 34. Recommended PCB Layout Power Supplies RF Choke or Ferrite Bead +5V VDD Digital Logic and Audio Processor AGND VDD +VS –VS VCC DGND Output Circuits PCM1680 AGND Digital Section Analog Section Common Ground B0032-02 Figure 35. Single-Supply PCB Layout 31 PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCM1680DBQ ACTIVE SSOP/ QSOP DBQ 28 PCM1680DBQR ACTIVE SSOP/ QSOP DBQ 28 48 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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