NJU8719 PRELIMINARY Monaural BTL Output Switching Driver for Class D Amplifier ! PACKAGE OUTLINE ! GENERAL DESCRIPTION The NJU8719 is a monaural BTL output switching driver for class D amplifier. It converts 1bit digital signal input, such as PWM or PDM signal, to analog signal output with simple external LC low-pass filter. The NJU8719 realizes very high power-efficiency by class D operation. Therefore, It is suitable for portable set with speaker. NJU8719V ! PIN CONFIGURATION ! FEATURES # # # # # # 1-channel 1bit Audio Signal Input Monaural BTL Output Standby(Hi-Z) Control Function Operating Voltage : 2.4V to 5.25V CMOS Technology Package Outline : SSOP10 VDD IN NC MCK STBYB 10 9 8 7 6 1 2 3 4 5 VSS OUTP VDDO OUTN VSS ! BLOCK DIAGRAM VDD VDDO VSS IN OUTP Dead Time Generator MCK OUTN STBYB Ver.2004-05-20 VSS -1- NJU8719 ! TERMINAL DESCRIPTION No. 1 2 3 SYMBOL VDD IN NC I/O − I − 4 MCK I Function Power Supply, VDD=5V 1-bit Data Input Terminal Non connection Master Clock Input Terminal The condition of the data input terminal is fetched with the rising edge of this signal. Standby Control Terminal (L:Standby) 5 STBYB I 6 Power GND and Output GND terminal: VSS=0V VSS − 10 7 OUTN O Negative output 8 VDDO − Output Power Supply, VDD=5V 9 OUTP O Positive output *VSS(Terminal No.6,10) should be connected at a nearest point to the IC. *VDD(Terminal No.1) and VDDO(Terminal No.8) should be connected at a nearest point to the IC. *STBYB(Terminal No.5) must be connected to VDD, when this terminal is not used. ! INPUT TERMINAL STRUCTURE VDD Input Terminal VSS -- 2 2 -- Ver.2004-05-20 NJU8719 NJU3555 ! FUNCTIONAL DESCRIPTION (1) Signal Output The OUTP and OUTN generate PMW output signal, which is converted to analog signal via external 2nd-order or higher LC filter. The NJU8719 drives a speaker by the BTL output, and OUTP is a positive output and OUTN is a negative outputs. A switching regulator with a high response against a voltage fluctuation is the best selection for the VDDO, which is the power supply for output drivers. To obtain better T.H.D. performance, the stabilization of the power is required. (2) Standby Control Function By setting the STBYB terminal to “L”, the NJU8719 becomes standby condition. OUTP and OUTN are in Hi-Z. During standby condition, (3) Master Clock Master clock (MCK) synchronizes with the Audio signal input (IN). The setup time and the hold time should be kept in the AC characteristics because IN is fetched with the rising edge of MCK. MCK requires jitter-free or jitter as small as possible because the jitter downs S/N ratio. OUTP and OUTN occur the pop noise when MCK is stopped in operation without standby mode. Therefore, the standby mode should be set before MCK stop. Ver.2004-05-20 -3- NJU8719 ! ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL VDD VDDO RATING -0.3 to +5.5 -0.3 to +5.5 UNIT Input Voltage Vin -0.3 to VDD+0.3 V Operating Temperature Topr -40 to +85 °C Storage Temperature Tstg -40 to +125 °C PD 360* mW Supply Voltage Power Dissipation SSOP10 V * : Mounted on two-layer board of based on the JEDEC. Note 1) All voltage values are specified as VSS=0V. Note 2) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electrical characteristics conditions will cause malfunction and poor reliability. Note 3) De-coupling capacitors should be connected between VDD-VSS and VDDO-VSS due to the stabilized operation. ! ELECTRICAL CHARACTERISTICS (Ta=25°C, VDD= VDDO=5.0V, VSS=0V, fS=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT 2.4 5.0 5.25 V VDD ,VDDO Supply Voltage VDD Output Driver High side Resistance RH VOUT=VDDO-0.1V - 0.5 1.5 Ω Output Driver Low side Resistance RL VOUT=0.1V - 0.5 1.5 Ω - - 1 µA - 3.8 5.7 mA VIH 0.7VDD - VDD V VIL 0 - 0.3VDD V ILK - - ±1 µA Operating Current at Standby Operating Current at Operating (Mute signal input) IST IDD IN, STBYB=0V No-load operating IN=32fS MCK=256fS No-load operating Input Voltage Input Leakage Current -- 4 4 -- Ver.2004-05-20 NJU8719 NJU3555 ! TIMING CHARACTERISTICS • Audio Signal Input tMCKL tMCKH MCK IN tDS (Ta=25°C, VDD= VDDO=5.0V, VSS=0V, fS=44.1kHz, unless otherwise noted) SYMBOL CONDITIONS MIN. TYP. MAX. UNIT PARAMETER • tDH MCK Frequency fMCKI - - 25 MHz MCK Pulse Width (H) tMCKH 12 - - ns MCK Pulse Width (L) tMCKL 12 - - ns IN Setup Time tDS 20 - - ns IN Hold Time tDH 20 - - ns Output Control Signal Input STBYB 0.7VDD 0.7VDD 0.3VDD 0.3VDD tUP PARAMETER tDN (Ta=25°C, VDD= VDDO=5.0V, VSS=0V, fS=44.1kHz, unless otherwise noted) SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Rise Time tUP - - 50 ns Fall Time tDN - - 50 ns Note 4) All timings are based on 30% and 70% voltage level of VDD. Ver.2004-05-20 -5- NJU8719 ! APPLICATION CIRCUIT 22µH VDD 10µF 0.1µF OUTP(9) VDD(1) 1µF VSS(10) IN(2) MCK(4) STBYB(5) NJU8719 8Ω 22µH OUTN(7) VDDO(8) 1µF 100µF 1µF Speaker VDDO VSS(6) Note 5) De-coupling capacitors must be connected between each power supply terminal and GND terminal. Note 6) The power supply for VDDO requires fast driving response performance such as a switching regulator for T.H.D.. Note 7) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please consider and check the circuit carefully to fit your application. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -- 6 6 -- Ver.2004-05-20