NTE1639 Integrated Circuit CMOS Clock Generator/Driver for BBDs Description: The NTE1639 is a CMOS LSI Clock Generator ina 8–Lead DIP type package capable of generating two phase clock signals of low output impedance for use as a BBD driver. The built–in VGG power supply circuit provides the proper voltages needed for driving BBDs such as the NTE1641. Features: D BBD Direct Driving Capability of up to two BBD’s D Self and Separate Oscillations. D Two Phase Clock Output (Duty: 1/2) D Built–in VGG Voltage Generator for Driving the NTE1641 BBD. D Single Power Supply: –8V to –16V. Applications: D BBD Clock Generator/Driver. Absolute Maximum Ratings: (TA = +25°C unless otherwise specified) Drain Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18V to +0.3V Input/Output Pin Voltage, VI, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD –0.3V to +0.3V Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mW Operating Ambient Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30° to +125°C Recommended Operating Conditions: (TA = +25°C unless otherwise specified) Item Drain Supply Voltage Symbol VDD Condition GND = 0V Min Typ Max Unit –8 –15 –16 V Electrical Characteristics: (TA = +25°C, VDD = –15V, GND = 0V unless otherwise specified) Parameter Symbol Input Drain Current IDD Total Power Dissipation Ptot Test Condition No load Clock Output 40kHZ Min Typ Max Unit – 3 – mA – 45 – mW OX1 Input Pin Voltage “H” Level VIH 0 – –1 V Voltage “L” Level VIL VDD+1 – VDD V – – 30 µA Input Leakage Current ILeak VI = 0V to –15V Output Current “H” Level IOH(1) VO = –1V 0.6 – – mA Output Current “L” Level IOL(1) VO = –14V 0.5 – – mA Output Leakage Current ILOL(1) VO = VDD VO = GND – – – – 30 30 µA µA Output Current “H” Level IOH(2) VO = –1V 1.5 – – mA Output Current “L” Level IOL(2) VO = –14V 2 – – mA Output Leakage Current ILOL(2) VO = VDD VO = GND – – – – 30 30 µA µA Output Current “H” Level IOH(3) VO = –1V 10 – – mA Output Current “L” Level IOL(3) VO = –14V 10 – – mA Output Leakage Current ILOL(3) VO = VDD VO = GND – – – – 30 30 µA µA OX2 Output Pin OX3 Output pin CP1, CP2 output pin VGG OUT output pin (Note 1) Output Voltage VGG(Out) –14 Note 1. This pin generates the VGG voltage for a BBD manufactured by NTE. So therefore, it might not be applicable for other devices. In any case, the VGG(OUT) changes by the following formula depending on the value of VDD. VGG(OUT) ≅ V 14 VDD 15 Pin Descriptions: Pin No. Symbol Pin Name Description 1 GND Ground Connected to GND of the circuit. 2 CP1 Clock Output 1 3 VDD VDD apply 4 CP2 Clock Output 2 5 OX3 6 OX2 OSC connections to C1, R2, and R1 separately 7 OX1 R, C are connected for the In case of separate excitainternal clock. tion, OX3 and OX2 are opened and OX1 is set to OSC input. 8 VGG OUT VGG Voltage Output –14V is output. (VDD = –15V) VGG OUT = 14/15VDD. This pin outputs a clock signal that is the reverse phase of CP2 with a Duty Cycle of 1/2 the frequency of oscillation. –15V is applied This pin outputs a clock signal that is a the reverse phase of CP1 The Maximum Clock Frequency: The upper limit value of the clock frequency is determined by the load capacitance and power consumption. The maximum power dissipation for the NTE1639 is PD = 200mW. If the clock frequency of the load capacitance is increased, the power consumption will be increased. Accordingly, in order to utilize this device with a dissipation less than the permissible value, it is necessary to select adequate values for the clock frequency and load capacitance. By connecting a resistance to the clock output pin, it is possible to increase the value of the maximum clock frequency without increasing dissipation. Because the dissipation on the LSI side is lessened, part of the power consumption required for driving the load capacitance is consumed by the series resistance. Pin Connection Diagram GND 1 8 VGG (Out) CP 1 2 7 OX 1 VDD 3 6 OX 2 4 5 OX 3 CP 2 8 5 .256 (6.52) Max 1 4 .393 (10.0) Max .300 (7.62) .150 (3.81) .100 (2.54) .070 (1.77) Min .300 (7.62)