TI CD74HCT85

[ /Title
(CD74
HC85,
CD74
HCT85
)
/Subject
(High
Speed
CMOS
Logic
4-Bit
Magnitude
Compara-
CD74HC85,
CD74HCT85
Data sheet acquired from Harris Semiconductor
SCHS136
High Speed CMOS Logic
4-Bit Magnitude Comparator
August 1997
Features
Description
• Buffered Inputs and Outputs
The CD74HC85 and CD74HCT85 are high
magnitude comparators that use silicon-gate
technology to achieve operating speeds similar to
with the low power consumption of standard
integrated circuits.
• Typical Propagation Delay: 13ns (Data to Output at
VCC = 5V, CL = 15pF, TA = 25oC
• Serial or Parallel Expansion Without External Gating
speed
CMOS
LSTTL
CMOS
These 4-bit devices compare two binary, BCD, or other
monotonic codes and present the three possible magnitude
results at the outputs (A > B, A < B, and A = B). The 4-bit
input words are weighted (A0 to A3 and B0 to B3), where A3
and B3 are the most significant bits.
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
The devices are expandable without external gating, in both
serial and parallel fashion. The upper part of the truth table
indicates operation using a single device or devices in a
serially expanded application. The parallel expansion
scheme is described by the last three entries in the truth
table.
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
Ordering Information
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
PART NUMBER
TEMP. RANGE (oC)
PKG.
NO.
PACKAGE
CD74HC85E
-55 to 125
16 Ld PDIP
E16.3
CD74HCT85E
-55 to 125
16 Ld PDIP
E16.3
CD74HC85M
-55 to 125
16 Ld SOIC
M16.15
CD74HCT85M
-55 to 125
16 Ld SOIC
M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74HC85, CD74HCT85
(PDIP, SOIC)
TOP VIEW
16 VCC
B3 1
(A < B) IN 2
15 A3
(A = B) IN 3
14 B2
(A > B) IN 4
13 A2
(A > B) OUT 5
12 A1
(A = B) OUT 6
11 B1
(A < B) OUT 7
10 A0
GND 8
9 B0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number
1770.1
CD74HC85, CD74HCT85
Functional Diagram
15
A3
13
A2
12
A1
10
A0
(A < B) IN
(A = B) IN
(A > B) IN
B3
7
2
3
6
4
5
(A < B) OUT
(A = B) OUT
(A > B) OUT
1
14
B2
11
B1
9
B0
TRUTH TABLE
COMPARING INPUTS
A3, B3
A2, B2
A1, B1
CASCADING INPUTS
OUTPUTS
A0, B0
A>B
A<B
A=B
A>B
A<B
A=B
SINGLE DEVICE OR SERIES CASCADING
A3 > B3
X
X
X
X
X
X
H
L
L
A3 < B3
X
X
X
X
X
X
L
H
L
A3 = B3
A2 >B2
X
X
X
X
X
H
L
L
A3 = B3
A2 < B2
X
X
X
X
X
L
H
L
A3 = B3
A2 = B2
A1 > B1
X
X
X
X
H
L
L
A3 = B3
A2 = B2
A1 < B1
X
X
X
X
L
H
L
A3 = B3
A2 = B2
A1 = B1
A0 > B0
X
X
X
H
L
L
A3 = B3
A2 = B2
A1 = B1
A0 < B0
X
X
X
L
H
L
A3 = B3
A2 = B2
A1 = B1
A0 = B0
H
L
L
H
L
L
A3 = B3
A2 = B2
A1 = B1
A0 = B0
L
H
L
L
H
L
A3 = B3
A2 = B2
A1 = B1
A0 = B0
L
L
H
L
L
H
PARALLEL CASCADING
A3 = B3
A2 = B2
A1 = B1
A0 = B0
X
X
H
L
L
H
A3 = B3
A2 = B2
A1 = B1
A0 = B0
H
H
L
L
L
L
A3 = B3
A2 = B2S
A1 = B1
A0 = B0
L
L
L
H
H
L
NOTE: H = High Voltage Level, L = Low Voltage, Level, X = Don’t Care
2
CD74HC85, CD74HCT85
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
190
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
VIH
-
-
2
1.5
-
-
1.5
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
-
1.5
-
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
3
CD74HC85, CD74HCT85
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
-
High Level Output
Voltage
CMOS Loads
VOH
VIH or VIL
PARAMETER
25oC
VCC
(V)
-40oC TO 85oC -55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5 to
5.5
2
-
-
2
-
2
-
V
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC and
GND
0
5.5
-
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note)
NOTE: For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
A0-A3, B0-B3 and (A = B) IN
1.5
(A > B) IN, (A < B) IN
1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.
360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
HC TYPES
Propagation Delay,
An, Bn to (A > B) OUT,
(A < B) OUT
tPLH, tPHL CL = 50pF
An, Bn to (A = B) OUT
-40oC TO
85oC
25oC
-55oC TO
125oC
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
195
-
245
-
295
ns
4.5
-
-
39
-
47
-
59
ns
CL = 15pF
5
-
16
-
-
-
-
-
ns
CL = 50pF
6
-
-
33
-
42
-
50
ns
tPLH, tPHL CL = 50pF
2
-
-
175
-
240
-
265
ns
4.5
-
-
35
-
44
-
53
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
6
-
-
30
-
37
-
45
ns
4
CD74HC85, CD74HCT85
Switching Specifications Input tr, tf = 6ns
PARAMETER
(Continued)
TEST
CONDITIONS
SYMBOL
(A > B) IN, (A < B) IN, (A = B) IN tPLH, tPHL CL = 50pF
to (A > B) OUT, (A < B) OUT
(A > B) IN to (A = B) OUT
Output Transition Times
(Figure 1)
CPD
CIN
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
140
-
175
-
210
ns
4.5
-
-
28
-
35
-
42
ns
5
-
11
-
-
-
-
-
ns
CL = 50pF
6
-
-
24
-
30
-
36
ns
2
-
-
120
-
150
-
180
ns
4.5
-
-
24
-
30
-
36
ns
CL = 15pF
5
-
9
-
-
-
-
-
ns
CL = 50pF
6
-
-
20
-
26
-
31
ns
-
5
-
24
-
-
-
-
-
pF
2
-
-
75
-
95
-
110
ns
tTLH, tTHL CL = 50pF
Input Capacitance
-55oC TO
125oC
CL = 15pF
tPLH, tPHL CL = 50pF
Power Dissipation Capacitance
(Notes 2, 3)
-40oC TO
85oC
25oC
-
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
-
-
-
10
-
10
-
10
pF
HCT TYPES
Propagation Delay,
An, Bn to (A > B) OUT,
(A < B) OUT
tPLH, tPHL CL = 50pF
CL = 15pF
4.5
-
-
37
-
46
-
56
ns
5
-
15
-
-
-
-
-
ns
An, Bn to (A = B) OUT
tPLH, tPHL CL = 50pF
4.5
-
-
40
-
50
-
60
ns
5
-
17
-
-
-
-
-
ns
CL = 15pF
(A > B) IN, (A < B) IN, (A = B) IN tPLH, tPHL CL = 50pF
to (A > B) OUT, (A < B) OUT
CL = 15pF
4.5
-
-
30
-
38
-
45
ns
5
-
12
-
-
-
-
-
ns
(A > B) IN to (A = B) OUT
tPLH, tPHL CL = 50pF
CL = 15pF
4.5
-
-
31
-
39
-
47
ns
5
-
13
-
-
-
-
-
ns
Output Transition Times
(Figure 1)
tTLH, tTHL CL = 50pF
4.5
-
-
15
-
19
-
22
ns
5
-
26
-
-
-
-
-
pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
CPD
Input Capacitance
CIN
-
NOTES:
4. CPD is used to determine the dynamic power consumption, per gate/package.
5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
tPHL
tf = 6ns
tr = 6ns
VCC
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
CD74HC85, CD74HCT85
Test Circuits and Waveforms
GND
VCC
GND
LEAST SIGNIFICANT
4-BITS OF EACH WORD
A0
A1
A2
A3
B0
B1
B2
B3
(A > B) IN
(A = B) IN
(A < B) IN
A0
A1
CD74HC85
A2 CD74HCT85
A3
B0
B1
B2
B3
(A > B) IN
(A = B) IN
(A < B) IN
A4
A5
A6
A7
B4
B5
B6
B7
MOST SIGNIFICANT
4-BITS OF EACH WORD
A4
A5
A6
A7
B4
B5
B6
B7
A0
A1
A2
A3
B0
B1
B2
B3
CD74HC85
CD74HCT85
(A > B) OUT
(A = B) OUT
(A < B) OUT
(A > B) IN
(A = B) IN
(A < B) IN
A0
A1
A2
A3
B0
B1
B2
B3
FIGURE 3. SERIES CASCADING - COMPARING 12-BIT WORDS
6
CD74HC85
CD74HCT85
(A > B) OUT
(A = B) OUT
(A < B) OUT
OUTPUTS
Test Circuits and Waveforms
B1
A1
B0
A0
GND
VCC
GND
CD74HC85
B3 CD74HCT85
A3
B2
A2 (A < B) OUT
B1 (A = B) OUT
A1 (A > B) OUT
B0
A0
(A < B) IN
(A = B) IN
(A > B) IN
B6
A6
B5
A5
B4
A4
B3
A3
B2
GND
A2
CD74HC85
B3 CD74HCT85
A3
B2
A2 (A < B) OUT
B1 (A = B) OUT
A1 (A > B) OUT
B0
A0
(A < B) IN
(A = B) IN
(A > B) IN
B11
A11
B10
A10
B9
A9
B8
A8
B7
GND
A7
CD74HC85
B3 CD74HCT85
A3
B2
A2 (A < B) OUT
B1 (A = B) OUT
A1 (A > B) OUT
B0
A0
(A < B) IN
(A = B) IN
(A > B) IN
NC
NC
OUTPUTS
B3 CD74HC85
CD74HCT85
A3
B2
A2 (A > B) OUT
B1 (A = B) OUT
A1 (A < B) OUT
B0
A0
(A < B) IN
(A = B) IN
(A > B) IN
FIGURE 4. PARALLEL CASCADING - COMPARING 12-BIT WORDS
7
OUTPUTS
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated