[ /Title (CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8) /Subject (High Speed Data sheet acquired from Harris Semiconductor SCHS147A October 1997 - Revised February 1999 CD74HC138, CD74HCT138, CD74HC238, CD74HCT238 High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer Inverting and Non-Inverting Features • Select One Of Eight Data Outputs Active Low for 138, Active High for 238 • l/O Port or Memory Selector • Three Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD74HC138, CD74HCT138, CD74HC238, CD74HCT238 (PDIP, SOIC) TOP VIEW A0 1 16 VCC A1 2 15 Y0 (Y0) A2 3 14 Y1 (Y1) E1 4 13 Y2 (Y2) E2 5 12 Y3 (Y3) E3 6 11 Y4 (Y4) (Y7) Y7 7 10 Y5 (Y5) GND 8 9 Y6 (Y6) Signal names in parentheses are for ’HC238 and ’HCT238. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 1999, Texas Instruments Incorporated 1 CD74HC138, CD74HCT138, CD74HC238, CD74HCT238 Description Ordering Information The Harris CD74HC138, CD74HC238 and CD74HCT138, CD74HCT238 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. Both circuits have three binary select inputs (A0, A1 and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC/HCT138 series will go low or which of the normally low outputs of the HC/HCT238 series will go high. PART NUMBER Two active low and one active high enables (E1, E2, and E3) are provided to ease the cascading of decoders. The decoder’s 8 outputs can drive 10 low power Schottky TTL equivalent loads. TEMP. RANGE (oC) CD74HC138E PACKAGE PKG. NO. CD74HCT138E -55 to 125 16 Ld PDIP E16.3 CD74HC238E -55 to 125 16 Ld PDIP E16.3 CD74HCT238E -55 to 125 16 Ld PDIP E16.3 CD74HC138M -55 to 125 16 Ld SOIC M16.15 CD74HCT138M -55 to 125 16 Ld SOIC M16.15 CD74HC238M -55 to 125 16 Ld SOIC M16.15 CD74HCT238M -55 to 125 16 Ld SOIC M16.15 CD74HC138SM -55 to 125 16 Ld SSOP M16.209 NOTES: Ordering Information PART NUMBER TEMP. RANGE (oC) -55 to 125 PACKAGE 16 Ld PDIP 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. PKG. NO. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. E16.3 Functional Diagram HC/HCT HC/HCT 238 138 A0 1 15 2 14 3 13 A1 A2 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 12 4 11 5 10 6 9 E1 E2 E3 7 TRUTH TABLE CD74HC138, CD74HCT138 INPUTS ENABLE ADDRESS OUTPUTS E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H L X X X X X H H H H H H H H X H X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H 2 CD74HC138, CD74HCT138, CD74HC238, CD74HCT238 TRUTH TABLE CD74HC138, CD74HCT138 INPUTS ENABLE ADDRESS OUTPUTS E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L Y5 Y6 Y7 NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care TRUTH TABLE CD74HC238, CD74HCT238 INPUTS ENABLE ADDRESS A1 OUTPUTS E2 E1 A2 X X H X X X L L L L L L L L L X X X X X L L L L L L L L E3 A0 Y0 Y1 Y2 Y3 Y4 X H X X X X L L L L L L L L H L L L L L H L L L L L L L H L L L L H L H L L L L L L H L L L H L L L H L L L L L H L L L H H L L L H L L L L H L L H L L L L L L H L L L H L L H L H L L L L L H L L H L L H H L L L L L L L H L H L L H H H L L L L L L L H NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care 3 CD74HC138, CD74HCT138, CD74HC238, CD74HCT238 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 4 CD74HC138, CD74HCT138, CD74HC238, CD74HCT238 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS A0-A2 1.5 E1, E2 1.25 E3 1 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 13 - - - - - ns CL = 50pF 6 - - 26 - 33 - 38 ns HC TYPES Propagation Delay tPLH, tPHL CL = 50pF Address to Output 5 Switching Specifications Input tr, tf = 6ns PARAMETER TEST CONDITIONS SYMBOL Enable to Output HC/HCT138 (Continued) tPLH, tPHL CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF Power Dissipation Capacitance, (Notes 5, 6) CPD Input Capacitance CIN CL = 15pF - -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 150 - 190 - 265 ns 4.5 - - 30 - 38 - 53 ns 6 - - 26 - 33 - 45 ns 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns 5 - 67 - - - - - pF - - - 10 - 10 - 10 pF 4.5 - - 35 - 44 - 53 ns 5 - 14 - - - - - ns HCT TYPES Propagation Delay Address to Output tPLH, tPHL CL = 50pF CL = 15pF Enable to Output HC/HCT138 tPLH, tPHL CL = 50pF 4.5 - - 35 - 44 - 53 ns Enable to Output HC/HCT238 tPLH, tPHL CL = 15pF 4.5 - - 40 - 50 - 60 ns Output Transition Time (Figure 2) tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns 5 - 67 - - - - - pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance, (Notes 5, 6) CPD Input Capacitance CIN CL = 15pF - NOTES: 5. CPD is used to determine the dynamic power consumption, per gate. 6. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPLH tPHL FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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