Pr E2L0034-17-Y1 el The OKI MSM5412222 is a high performance 3-Mbit, 256K ¥ 12-bit, Field Memory. It is especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. MSM5412222 is a FRAM for wide or low end use in general commodity TVs and VTRs exclusively. MSM5412222 is not designed for high end use in medical systems, professional graphics systems which require long term picture storage, data storage systems and others. Two or more MSM5412222s can be cascaded directly without any delay devices between them. (Cascading provides larger storage depth or a longer delay). Each of the 12-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The MSM5412222 provides high speed FIFO, First-In First-Out, operation without external refreshing: MSM5412222 refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MSM5412222’s function is simple, and similar to a digital delay device whose delay-bitlength is easily set by reset timing. The delay length, and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 12-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. Additionally, the MSM5412222 has a write mask function or input enable function (IE), and readdata skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to MSM5412222. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in picture” on a TV screen. The MSM5412222 is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514222B and 2-Mbit Field Memory MSM518222. Three MSM514222Bs or one MSM514222B plus one MSM518222 can be replaced simply by one MSM5412222. 1/15 y DESCRIPTION ar 262,214-Word ¥ 12-Bit Field Memory in This version: Jan. 1998 MSM5412222 Previous version: Dec. 1996 im ¡ Semiconductor MSM5412222 ¡ Semiconductor ¡ Semiconductor MSM5412222 FEATURES • Single power supply : 5 V ±10% • 512 Rows ¥ 512 Columns ¥ 12 bits • Fast FIFO (First-In First-Out) operation • High speed asynchronous serial access Read/write cycle time 25 ns/30 ns Access time 23 ns/25 ns • Direct cascading capability • Write mask function (Input enable control) • Data skipping function (Output enable control) • Self refresh (No refresh control is required) • Package options: 44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM5412222-xxTS-K) 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM5412222-xxJS) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) Cycle Time (Min.) MSM5412222-25TS-K 23 ns 25 ns MSM5412222-30TS-K 25 ns 30 ns MSM5412222-25JS 23 ns 25 ns MSM5412222-30JS 25 ns 30 ns Package 400 mil 44-pin TSOP (II) 400 mil 40-pin SOJ 2/15 ¡ Semiconductor MSM5412222 PIN CONFIGURATION (TOP VIEW) VSS DIN11 DIN10 NC DIN9 DIN8 DIN7 DIN6 NC DIN5 DIN4 DIN3 DIN2 NC DIN1 DIN0 SWCK RSTW NC WE IE VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS DOUT11 DOUT10 NC DOUT9 DOUT8 DOUT7 DOUT6 NC DOUT5 DOUT4 DOUT3 DOUT2 VSS DOUT1 DOUT0 SRCK RSTR NC RE OE VCC 44-Pin Plastic TSOP (II) (K Type) VSS 1 40 VSS NC 2 39 NC DIN11 3 38 DOUT11 DIN10 4 37 DOUT10 DIN9 5 36 DOUT9 DIN8 6 35 DOUT8 DIN7 7 34 DOUT7 DIN6 8 33 DOUT6 DIN5 9 32 DOUT5 DIN4 10 31 DOUT4 DIN3 11 30 DOUT3 DIN2 12 29 DOUT2 DIN1 13 28 DOUT1 DIN0 14 27 DOUT0 SWCK 15 26 SRCK RSTW 16 25 RSTR WE 17 24 RE IE 18 23 OE NC 19 22 VSS VCC 20 21 VCC 40-Pin Plastic SOJ Pin Name Function SWCK Serial Write Clock SRCK Serial Read Clock WE Write Enable RE Read Enable IE Input Enable OE Output Enable RSTW Write Reset Clock RSTR Read Reset Clock DIN0 - 11 DOUT0 - 11 Data Input Data Output VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 3/15 RE Data-out Buffer (¥ 12) Serial Read RSTR SRCK Controller 512 Word Serial Read Register (¥ 12) Read Line Buffer Low-Half (¥ 12) Read Line Buffer High-Half (¥ 12) 256 (¥ 12) 256 (¥ 12) 71 Word Sub-Register (¥ 12) ¡ Semiconductor OE BLOCK DIAGRAM DOUT (¥ 12) 256K (¥ 12) Memory Array X Decoder Read/Write and Refresh Controller 71 Word Sub-Register (¥ 12) 256 (¥ 12) Write Line Buffer Low-Half (¥ 12) 256 (¥ 12) Clock Oscillator Write Line Buffer High-Half (¥ 12) 512 Word Serial Write Register (¥ 12) VBB Generator Serial Read DIN (¥ 12) IE WE Controller RSTW SWCK MSM5412222 4/15 Data-in Buffer (¥ 12) ¡ Semiconductor MSM5412222 OPERATION Write Operation The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e. SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle. Note that every write timing of MSM5412222 is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Write Reset : RSTW The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE and IE are ignored in the write reset cycle. Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Data Inputs : DIN0 - 11 Write Clock : SWCK The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Write Enable : WE WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MSM5412222 is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK. Input Enable : IE IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are referenced to the rising edge of SWCK. 5/15 ¡ Semiconductor MSM5412222 Read Operation The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is accomplished by cycling SRCK, and holding RE high after the read address pointer reset operation or RSTR. Each read operation, which begins after RSTR, must contain at least 80 active read cycles, i.e. SRCK cycles while RE is high. Read Reset : RSTR The first positive transition of SRCK after RSTR becomes high resets the read address counters to zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states of RE and OE are ignored in the read reset cycle. Before RSTR may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles. Data Out : DOUT0 - 11 Read Clock : SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read operation. The SRCK input increments the internal read address pointer when RE is high. The three-state output buffer provides direct TTL compatibility ( no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK. *There are no output valid time restriction on MSM5412222. Read Enable : RE The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. Output Enable : OE OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced to the rising edge of SRCK. 6/15 ¡ Semiconductor MSM5412222 Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 ms after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 ms stabilization interval, the following initialization sequence must be performed. Because the read and write address counters are not valid after power-up, a minimum of 80 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy write cycles/RSTW and dummy read cycles/RSTR may occur simultaneously. If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is necessary to perform an RSTR operation plus a minimum of 80 SRCK cycles plus another RSTR operation, and an RSTW operation plus a minimum of 80 SRCK cycles plus another RSTW operation to properly initialize read and write address pointers. Old/New Data Access There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the next RSTW operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 70 SWCK cycles. If the RSTR operation for the first field readout occurs less than 70 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called “old data”. In order to read out “new data”, i.e., the second field written in, the delay between an RSTW operation and an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. It may be “old data” or “new” data, or a combination of old and new data. Such a timing should be avoided. Cascade Operation The MSM5412222 is designed to allow easy cascading of multiple memory devices. This provides higher storage depth, or a longer delay than can be achieved with only one memory device. 7/15 ¡ Semiconductor MSM5412222 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Input Output Voltage VT at Ta = 25°C, VSS –1.0 to 7.0 V Output Current IOS Ta = 25°C 50 mA Power Dissipation PD Ta = 25°C 1 W Operating Temperature Topr — 0 to 70 °C Storage Temperature Tstg — –55 to 150 °C Recommended Operating Conditions Symbol Min. Typ. Max. Unit Power Supply Voltage Parameter VCC 4.5 5.0 5.5 V Power Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.4 VCC VCC + 1 V Input Low Voltage VIL –1.0 0 0.8 V DC Characteristics Parameter Symbol Condition Min. Max. Unit ILI 0 < VI < VCC + 1, Other Pins Tested at V = 0 V –10 10 mA Output Leakage Current ILO 0 < VO < VCC –10 10 mA Output "H" Level Voltage VOH IOH = –1 mA 2.4 — V Output "L" Level Voltage VOL IOL = 2 mA V Input Leakage Current Operating Current ICC1 Standby Current ICC2 Minimum Cycle Time, Output Open Input Pin = VIH / VIL — 0.4 -25 — 100 -30 — 90 — 5 Capacitance mA mA (Ta = 25°C, f = 1 MHz) Parameter Symbol Max. Unit Input Capacitance (DIN, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE) CI 7 pF Output Capacitance (DOUT) CO 10 pF 8/15 ¡ Semiconductor MSM5412222 AC Characteristics Parameter Access Time from SRCK (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol MSM5412222-25 MSM5412222-30 Min. Max. Min. Max. Unit tAC — 23 — 25 ns DOUT Hold Time from SRCK tDDCK 6 — 6 — ns DOUT Enable Time from SRCK tDECK 6 23 6 25 ns SWCK "H" Pulse Width tWSWH 9 — 12 — ns SWCK "L" Pulse Width tWSWL 10 — 12 — ns Input Data Setup Time tDS 2 — 2 — ns Input Data Hold Time tDH 4 — 4 — ns WE Enable Setup Time tWENS 0 — 0 — ns WE Enable Hold Time tWENH 3 — 3 — ns WE Disable Setup Time tWDSS 0 — 0 — ns WE Disable Hold Time tWDSH 3 — 3 — ns IE Enable Setup Time tIENS 0 — 0 — ns IE Enable Hold Time tIENH 3 — 3 — ns IE Disable Setup Time tIDSS 0 — 0 — ns IE Disable Hold Time tIDSH 3 — 3 — ns WE "H" Pulse Width tWWEH 5 — 10 — ns WE "L" Pulse Width tWWEL 5 — 10 — ns IE "H" Pulse Width tWIEH 5 — 10 — ns IE "L" Pulse Width tWIEL 5 — 10 — ns RSTW Setup Time tRSTWS 0 — 0 — ns RSTW Hold Time tRSTWH 3 — 3 — ns SRCK "H" Pulse Width tWSRH 9 — 12 — ns SRCK "L" Pulse Width tWSRL 10 — 12 — ns RE Enable Setup Time tRENS 0 — 0 — ns RE Enable Hold Time tRENH 3 — 3 — ns RE Disable Setup Time tRDSS 0 — 0 — ns RE Disable Hold Time tRDSH 3 — 3 — ns OE Enable Setup Time tOENS 0 — 0 — ns OE Enable Hold Time tOENH 3 — 3 — ns OE Disable Setup Time tODSS 0 — 0 — ns OE Disable Hold Time tODSH 3 — 3 — ns tOEZ 17 — 17 — ns tWREH 5 — 10 — ns RE "L" Pulse Width tWREL 5 — 10 — ns OE "H" Pulse Width tWOEH 5 — 10 — ns OE "L" Pulse Width tWOEL 5 — 10 — ns RSTR Setup Time tRSTRS 0 — 0 — ns RSTR Hold Time tRSTRH 3 — 3 — ns SWCK Cycle Time tSWC 25 — 30 — ns SRCK Cycle Time tSRC 25 — 30 — ns tT 3 30 3 30 ns Output Buffer Turn-off Delay Time from OE RE "H" Pulse Width Transition Time (Rise and Fall) 9/15 ¡ Semiconductor MSM5412222 Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and VIL = 0 V. The transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and VIL = 0 V. 2. AC measurements assume tT = 3 ns. 3. Read address must have more than a 600 address delay than write address in every cycle when asynchronous read/write is performed. 4. Read must have more than a 600 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called "new data read". When read has less than a 70 address delay than write, the read data are the data written in a previous series of write cycles which had been written before at last write reset cycle: this is called "old data read". 5. When the read address delay is between more than 71 and less than 599, read data will be undetermined. However, normal write is achieved in this address condition. 6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are VOH = 2.0 V and VOL = 0.8 V. 10/15 ¡ Semiconductor MSM5412222 TIMING WAVEFORM Write Cycle Timing (Write Reset) n cycle 0 cycle 1 cycle 2 cycle VIH VIL SWCK tWSWH tWSWL tRSTWH tRSTWS ,, ,, tT tSWC RSTW VIH VIL tDH tDS DIN n-1 n 0 1 2 VIH VIL WE VIH VIL IE VIH VIL Write Cycle Timing (Write Enable) n cycle Disable cycle Disable cycle n+1 cycle SWCK tWENH tWDSH tWDSS tWENS WE tWWEL DIN IE RSTW n-1 VIH VIL VIH VIL tWWEH n n+1 VIH VIL VIH VIL VIH VIL 11/15 ¡ Semiconductor MSM5412222 ,, , Write Cycle Timing (Input Enable) n cycle n+1 cycle n+2 cycle n+3 cycle VIH VIL SWCK tIENH tIDSH tIDSS tIENS VIH VIL IE tWIEL DIN n-1 tWIEH n n+3 VIH VIL VIH VIL WE VIH VIL RSTW ,, , Read Cycle Timing (Read Reset) n cycle 0 cycle 1 cycle VIH VIL SRCK tT RSTR tWSRH tRSTRH tRSTRS tWSRL tSRC RE OE n-1 VIH VIL tDDCK tAC DOUT 2 cycle n 0 1 2 VOH VOL VIH VIL VIH VIL 12/15 ¡ Semiconductor MSM5412222 Read Cycle Timing (Read Enable) , , , , , n cycle SRCK disable cycle tRENH RE tRDSH tWREL DOUT OE RSTR disable cycle tRDSS n+1 cycle VIH VIL tRENS VIH VIL tWREH n-1 n n+1 VOH VOL VIH VIL VIH VIL Read Cycle Timing (Output Enable) n cycle SRCK n+1 cycle tODSH RE RSTR tODSS tOENS VIH VIL tWOEN DOUT n+3 cycle VIH VIL tOENH OE n+2 cycle n-1 n tWOEH tDECK Hi-Z n+3 VOH VOL VIH VIL VIH VIL 13/15 ¡ Semiconductor MSM5412222 PACKAGE DIMENSIONS (Unit : mm) TSOPII44-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.54 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/15 ¡ Semiconductor MSM5412222 (Unit : mm) SOJ40-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/15