OKI MS81V06160

Semiconductor
MS81V06160
This version: Sep. 2000
Preliminary
(401,408-word × 16-bit) FIFO memory
GENERAL DESCRIPTION
The MS81V06160 is a 6Mb FIFO (First-In First-Out) memory designed for 401,408-words × 16-bit high-speed
asynchronous read/write operation.
The MS81V06160 is best suited for a field memory for digital TVs or LCD panels which require high-speed, large
memory , and is not designed for high end use in professional graphics systems, which require long term picture
storage and data storage.
The MS81V06160 is provided with independent control clocks to support asynchronous read and write operations.
Different clock rates are also supported, which allow alternate data rates between write and read data streams.
The first data read operation can be performed after 1600 ns + 4 cycles from read reset and the first data write
operation is enabled after 1600 ns + 4 cycles from write reset. Thereafter, the high-speed read/write operation is
possible every cycle time.
Additionally, a write mask function by IE pin and a read-data skipping function by OE pin implement image data
processing easily.
The MS81V06160 provides high speed FIFO (First-in First-out) operation without external refreshing:
MS81V06160 refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access
operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the
power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration
logic.
The MS81V06160’s function is simple, and similar to a digital delay device whose delay-bit- length is easily set by
reset timing. The delay length and the number of read delay clocks between write and read, is determined by
externally controlled write and read reset timings. The MS81V06160 uses a thin and small 70-pin plastic TSOP.
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Semiconductor
MS81V06160
FEATURES
•
•
•
•
•
•
•
•
•
401,408 words × 16 bits
Fast FIFO (First-In First-Out) operation: 12 ns cycle time
Self refresh (No refresh control is required)
High speed asynchronous serial access
Read/Write Cycle Time
12 ns/15 ns
Access Time
9 ns/12 ns
Variable length delay bit (600 to 401,408)
Write mask function (Output enable control)
Cascading capability
Single power supply: 3.3 V ± 10%
Package:
70-pin plastic TSOP TYPE II (TSOP II 70-P-400-0.5-K) (Product name: MS81V06160-xxTA)
xx indicates speed rank.
MS81V06160-TA
Parameter
Symbol
–12
–15
Access Time
tAC
9 ns
12 ns
Read/Write
Cycle Time
tSWC
tSRC
12 ns
15 ns
Operation current
Icc1
210 mA
170 mA
Standby current
Icc2
6 mA
6 mA
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Semiconductor
MS81V06160
PIN CONFIGURATION (TOP VIEW)
VCC
NC
NC
NC
VSS
DI0
DI1
DI2
DI3
VSS
DO0
DO1
VCC
DO2
DO3
VSS
VSS
VCC
VCC
DO4
DO5
VCC
DO6
DO7
VSS
DI4
DI5
DI6
DI7
VSS
OE
RE
RSTR
SRCK
VCC
1
70
2
69
3
68
4
67
5
66
6
65
7
64
8
63
9
62
10
61
11
60
12
59
13
58
14
57
15
56
16
55
17
54
18
53
19
52
20
51
21
50
22
49
23
48
24
47
25
46
26
45
27
44
28
43
29
42
30
41
31
40
32
39
33
38
34
37
35
36
VSS
NC
NC
NC
VCC
DI15
DI14
DI13
DI12
VSS
DO15
DO14
VCC
DO13
DO12
VSS
VSS
VCC
VCC
DO11
DO10
VCC
DO9
DO8
VSS
DI11
DI10
DI9
DI8
VCC
IE
WE
RSTW
SWCK
VSS
70-pin Plastic TSOP
SWCK
SRCK
WE
Serial Write Clock
Serial Read Clock
Write Enable
RE
Read Enable
IE
Input Enable
OE
Output Enable
RSTW
Reset Write
RSTR
Reset Read
DI0-15
Data Input
DO0-15
Data Output
VSS
Ground (0 V)
VCC
Power Supply (3.3 V)
NC
No Connection
Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage
level must be provided to every VSS pin.
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Semiconductor
MS81V06160
BLOCK DIAGRAM
DO (X16)
OE
Data-output
Buffer
RE
Serial
RSTR
Read
SRCK
Controller
Read Data Register
(X16)
401,408 x 16
X
Decoder
Memory
Read/Write
Refresh
Timing Generater
Array
(X16)
Refresh
Counter
Write Data Register
Serial
Data-input
Buffer
DI (X16)
IE
WE
Write
Controller
RSTW
SWCK
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Semiconductor
MS81V06160
PIN DESCRIPTION
Data Inputs: (DI0-15)
These pins are used for serial data inputs.
Write Reset: RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW
setup and hold times are referenced to the rising edge of SWCK.
Write Enable: WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the
input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)
restrictions, because the MS8106160 is in fully static operation as long as the power is on. Note that WE setup and
hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 2.
After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at
address 0 is started after a time tWL form the cycle in which WE is brought high.
After write reset, WE should be remained high for 2 cycles after driving WE high first.
Input Enable: IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer
is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are
referenced to the rising edge of SWCK. The latency for the write operation control by IE is 2.
Data Out: (DO0-15)
These pins are used for serial data outputs.
Read Reset: RSTR
The first positive transition of SRCK after RSTR becomes high resets the read address pointers to zero.
RSTR setup and hold times are referenced to the rising edge of SRCK.
Read Enable: RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the
rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE
setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the
SRCK clock.
The latency for the read operation control by RE is 2. After read reset, RE must remain low for more than 1600 ns
(tFRD). After read reset, the read data at address 0 is output after a time tRL from the cycle in which WE is brought
high.
After read reset, RE should be remained high for 2 cycles after driving RE high first.
Output Enable: OE
OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is
always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced
to the rising edge of SRCK. The latency for the read operation control by OE is 2.
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Semiconductor
MS81V06160
Serial Write Clock: SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.
Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.
Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read
operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of
SRCK. *There are no output valid time restriction on MS8106160.
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Semiconductor
MS81V06160
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Rating
Power Supply Voltage
Parameter
VCC
Ta = 25°C
• 0.5 to +4.6
Unit
V
Input Output Voltage
VT
Ta = 25°C, VSS
• 0.5 to +4.6
V
Output Current
IOS
Ta = 25°C
50
mA
Power Dissipation
PD
Ta = 25°C
1
W
Operating Temperature
Topr
—
0 to 70
°C
Storage Temperature
Tstg
—
• 55 to +150
°C
Recommended Operating Conditions
Symbol
Min.
Typ.
Max.
Unit
Power Supply voltage
Parameter
VCC
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
VCC
VCC + 0.2
V
Input Low Voltage
VIL
• 0.3
0
0.8
V
DC Characteristics
Parameter
Symbol
Condition
Min.
Max.
Unit
ILI
0 < VI < VCC,
Other Pins Tested at V = 0 V
–10
+10
µΑ
Output Leakage Current
ILO
0 < VO < VCC
–10
+10
µΑ
Output “H” Level Voltage
VOH
IOH = –2 mA
2.4
—
V
Output “L” Level Voltage
VOL
V
Input Leakage Current
IOH = 2 mA
Operating Current
ICC1
Minimum Cycle Time
Output Open
Standby Current
ICC2
Input Pin = VIH/VIL
—
0.4
–12
—
210
–15
—
170
–12
—
6
–15
—
6
mA
mA
Capacitance
(VCC = 3.3 V ± 0.3 V, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Max.
Unit
Input Capacitance
CI
5
pF
Output Capacitance
CO
7
pF
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Semiconductor
MS81V06160
AC Characteristics
(VCC = 3.3 V ± 10%, Ta = 0 to 70°C)
Parameter
Access Time from SRCK
Symbol
MS81V06160-12
MS81V06160-15
Min.
Max.
Min.
Max.
Unit
tAC
—
9
—
12
ns
tDDCK
3
—
3
—
ns
DOUT Enable Time from SRCK
tDECK
3
9
3
12
ns
SWCK “H” Pulse Width
tWSWH
4
—
6
—
ns
SWCK “L” Pulse Width
tWSWL
4
—
6
—
ns
Input Data Setup Time
tDS
3
—
3
—
ns
Input Data Hold Time
tDH
1
—
1.5
—
ns
WE Enable Setup Time
tWENS
3
—
3
—
ns
WE Enable Hold Time
tWENH
1
—
1.5
—
ns
WE Disable Setup Time
tWDSS
3
—
3
—
ns
WE Disable Hold Time
tWDSH
1
—
1.5
—
ns
IE Enable Setup Time
tIENS
3
—
3
—
ns
IE Enable Hold Time
tIENH
1
—
1.5
—
ns
IE Disable Setup Time
tIDSS
3
—
3
—
ns
IE Disable Hold Time
tIDSH
1
—
1.5
—
ns
WE “H” Pulse Width
tWWEH
4
—
6
—
ns
WE “L” Pulse Width
tWWEL
4
—
6
—
ns
IE “H” Pulse Width
tWIEH
4
—
6
—
ns
IE “L” Pulse Width
tWIEL
4
—
6
—
ns
RSTW Setup Time
tRSTWS
3
—
3
—
ns
RSTW Hold Time
tRSTWH
1
—
1.5
—
ns
SRCK “H” Pulse Width
tWSRH
4
—
6
—
ns
SRCK “L” Pulse Width
tWSRL
4
—
6
—
ns
RE Enable Setup Time
tRENS
3
—
3
—
ns
RE Enable Hold Time
tRENH
1
—
1.5
—
ns
RE Disable Setup Time
tRDSS
3
—
3
—
ns
RE Disable Hold Time
tRDSH
1
—
1.5
—
ns
OE Enable Setup Time
tOENS
3
—
3
—
ns
OE Enable Hold Time
tOENH
1
—
1.5
—
ns
OE Disable Setup Time
tODSS
3
—
3
—
ns
OE Disable Hold Time
tODSH
1
—
1.5
—
ns
RE “H” Pulse Width
tWREH
4
—
6
—
ns
RE “L” Pulse Width
tWREL
4
—
6
—
ns
OE “H” Pulse Width
tWOEH
4
—
6
—
ns
OE “L” Pulse Width
tWOEL
4
—
6
—
ns
RSTR Setup Time
tRSTRS
3
—
3
—
ns
RSTR Hold Time
tRSTRH
1
—
1.5
—
ns
SWCK Cycle Time
tSWC
12
—
15
—
ns
SRCK Cycle Time
tSRC
12
—
15
—
ns
Transition Time (Rise and Fall)
tT
1
5
1
5
ns
WE “L” Period before W Reset
tLWE
3
—
3
—
clk
RE “L” Period before R Reset
tLRE
3
—
3
—
clk
RE Delay after Reset
tFRD
1,600
—
1,600
—
ns
WE Delay after Reset
tFWD
1,600
—
1,600
—
ns
DOUT Hold Time from SRCK
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Semiconductor
Parameter
MS81V06160
Symbol
MS81V06160-12, MS81V06160-15
Unit
Write Latency
tWL
4
clk
Read Latency
tRL
4
clk
WE Write Control Latency
tWEL
2
clk
IE Write Control Latency
tIEL
2
clk
RE Read Control Latency
tREL
2
clk
OE Read Control Latency
tOEL
2
clk
AC Characteristic Measuring Conditions
Output Compare Level
Output Load
Input Signal Level
1.4 V
1 TTL + 30 pF
3.0 V/0.0 V
Input Signal Rise/Fall Time
1 ns
Input Signal Measuring Reference Level
1.4 V
Note: Input voltage levels for the AC characteristic measurement are VIH = 3.0 V and VIL = 0 V.
When transition time tT becomes 1 ns or more, the input signal reference levels for the parameter
measurement are VIH (min.) and VIL (max.).
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Semiconductor
MS81V06160
OPERATION MODE
Write Operation Cycle
The write operation is controlled by four control signals, SWCK, RSTW, WE, and IE. The write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW.
RSTW must be performed for internal circuit initialization before write operation. WE must be low before and
after the reset cycle (tLWE + tFWD).
Each write operation, which begins after RSTW must contain at least 231 active write cycles, i.e., SWCK cycles
while WE and IE are high.
Settings of WE and IE to the operation mode of Write address pointer and Data input.
WE
IE
H
H
H
L
L
X
Internal Write address pointer
Incremented
Halted
Data input (Latency 2)
Input
Not input
X indicates "don't care"
Read Operation Cycle
The read operation is controlled by four control signals, SRCK, RSTR, RE, and OE. The read operation is
accomplished by cycling SRCK, and holding both RE and OE high after the read address pointer reset operation or
RSTR.
Each read operation, which begins after RSTR, must contain at least 231 active read cycles, i.e., SRCK cycles
while RE and OE are high. RE must be low before and after the reset cycle (tLRE + tFWD).
Settings of RE and OE to the operation mode of read address pointer and Data output.
RE
OE
H
H
H
L
L
H
L
L
Internal Read address pointer
Incremented
Halted
Data output (Latency 2)
Output
High impedance
Output
High impedance
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 200 µs after Vcc has stabilized to a
value within the range of recommended operating conditions. After this 200 µs stabilization interval, the following
initialization sequence must be performed. Because the read and write address pointers are undefined after
power-up, a minimum of 330 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be
performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read
address pointer.
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Semiconductor
MS81V06160
Old/New Data Access
There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory.
If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the
next RSTW operation), then the data just written will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second field of
data for as many as 70 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 70 SWCK
cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that
the first field will still be read out. The first field of data that is read out while the second field of data is written is
called “old data”. In order to read out “new data”, i.e., the second field written in, read reset must be input after
write address 200 the delay between an RSTW operation and an RSTR operation must be at least 600 SRCK cycles.
If the delay between RSTW and RSTR operations is more than 71 but less than 600 cycles, then the data read out
will be undetermined. It may be “old data” or “new” data, or a combination of old and new data. Such a timing
should be avoided.
When the read address delay is between more than 71 and less than 599 or more than 401,408, read data will be
undetermined. However, normal write is achieved in this address codition.
11/18
Semiconductor
MS81V06160
TIMING DIAGRAM
Write Cycle Timing (Write Reset)
tSWC
tWSWH
SWCK
0 cycle
tWSWL
tRSTWS
tRSTWH
RSTW
tDS
tDH
DI 0-15
Dn-1
tWL
Dn
D0
D1
tFWD
tLWE
WE
IE
*After write reset, WE should be remained high for 2 cycles after driving WE high first.
Write Cycle Timing (Write Enable)
1 cycle
2 cycle
3cycle
4 cycle
5 cycle 6 cycle
SWCK
tWWEH
tWWEL
WE
tWENH
DI 0-15
D0
tWDSH
D1
D2
tWDSS
tWENS
D4
D3
D5
D6
D7
tWEL
RSTW
IE
L
H
12/18
Semiconductor
MS81V06160
Write Cycle Timing (Input Enable)
1 cycle
2 cycle
3 cycle
4 cycle
tWIEL
tWIEH
5 cycle
6 cycle
7 cycle
8 cycle
9 cycle 10 cycle
SWCK
IE
tIENH
DI 0-15
D0
tIDSS
tIDSH
D1
D3
D2
tIENS
D8
D9
D10
D11
tIEL
RSTW
L
H
WE
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Semiconductor
MS81V06160
Read Cycle Timing (Read Reset)
tSRC
tWSRH
SRCK
0 cycle
1 cycle
tWSRL
tRSTRH
tRSTRS
tRL
RSTR
tAC
tFRD
DO 0-15
Qn-1
Qn
Q0
Q1
Q6
Q7
tLRE
RE
H
OE
*After write reset, RE should be remained high for 2 cycles after driving RE high first.
Read Cycle Timing (Read Enable)
1 cycle
2 cycle
3 cycle
4 cycle
5 cycle
SRCK
tWREH
tWREL
RE
tRENH
DO 0-15
Q0
tRDSH
Q1
Q2
tRDSS
Q3
tRENS
tAC
Q4
Q5
tREL
RSTR
L
H
OE
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Semiconductor
MS81V06160
Read Cycle Timing (Output Enable)
1 cycle
2 cycle
3 cycle
4 cycle
5 cycle
6 cycle
7 cycle
8 cycle
9 cycle
10 cycle 11 cycle
SRCK
tWOEH
tWOEL
OE
tOENH
tODSH
tODSS
tOENS
tAC
tDDCK
DO 0-15
Q0
Q1
Q3
Q2
tOEL
RSTR
Q8
Q9
Q10
Q11
tDECK
L
H
RE
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Semiconductor
Read/Write Cycle Timing (New Data Read)
MS81V06160
16/18
Semiconductor
Read/Write Cycle Timing (Old Data Read)
MS81V06160
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MS81V06160
Read/Write Cycle Timing
Semiconductor
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