OKI Semiconductor
ML87V3104
FEDL87V3104-03
Issue Date: Nov. 28, 2003
LCD Display Controller with Embedded Display Memory
GENERAL DESCRIPTION
The ML87V3104 is an LCD graphic display controller intended for use in medium to small-sized equipment
having such as QVGA grade medium-sized LCD panels, such as PDA or portable information terminals.
Since this LSI device has an internal display memory, use of this device reduces the component count. It is
possible to set an easy to use configuration of the display memory size, such as 1024 × 1024 dots × 4 bits or 2048
× 256 dots × 8 bits, depending on the application at hand, and it is possible to access the image data without having
to be concerned about address conversion.
The area specified in the display memory can be output on the display.
The display data and the control information can be set by the host CPU.
FEATURES
• Display memory:
Horizontal 4096 dots, maximum, vertical 4096 dots, maximum (with restrictions)
• Display size:
Horizontal 1024 dots, maximum, vertical 1024 dots, maximum (with restrictions)
suitable for QVGA (320 × 240) or HVGA (640 × 240, 480 × 320)
• Number of display colors:
16/256 Colors out of 4096 colors (pseudo-colors)
4096/65536 Colors (direct colors)
• Color palette:
256 Colors × 12 bits (R4, G4, B4)
• Output data:
STN 4/8 bits parallel,
TFT 12 bits (R4, G4, B4) / 16 bits (R5, G6, B5)
• Display functions:
Scroll (in units of 16 horizontal pixels and 1 vertical line),
Sub-screen display (any position, pseudo-color mode only)
Hardware cursor (16 × 16 × 2 bits)
• LCD Drive signals:
Duty 1/64 to 1/1024, up to 16-gray levels,
Programmable AC driving signal (Toggle period can be specified.)
• Host CPU: 8/16 bits
(68k- Series, 80-Series, RISCs of different companies, etc.)
• Embedded memory:
4M bit DRAM
• Operating frequency:
15 MHz, maximum
• Power supply voltages:
3.3 V ± 0.3 V
• Package:
100-Pin plastic TQFP (TQFP100-P-1414-0.50-K)
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BLOCK DIAGRAM
Display
Memory
(4M bit DRAM)
ADRS
C
Conv.
Memory
Controller
Color
Palette
Output
Format
to LCD
P
CPU
Bus
(8/16bits)
U
I/F
Config.
Cursor Gen.
Timing Gen.
Reg.
LCD Interface
LCD control
signals
APPLICATION CIRCUIT
The following is an example of application to a handy terminal for POS systems.
System
BUS
Key
16-bit
MCU
RAM
ROM
PC
Card
Barcode Serial I/F
Scanner
ML87V3104
QVGA
Color STN
LCD module
Touch Panel
Peripheral
Interface
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ML87V3104
PIN CONFIGURATION (TOP VIEW)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
D00
D01
D02
D03
VDDI
D04
D05
D06
D07
(NC)
(NC)
(NC)
VSS
AD00
AD01
VDDI
AD02
AD03
AD04
AD05
VSS
AD06
AD07
AD08
AD09
100-pin Plastic TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TQFP100-P-1414-0.50-K
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(NC)
AD10
AD11
(NC)
AD12
AD13
(NC)
VDDI
AD14
AD15
A16
A17
VSS
A18
VDDI
PORT1
PORT0
(TOUT)
(NC)
VSS
DDD0
DDD1
DDD2
DDD3
(NC)
(NC)
DISP
DF
FRP
LCP
VSS
DDA3
DDA2
DDA1
DDA0
VDDO
CPS
CP
(NC)
VSS
(NC)
DDB3
DDB2
DDB1
DDB0
VDDO
DDC3
DDC2
DDC1
DDC0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
(NC)
CSN
REN
WEN
BSN
VSS
DSN
BSYN
REGS
BCLK
VDDI
XOSCI
(NC)
XOSCO
VSS
RESETN
(NC)
HMOD3
HMOD2
VDDI
HMOD1
HMOD0
TEST1
TEST0
(NC)
NC: No-connection pins These pins should be left open during normal use.
Please supply the same voltage to all the “VDDI” pins, also “VDDO” pins.
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PIN DESCRIPTIONS
Table P1. List of pins and their descriptions
Pin
Symbol
I/O
Type
Description
27
DISP
O
4mA drive
LCD Display enable
28
DF
O
4mA drive
LCD AC driving signal pin
29
FRP
O
4mA drive
LCD Frame pulse
30
LCP
O
LCD Line clock pulse
32-35
DDA3 - 0
O
4mA drive
4mA drive
3-state
37
CPS
O
4mA drive
LCD Data clock pulse 2 or Data Strobe
38
CP
O
LCD Data clock pulse
42-45
DDB3 - 0
O
47-50
DDC3 - 0
O
52-55
DDD3 - 0
O
4mA drive
4mA drive
3-state
4mA drive
3-state
4mA drive
3-state
59, 60
PORT0, 1
I/O
LVTTL /
4mA drive
General purpose I/O port (input / output direction
can be set for each pin)
62, 64, 65
66, 67, 70, 71
73, 74, 76-79
81-84, 86, 87
A18 - 16
I
LVTTL
AD15 - 00
I/O
LVTTL /
4mA drive
Host address/data multiplexed bus
92-95, 97-100
D07 - 00
I/O
LVTTL /
4mA drive
Host data bus
2
CSN
I
LVTTL, Schmitt
Chip select (active “L”)
3
REN
I
LVTTL, Schmitt
Read enable (active “L”)
Write enable (active “L”)
LCD Data A
LCD Data B
LCD Data C
LCD Data D
Host address bus
4
WEN
I
LVTTL, Schmitt
5
BSN
I
LVTTL, Schmitt
Bus start/address strobe (active “L”)
7
DSN
I
LVTTL, Schmitt
Data strobe (active “L”)
O
8mA drive
3-state
8
BSYN
Busy/wait (active “L”, 3-stated)
10
BCLK
I
LVTTL, Schmitt
Bus clock
9
REGS
I
LVTTL, Schmitt
Register select
12
XOSCI
I
Clock oscillator input (built-in feedback resistor)
14
XOSCO
O
X’tal oscillation
buffer
16
RESETN
I
LVTTL
System reset (active “L”)
18, 19, 21, 22
HMOD3 - 0
I
LVTTL
Host mode select
23, 24
TEST1, 0
I
LVTTL
Test mode select (normally tied to “L”)
58
11, 20, 61, 68,
85, 96
(TOUT)
O
2mA drive
VDDI
—
Power Supply
Power supply for the internal core and I/O
36, 46
6, 15, 31, 40,
56, 63, 80, 88
VDDO
—
Power Supply
Power supply for the LCD interface signal outputs
VSS
—
Power Supply
Common ground
Clock oscillator output
(Test output. Not used.)
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FUNCTIONAL DESCRIPTION
1. Display Memory
The address and data configuration of the display memory is specified by making control register settings.
When the defined memory size is smaller than the internal DRAM (4M bits), the page mode operation is started
automatically, making it possible to specify the display address in units of a page and to access the host CPU (a
maximum of 256 pages). Even when the address space of the host CPU bus is smaller than the display memory
space, the entire area can be accessed using the page mode.
There are limitations on the LCD drive mode depending on the display memory data width. (See Section 3.1.)
Note that the LCD control timings must be defined before accessing the display memory. (See Section 3.1.2)
• Control registers:
IMASZX [#03h: bit 3-0]:
IMASZY [#03h: bit 7-4]:
IMDBPP [#02h: bit 1-0]:
HSTPGA [#3Bh]:
Display memory horizontal size (2n) (Table F1.1)
Display memory vertical size (2n)
(Table F1.1)
Number of bits per pixel
(Table F1.2)
Page number for host access
Table F1.1 Display memory size selection
Vertical size
(lines)
IMASZX
0000
64
0000
64
0001
128
0001
128
0010
256
0010
256
0011
512
0011
512
0100
1024
0100
1024
0101
2048
0101
2048
IMASZY
Horizontal size
(pixels)
0110
4096
0110
4096
0111
(Reserved)
0111
(Reserved)
1XXX
(Reserved)
1XXX
(Reserved)
Table F1.2 Display memory data width
IMDBPP
Number of bits
(bits / pixel)
00X
—
010
4
011
8
100
16*1
Number of simultaneously displayed colors
Color mode
Monochrome mode
Applicable
LCD type
—
—
—
Pseudo color
Direct color
16/4096
16
256/4096
256
4096
—
STN
65536
—
TFT
STN/TFT
*1: Correspondence between the display memory data and the color data in the 16BPP mode.
7
STN 16 BPP
(12)
(no use)
7
TFT 16 BPP
Upper byte
0
R R R R
3 2 1 0
Upper byte
0
R R R R R G G G
5 4 3 2 1 5 4 3
7
Lower byte
0
G G G G B B B B
3 2 1 0 3 2 1 0
7
Lower byte
0
G G G B B B B B
2 1 0 5 4 3 2 1
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Example 1:
ML87V3104
When IMASZX = “100”, IMASZY = “100”, and IMDBPP = “010”:
The memory size is 1024 horizontal pixels, 1024 vertical lines and 4 bits/pixel.
1024 × 1024 × 4 = 4M bits
The memory can be accessed using 19 host address bits (10 horizontal bits plus 9 vertical bits) with
the host data width being 8 bits (in 2-pixel packed format).
Example 2:
When IMASZX = “010”, IMASZY = “010”, and IMDBPP = “011”:
The memory size is 256 horizontal pixels, 256 vertical lines with 8 bits/pixel and 8 pages.
256 × 256 × 8 = 512K bits (< 4M bits)
4M bits/512 K bits = 8 pages
The memory can be accessed using 16 host address bits (8 horizontal bits plus 8 vertical bits) and the
lower 3 bits of the page register, with the host data width being 8 bits (in 2-pixel packed format).
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2. Display Control
2.1 Display section
The display section of the ML87V3104 is composed of the display memory, the cursor and cursor color registers,
the color palette, the FRC table, and output format conversion section. (Fig. F2.1)
The color display in the case of 4 bits/pixel and 8 bits/pixel can be made using, respectively, 16 and 256 colors out
of 4096 colors. (Pseudo-color mode)
Further, in the STN mode, the output is made after conversion into the gradation expression data in the FRC
method.
In the case of 16 bits/pixel, the output is made directly without passing through the color palette. (Direct color
mode)
In the STN mode, out of the total 16 bits, only 4 bits each of RGB (12 bits in all) will be valid and display 4096
colors can be made.
In the TFT mode, the 16 bits are divided into 5 bits of R, 6 bits of G, and 5 bits of B, making it possible to display
65536 colors.
Even the direct mode can also be used in the case of 8 bits/pixel.
Display memory
4
8/16
1
512 × 8b
Color
palette
8
4
FRC
Table
SEL
Cursor
pattern
register
16 × 16 × 2b
2
4
SEL
Color
register
256 × 12b
Output
1
format
conversion
DDB3-0
16 × 16b
4
1
8
4
SEL
3 × 8b
Cursor
display
control
4
SEL
DDA3-0
4
DDC3-0
DDD3-0
8/16
Fig. 2.1 The display section
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2.2 Display screen composition
The display screen consists of the main screen with a size equal to the display size of the LCD panel, and a
sub-screen displayed in a smaller area within the main screen. (Fig. F2.2.1)
In the case of a color LCD panel, one set of the three colors (RGB) is considered as one pixel. (Fig. F2.2.2)
(1)
Main screen
(6)
Sub-screen
(2)
(4)
(5)
(3)
Fig. F2.2.1 The display screen composition
1 Pixel
1 Pixel
1 Line
1 Line
(a) Monochrome LCD
(b) Color LCD
Fig. F2.2.2 The LCD panel dot composition
• Control registers:
Horizontal display size ≤ 1024 pixels
(1) MSCSZH
[#21h, #20h]:
(2) MSCSZV
[#23h, #22h]: Vertical display size ≤ 1024 lines
(3) SSCSZH
[#25h, #24h]: Sub-screen horizontal display size < (1)
(4) SSCSZV
[#27h, #26h]: Sub-screen vertical display size < (2)
(5) SDPOSH
[#29h, #28h]: Sub-screen horizontal display position < (1)
(6) SDPOSV
[#2Bh, #2Ah]: Sub-screen vertical display position < (2)
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2.3 Display functions
2.3.1 Main screen, sub-screen, and scrolling
The main screen and the sub-screen in the display screen (see Fig. F2.2.1) can respectively display the areas
specified in the display memory. (Fig. F2.3.1)
Display memory
Origin
(2)
(1)
LCD Screen
(4)
Main screen
Sub-screen
(3)
Fig. F2.3.1 The display screen composition
• Control registers:
(1) MDPSTX [#31h, #30h]:
Starting horizontal address of reading out the main screen display area
(2) MDPSTY [#33h, #32h]:
Starting vertical address of reading out the main screen display area
(3) SDPSTX [#35h, #34h]:
Starting horizontal address of reading out the sub-screen display area
(4) SDPSTY [#37h, #36h]:
Starting vertical address of reading out the sub-screen display area
(5) MDPPGA [#38h]:
Page number of the main screen display area
(6) SDPPGA [#39h]:
Page number of the sub-screen display area
The starting addresses of reading out the display memory can be specified for the separate main screen and
sub-screen in units of 16 horizontal pixels and one vertical line. In addition, by successively over-writing by the
host CPU, it is possible to realize scrolling of the display screen.
The sub-screen is always displayed by superimposing on the main screen.
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2.3.2 Screen mode
It is possible to select the method of placing the LCD panel by setting the screen mode.
It is possible to specify the landscape (horizontal screen) or portrait (vertical screen), and to specify the left/right
and top/bottom reversal of the displayed image.
• Control register:
SCRMOD [#02h; bit6-4]:
Screen mode
Table F2.3.2 The screen modes
SCRMOD
Screen mode
000
Normal
001
Left/right flip
Landscape
(longer horizontal side)
010
Top/bottom flip
011
Left/right and
top/bottom flip
100
Normal
101
Top/bottom flip
Portrait
(longer vertical side)
110
Left/right flip
111
Left/right and
top/bottom flip
: LCD data output scanning direction
Note: The screen mode definition has a difference between Landscape and Portrait.
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2.4 Cursor
2.4.1 Cursor display
It is possible to display the cursor on the screen. It is also possible to select whether or not to display the cursor,
and when cursor display is selected, it is always displayed in the front-most screen. This LSI has a pattern register
for the display of a cursor with a size of 16 pixels × 16 lines × 2 bits in which it is possible to write the cursor shape.
Displaying the cursor has no effect on the display memory.
The cursor display color can be specified by the contents of the 2-bit (4-value) cursor pattern register for each pixel.
One of the four values is “transparent”, and that pixel is not displayed when this value is specified. The other 3
values respectively correspond to the 8-bit cursor color registers (CSCOL1 to CSCOL3), and the specified value is
converted to the actually displayed pixel data from the color palette common to the display memory output.
2.4.2 Cursor display position
The cursor display position is specified in terms of the position in the screen of the cursor origin (the top left corner
of the cursor).
LCD screen
(2)
(1)
Cursor
Fig. F2.4.2 The cursor position
• Control registers:
(1) CSPOSH [#2Dh, #2Ch]:
Cursor display horizontal position
(2) CSPOSV [#2Fh, #2Eh]:
Cursor display vertical position
(3) CSDENB [#2Fh; bit7]:
Cursor display enable (‘0’: disable, ‘1’: enable)
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2.4.3 Cursor color register
The display data of the cursor is determined corresponding to the cursor data by the contents of the 8-bit cursor
color register. The number of valid bits depends on the number of bits per pixel (IMDBPP).
8
Display memory data
00
8
Cursor color register 1
Cursor color register 2
8
01
SEL
10
To color palette
8
Cursor color register 3
11
2
Cursor data
Fig. F2.4.3 The cursor color register
• Control registers:
CSCOL1
[#1Dh]:
Cursor color register 1
CSCOL2
[#1Eh]:
Cursor color register 2
CSCOL3 [#1Fh]:
Cursor color register 3
Valid bits:
Bits 3 to 0 for 4BPP
Bits 7 to 0 for 8BPP
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2.4.4 Cursor pattern register
The cursor pattern (shape) can be prepared by writing data in the 16 x 16 x 2-bit cursor pattern register. The data is
accessed in the 4-pixel packed format. (Fig. F2.4.4)
2 bits
X=0 1 2 3 4 5 6 7 8
Y=0
16 pixels
Y=1
Y=2
16
lines
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Cursor
Register
data
X = 4n + 0 X = 4n + 1 X = 4n + 2 X = 4n + 3
bit1 bit0 bit1 bit0 bit1 bit0 bit1 bit0
Fig. F2.4.4 The cursor pattern register
• Control registers:
CSPTAY [#18h; bit5-2]:
Cursor pattern register address Y (4 bits)
CSPTAX [#18h; bit1-0]:
Cursor pattern register address X (higher 2 bits)
CSPTD0 [#19h; bit7-6]:
Cursor pattern register data (X address = 4n+0)
CSPTD1 [#19h; bit5-4]:
Cursor pattern register data (X address = 4n+1)
CSPTD2 [#19h; bit3-2]:
Cursor pattern register data (X address = 4n+2)
CSPTD3 [#19h; bit1-0]:
Cursor pattern register data (X address = 4n+3)
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2.5 Color palette
The data written in the display memory is converted into the actual color data output to the LCD panel by the color
palette. (Pseudo-color mode) The color palette contains 4-bit × 3-color (R, G, B) (= 12 bits) registers
corresponding to each of the 256 entries addresses.
The correspondence between the display memory data and the color palette entry is established as shown in Table
F2.5 depending on the data width of the display memory. The color palette cannot be used in the direct color mode
(16BPP).
Table F2.5 The display memory data vs. the color palette entries
*1
Display memory data
Color palette entry
8 BPP
4 BPP
00
0
00
01
1
01
02
2
02
03
3
03
04
4
04
05
5
05
06
6
06
07
7
07
08
8
08
09
9
09
0A
A
0A
0B
B
0B
0C
C
0C
0D
D
0D
0E
E
0E
0F
F
0F
10
—
10
11
—
11
12
—
12
13
—
13
14
—
14
FC
—
FC
FD
—
FD
FE
—
FE
FF
—
FF
*1: A hyphen “—” indicates that the data value is not used.
• Control registers:
COLPTA [#10h]:
Color palette entry address
COLPDR [#11h; bit7-4]:
Color palette data R
COLPDG [#12h; bit7-4]:
Color palette data G
COLPDB [#13h; bit7-4]:
Color palette data B
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2.6 Gray level control
In the case of an STN type LCD panel, the FRC (Frame Rate Control) method is used for the multiple gray level
display. By controlling the blinking pattern of the dot, it is possible to express intermediate gray levels in a quasi
manner.
Taking 16 frames as one period, it is possible to express up to 16 gray levels.
The dot blinking pattern is set in the 16-word x 16-bit FRC table. The 4-bit table address corresponds to the gray
levels from 0 to 15. The 16-bit table data expresses the dot blinking patterns corresponding to the different gray
levels, and the dot display is switched for each frame sequentially from the MSB to the LSB, with the operation
being repeated at a period of 16 frames.
In the case of a color STN panel, the FRC pattern is the same for all colors.
• Control registers:
FRCTBA [#15h; bit3-0]:
FRC table address
FRCTBD [#17h, #16h]:
FRC table data
Table F2.6 The FRC table (initial value)
Table
address
(gradation) 15
FRC table (displayed in the sequence 15, 14, ..., 1, 0)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
2
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
3
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
4
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
5
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
6
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
7
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
8
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
9
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
10
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
11
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
12
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
13
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
14
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note:
This table shows the initial value set after a reset, and is not one assuming
any specific LCD panel specifications. Set the values in this table to suit
the characteristics of the LCD panel being used.
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3. LCD Interface
3.1 LCD driving method
3.1.1 LCD driving mode
The ML87V3104 is suitable for various types of LCD panels, and allows the LCD driving mode to be selected by
setting the control registers.
The number of valid data bits in the LCD interface varies depending on the driving mode. The output data signals
that are not used will be maintained in the high-impedance state. Further, there are some restrictions on the
selection of the display memory data width (bits per pixel) depending on the driving mode. (Table F3.1)
• Control registers:
LCDMOD [#00h; bit7-4]:
LCD panel operation mode
LCDDAT [#00h; bit3-0]:
LCD panel interface data width
Table F3.1 LCD driving modes
LCDMOD
LCDDAT
000
0000
O
Z
Z
Z
8 bits
O
O
Z
Z
4 bits,
2 phase
O
Z
Z
Z
4 bits
O
Z
Z
Z
8 bits
O
O
Z
Z
100
4 bits,
2 phase
O
Z
Z
Z
000
4 bits
O
Z
Z
Z
8 bits
O
O
Z
Z
4 bits,
2 phase
O
Z
Z
Z
Pseudo-color
12 bits
O
O
O
Z
4, 8
Direct color
16 bits
O
O
O
O
16
010
Pseudo-color
Color STN
000
0100
010
010
Direct color
Monochrome STN
100
1000
Display
memory
BPP
DDA DDB DDC DDD
4 bits
100
0001
Output data
LCD driving mode
000
4, 8
16(12)
4
Color TFT
1001
001
BPP: bits per pixel
‘O’: 4 bits are active.
‘Z’: 4 bits are in a high impedance state.
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3.1.2 LCD control timing
The LCD control timing is determined by the LCP (line clock pulse) signal and the FRP (frame pulse) signal. It is
also possible to set the polarities of these pulses individually.
(1)
LCP
FRP
(2)
(3)
Active display area
(5)
(6)
(7)
Fig. F3.1.2 LCD drive timing
• Control registers:
(1) LCPCYC [#05h, #04h]:
(LCP signal period – 1)
In units of a CP clock in the STN color 4-bit mode
In units of 2 CP clocks in the STN color 8-bit mode or 4-bit 2-phase mode
In units of 4 CP clocks in the STN monochrome 4-bit mode
In units of 8 CP clocks in the STN monochrome 8-bit mode or 4-bit 2-phase mode
In units of a CP clock in the TFT color mode
(2) LCPSTA [#07h, #06h]:
LCP start timing, in units of a CP clock
(3) LCPWID [#07h; bit7-4]: (LCP pulse width – 1), in units of 4 × CP clocks
(4) LCPPOL [#05h; bit7]:
LCP pulse polarity, ‘0’: Positive, ‘1’: Negative
(5) FRPCYC [#09h, #08h]:
FRP signal period, in units of a line, (5) ≥ (6)+2
(6) FRPSTA [#0Bh, #0Ah]: FRP start timing, in units of a line
(7) FRPWID [#0Bh; bit7-4]: (FRP pulse width – 1), in units of a line
(8) FRPPOL [#09h; bit7]:
FRP pulse polarity, ‘0’: Positive, ‘1’: Negative
Note: The internal memory gets started by setting above registers. These must be set at first after the power
up or the internal memory cannot be accessed.
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3.1.3 LCD AC driving signal DF
The toggle period of the DF signal (AC driving signal) can be specified to be either one frame period or the period
of the set number of lines.
• Control registers:
DFFALT
[#0Dh; bit7]:
DF signal toggle mode
DFLALT
[#0Dh, #0Ch]:
(DF signal toggle period – 1), in units of a line
DFFALT
DF toggle mode
0
Reversal at one frame periods
1
Reversal at periods of (DFLALT+1) line
3.1.4 LCD data clocks CP, CPS
It is possible to select whether or not to output the CP and CPS clock pulses during the invalid period (blanking
period) of the LCD display data. In most cases, the appropriate setting is CPBLK = ‘1’ for an STN LCD and
CPBLK = ‘0’ for a TFT LCD.
• Control register:
CPBLK
[#01h; bit7]:
Control of CP and CPS clock output during blanking
CPBLK
CP and CPS clock output during blanking
0
Active
1
Clock pulses are stopped
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3.1.5 LCD data output control
Three types of control registers are provided in this LSI device for control of the LCD data output.
The register COLORD can be used for changing R, G, B sequence in a color LCD. This is also valid in the frame
sequential color mode.
The register DPDMOD is used for inverting the bits of the output data or for making the data all-zero or all-one.
The register DPMENB can be used for stopping the display memory readout operation itself. At this time, even
the LCD driving signals will be stopped. Further, it is also possible to specify the level of the DISP signal output.
The register REFENB controls the refresh operation of the display memory (embedded DRAM). If the refresh
operation is stopped, the entire contents of the display memory will be lost. Along with the register DPMENB, this
register is useful for achieving low power consumption when no display is being made.
• Control registers:
COLORD
DPDMOD
[#01h; bit7]:
Color arrangement sequence of the color LCD panel
COLORD
Color arrangement sequence
000
R, G, B, R, G, B, • • •
001
G, B, R, G, B, R, • • •
010
B, R, G, B, R, G, • • •
101
R, B, G, R, B, G, • • •
110
G, R, B, G, R, B, • • •
111
B, G, R, B, G, R, • • •
[#01h; bit3-2]: LCD data display mode
DPDMOD
DPMENB
REFENB
LCD data display mode
00
Normal
01
Reverse
10
All ‘0’
11
All ‘1’
[#01h; bit1-0]:
Display memory readout control, definition of DISP signal output
DPMENB
Display memory readout
DISP signal
00
Memory readout stopped
DISP = ‘L’
01
LCD drive stopped
DISP = ‘H’
10
Memory readout operating
DISP = ‘L’
11
LCD drive operating
DISP = ‘H’
[#02h, bit7, 3]: Embedded DRAM refresh operation enable
REFENB
DRAM refresh operation
1
0
0
X
Fully stopped (sleep mode)*1
0
Operation only during blanking
1
Always operating
1
*1: The contents of the display memory will be lost in the sleep mode.
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3.1.6 Calculation of the display frame rate
The frame rate (the frame frequency) is determined by the periods of the LCD panel driving signals LCP and FRP,
the clock frequency, and the LCD driving mode.
Frame rate = FXOSC/{(FRPCYC) × (LCPCYC) × (TPX)}
Where,
FXOSC
: External input clock frequency,
FRPCYC : Period (in units of a line) of the FRP (frame pulse) signal,
LCPCYC : Period (in units of a pixel) of the LCP (line pulse) signal,
TPX : TPX = 3/4 in the case of a color STN type LCD and TPX = 1 in all other cases.
Example:
What is the input clock frequency for making the frame rate equal to 150 Hz in the case of a color
STN QVGA (320 × 240) type LCD panel?
FRPCYC = 240 + 2 = 242
LCPCYC = 320 + 40 = 360
FXOSC = 150 × 242 × 360 × 3/4 = 9.8 MHz
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3.2 LCD data output format
The valid output data signal and the data format are determined depending on the LCD driving mode.
3.2.1 Color STN, 4-bit mode
LCD data output sequence
DDA3
R0
G1
B2
R4
DDA2
G0
B1
R3
G4
DDA1
B0
R2
G3
B4
DDA0
R1
G2
B3
R5
LCD panel segment arrangement
R GB R GB R GB R GB
0 0 0 1 1 1 2 2 2 3 3 3
Fig. F3.2.1 Color STN, 4-bit mode
3.2.2 Color STN, 8-bit mode
LCD data output sequence
DDA3
R0
B2
DDA2
G0
R3
DDA1
B0
G3
DDA0
R1
B3
DDB3
G1
R4
DDB2
B1
G4
DDB1
R2
B4
DDB0
G2
R5
LCD panel segment arrangement
R GB R GB R GB R GB
0 0 0 1 1 1 2 2 2 3 3 3
Fig. F3.2.2 Color STN, 8-bit mode
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3.2.3 Color STN, 4-bit 2-phase mode
LCD data output sequence
DDA3
R0
G0
B2
R3
DDA2
B0
R1
G3
B3
DDA1
G1
B1
R4
G4
DDA0
R2
G2
B4
R5
LCD panel segment arrangement
R GB R GB R GB R GB
0 0 0 1 1 1 2 2 2 3 3 3
Fig. F3.2.3 Color STN, 4-bit, 2-phase mode
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3.2.4 Monochrome STN, 4-bit mode
LCD data output sequence
DDA3
0
4
8
12
DDA2
1
5
9
13
DDA1
2
6
10
14
DDA0
3
7
11
15
LCD panel segment arrangement
0
1
2
3
4
5
6
7
8
9
Fig. F3.2.4 Monochrome STN, 4-bit mode
3.2.5 Monochrome STN, 8-bit mode
LCD data output sequence
DDA3
0
8
DDA2
1
9
DDA1
2
10
DDA0
3
11
DDB3
4
12
DDB2
5
13
DDB1
6
14
DDB0
7
15
LCD panel segment arrangement
0
1
2
3
4
5
6
7
8
9
Fig. F3.2.5 Monochrome STN, 8-bit mode
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3.2.6 Monochrome STN, 4-bit 2-phase mode
LCD data output sequence
DDA3
0
1
8
9
DDA2
2
3
10
11
DDA1
4
5
12
13
DDA0
6
7
14
15
LCD panel segment arrangement
0
1
2
3
4
5
6
7
8
9
Fig. F3.2.6 Monochrome STN, 4-bit, 2-phase mode
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3.2.7 Color TFT, 12-bit mode
LCD data output sequence
DDA 3-0 (R)
R0
R1
R2
R3
DDB3-0 (G)
G0
G1
G2
G3
DDC3-0 (B)
B0
B1
B2
B3
LCD panel segment arrangement
R G B R G B R G B R G B
0 0 0 1 1 1 2 2 2 3 3 3
Fig. F3.2.7 Color TFT, 12-bit mode
3.2.8 Color TFT, 16-bit mode
LCD data output sequence
LCD panel segment arrangement
DDA 3-0 (R)
DDB3
R0
R1
R2
R3
DDB2-0 (G)
DDC3-1
G0
G1
G2
G3
(B) B0
B1
B2
B3
DDC0
DDD3-0
R G B R G B R G B R G B
0 0 0 1 1 1 2 2 2 3 3 3
Fig. F3.2.8 Color TFT, 16-bit mode
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ML87V3104
4. General Purpose I/O Port
The ML87V3104 has two general purpose ports (PORT1, PORT0). It is possible to specify the input/output
directions independently for these ports. The output level of the output port can be set by writing data in the data
register. Further, the input level of the input port can be read out from the data register. When set as an input port,
writing to the data register will not be valid.
• Control registers:
PTDDIR
[#0Eh; bit1-0]:
PTDREG [#0Fh; bit1-0]:
General purpose port input/output mode (‘0’: output, ‘1’: input)
General purpose port data register (‘0’: L level, ‘1’: H level)
Bit 1 corresponds to PORT1 and bit 0 corresponds to PORT0.
PTDDIR[n]
PORTn
0
Output
PTDREG[n] → PORTn
1
Input
PTDREG[n] ← PORTn
PTDDIR[0]
PTDREG[0]
Pin 59
PORT0
Host Data
PTDDIR[1]
PTDREG[1]
Pin 60
PORT1
Host Data
Fig. F4.1 General purpose ports
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5. Host Interface
5.1 Host interface bus mode selection
The host interface bus can be selected to suit the external bus modes of different types of CPUs by setting the pins
HMOD3 to HMOD0.
Table F5.1 Host interface bus mode
HMOD
[3:0]
0000
0001
0010
Bus type
Address/
data bus
CSN, WEN, REN,
A0
Busy
AS, WEN, REN,
A1
A2
Bus control
Busy
BSN, WEN, REN,
Separate
ACK
A[18:00]
0011
—
0100
A4
0101
A5
011X
—
D[07:00]
Applicable CPUs*1
Hitachi SH-1,2, H8S,
Fujitsu F2MC-16F, FR30
Toshiba TLCS-900/H2
Hitachi SH-4
Hitachi SH-3,
Motorola MCF5204
Toshiba TX39
(Reserved)
BSN, RWN, DSN,
ACK
BSN, RWN, DSN,
Busy
—
Toshiba TX19,
Motorola MCF5206,
MPC801/850, M68K
Mitsubishi M32R, NEC V830,
Intel SA-110
(Reserved)
—
Hitachi SH-1,2,
1000
ASN, WEN, REN,
B0
Busy
Multiplexed
1001
B1
101X
—
11XX
—
NEC V850, 78K/IV
Mitsubishi M16C
Oki MSM66K, 80C51
A[18:16]
AS, WEN, REN,
Fujitsu F2MC-16L,
AD[15:00]
Busy
Toshiba TLCS-900
(Reserved)
—
*1: The types of CPUs listed here are only for reference. Please examine well about the specifications
of the host interface signals and the timings of the MCU being used, and then select the host mode.
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5.1.1 Bus control signals
The assignment of the bus control signals to the input/output pins is determined by the host interface bus mode.
Table F5.5.1 Bus control signals
Bus type
Pin name
A0
A1
A2
A4
A5
B0
B1
A18-16
A18-16
A18-16
A18-16
A18-16
A18-16
A18-16
A18-16
AD15-00
A15-00
A15-00
A15-00
A15-00
A15-00
AD15-00
AD15-00
D07-00
D07-00
D07-00
D07-00
D07-00
D07-00
—
—
REGS
REGS
REGS
REGS
REGS
REGS
REGS
REGS
CSN
CSN
CSN
CSN
CSN
CSN
CSN
CSN
REN
REN
REN
REN
RWN
RWN
REN
REN
WEN
WEN
WEN
WEN
—
—
WELN
WELN
BSN
—
BS
BSN
BSN
BSN
ASN
AS
DSN
—
—
—
—
—
WEHN
WEHN
BSYN
BSYN
BSYN
ACK
ACK
BSYN
BSYN
BSYN
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
REGS:
Memory/register address space selection; ‘L’: memory, ‘H’: register
CSN:
Chip select (Active ‘L’)
REN:
Read enable (Active ‘L’)
WEN:
Write enable (Active ‘L’)
WEHN:
Higher byte write enable (Active ‘L’)
WELN:
Lower byte write enable (Active ‘L’)
RWN:
Read/write selection; ‘L’: write, ‘H’: read
BSN:
Bus start (Active ‘L’)
ASN:
Address strobe (Active ‘L’)
DSN:
Data strobe (Active ‘L’)
BSYN:
Bus busy or wait (Active ‘L’)
ACK:
Data acknowledge (Active ‘L’)
BCLK:
Bus clock
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5.1.2 Bus interface timings
[Type A0 Write]
BCLK
CSN
REGS
A18-00
REG
MEM
WEN
(z)
D7-0
(write)
BSYN
[Type A0 Read]
BCLK
CSN
REGS
A18-00
REG
MEM
REN
D7-0
(z)
(read)
BSYN
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ML87V3104
[Type A1 Write]
BCLK
CSN
BS
REGS
A18-00
REG
MEM
REG
MEM
WEN
D7-0
(z)
(write)
BSYN
[Type A1 Read]
BCLK
CSN
BS
REGS
A18-00
REN
D7-0
(z)
(read)
BSYN
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ML87V3104
[Type A2 Write]
BCLK
CSN
BSN
REGS
A18-00
REG
MEM
REG
MEM
WEN
D7-0
(z)
(write)
ACK
[Type A2 Read]
BCLK
CSN
BSN
REGS
A18-00
REN
D7-0
(z)
(read)
ACK
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ML87V3104
[Type A4 Write]
BCLK
CSN
BSN
REGS
A18-00
REG
MEM
REG
MEM
RWN
D7-0
(z)
(write)
ACK
[Type A4 Read]
BCLK
CSN
BSN
REGS
A18-00
RWN
D7-0
(z)
(read)
ACK
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ML87V3104
[Type A5 Write]
BCLK
CSN
BSN
REGS
A18-00
REG
MEM
REG
MEM
RWN
D7-0
(z)
(write)
BSYN
[Type A5 Read]
BCLK
CSN
BSN
REGS
A18-00
RWN
D7-0
(z)
(read)
BSYN
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ML87V3104
[Type B0 Write]
BCLK
CSN
ASN
REGS
A18-16
WEHN
WELN
AD15-0
(z)
A
D (write)
A
D (write)
BSYN
[Type B0 Read]
BCLK
CSN
ASN
REGS
A18-16
REN
AD15-0
(z)
A
D (read)
A
D (read)
BSYN
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ML87V3104
[Type B1 Write]
BCLK
CSN
AS
REGS
A18-16
MEM
WEHN
WELN
AD15-0
(z)
A
D (write)
A
D (write)
BSYN
[Type B1 Read]
BCLK
CSN
AS
REGS
A18-16
MEM
REN
AD15-0
(z)
A
D (read)
A
D (read)
BSYN
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ML87V3104
5.2 Address mapping
The ML87V3104 supports a 19-bit byte address for access from the host CPU. The 4M bit display memory and
the 32-byte control registers are mapped to this address.
When accessing the display memory, the bit assignment of the address is determined by the setting of the memory
size. (Fig. F5.2) See the next section for details of the control registers.
Host address
Page No.
7
0
18
7
0
18
Host data
Y
0
4 bits/pixel
Effective page No.
(w bits)
7
0
Effective page No.
(w bits)
7
0
Effective page No.
(w bits)
0
0
7
0
X
1
px0 px1
3
03
0
X address
((u-1) bits)
Y
0
X
0
7
0
7
X=2n+0 X=2n+1
2-pixel packed format
0
Y address
(v bits)
18
Y
0
16 bits/pixel
7
Y address
(v bits)
18
8 bits/pixel
0
0
7
px
0
X address
(u bits)
XB
0
0
G
2 05
B
1
B=’0’
R
G B=’1’
Y address X address Byte
15 3
(u bits) address 5
(v bits)
The number of total address bits = ( w bits ) + ( v bits ) + ( u bits ) = 19 bits (512K Byte)
Fig. F5.2 Display memory address mapping
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5.3 Control registers
5.3.1 Outline of control registers
The initial setting and the operation of the ML87V3104 are controlled by writing data from the host CPU in the
control registers.
There are 64 single-byte control registers, and in addition, a register space is provided by indirect addressing for
the color palette table (256 × 3 bytes), the FRC table (16 × 2 bytes), and the cursor pattern register (64 bytes). (See
Table F5.1)
The control registers can be accessed by the host CPU by taking the REGS signal input to the ‘H’ level.
18
Host address
15
11
7
5
0
x x x x x x x x x x x x x
Control register
address (6 bits)
Fig. F5.3 The control register address
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Table F5.1 List of control registers (part 1/2)
Register
address
Register name*1
bit 7
00
01
02
bit 6
bit 5
LCDMOD
CP
REF
ENB1
SCRMOD
bit 1
LCDDAT
DPDMOD
REF
ENB0
Function
bit 0
DPMENB
IMDBPP
IMASZX
LCD driving mode
Display operation mode
Memory operation mode
Display memory size
LCPCYC[7:0]
LCP
(Reserved)
POL
06
LCPCYC[10:8]
LCPSTA[7:0]
07
LCPWID
08
LCPSTA[10:8]
(Res)
LCP (line) period and polarity
LCP start position, pulse width
FRPCYC[7:0]
FRP (frame) period and polarity
FRP
(Reserved)
POL
0A
FRPCYC[10:8]
FRPSTA[7:0]
0B
FRPWID
FRPSTA[10:8]
(Res)
0C
0D
bit 2
IMASZY
04
09
bit 3
(Res)
COLORD
BLK
03
05
bit 4
DFLALT[7:0]
DFF
(Reserved)
ALT
DFLALT[10:8]
FRP start position, pulse width
DF (AC driving signal) toggle period
(1 frame or n lines)
0E
(Reserved)
PTDDIR
General purpose port I/O mode
0F
(Reserved)
PTDREG
General purpose port data register
10
COLPTA[7:0]
Color palette table address
11
COLPDR[3:0]
(Reserved)
12
COLPDG[3:0]
(Reserved)
Color palette table data G
13
COLPDB[3:0]
(Reserved)
Color palette table data B
14
15
(Reserved)
(Reserved)
(Reserved)
FRCTBA[3:0]
16
FRCTBD[7:0]
17
FRCTBD[15:8]
18
(Res)
19
CSPTD0
CSPTAY[3:0]
CSPTD1
Color palette table data R
CSPTD2
FRC table address
FRC table data
CSPTAX[3:2] Cursor pattern register address
CSPTD3
Cursor pattern register data
1A
(Reserved)
(Reserved)
1B
(Reserved)
(Reserved)
1C
(Reserved)
(Reserved)
1D
CSCOL1[7:0]
Cursor color register 1
1E
CSCOL2[7:0]
Cursor color register 2
1F
CSCOL3[7:0]
Cursor color register 3
*1: The entries “(Reserved)” or “(Res)” indicate reserved bits. Writing data to these bits is not valid and
the data read out from these bits will be indeterminate.
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Table F5.1 List of control registers (part 2/2)
Register
address
Register name*1
bit 7
bit 6
bit 5
20
(Reserved)
26
(Reserved)
28
[9:8]
SDPOSH[7:0]
29
(Reserved)
2A
[9:8]
SDPOSV[7:0]
SSD
ENB
(Reserved)
2C
[9:8]
CSPOSH[7:0]
2D
(Reserved)
2E
[9:8]
CSPOSV[7:0]
CSD
ENB
(Reserved)
30
[9:8]
MDPSTX[7:0]
(Reserved)
32
MDPSTX[11:8]
MDPSTY[7:0]
(Reserved)
34
MDPSTY[11:8]
SDPSTX[7:0]
(Reserved)
36
37
[9:8]
SSCSZV[7:0]
27
35
[9:8]
SSCSZH[7:0]
25
SDPSTX[11:8]
SDPSTY[7:0]
(Reserved)
SDPSTY[11:8]
Function
bit 0
[9:8]
(Reserved)
24
33
bit 1
MSCSZV[7:0]
23
31
bit 2
(Reserved)
22
2F
bit 3
MSCSZH[7:0]
21
2B
bit 4
Main screen horizontal size
Main screen vertical size
Sub-screen horizontal size
Sub-screen vertical size
Sub-screen display horizontal position
Sub-screen display vertical position
Sub-screen display enable
Cursor display horizontal position
Cursor display vertical position
Cursor display enable
Display memory horizontal position for
main screen
Display memory vertical position for
main screen
Display memory horizontal position for
sub-screen
Display memory vertical position for
sub-screen
38
MDPPGA[7:0]
Display memory page number for main
screen
39
SDPPGA[7:0]
Display memory page number for
sub-screen
3A
(Reserved)
3B
HSTPGA[7:0]
3C
(Reserved)
3D
(Reserved)
3E
(Reserved)
3F
(Reserved)
(Reserved)
Display memory page number for host
access
(For testing, cannot be written into)
*1: The entries “(Reserved)” or “(Res)” indicate reserved bits. Writing data to these bits is not valid and the data
read out from these bits will be indeterminate.
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5.3.2 Register details
In the following descriptions of the different registers, the underlined part indicates the initial value after a reset.
[#00h] LCD driving mode
Data bit
bit 7
bit 6
bit 5
bit 4
LCDMOD
Register
3
2
W/R
1
0
2
1
0
W/R
LCD panel interface data width selection
LCDDAT
LCD Driving mode
010
4-bit mode
Color STN
100
XXX
010
(Reserved)
XXX
1000
000
—
4-bit mode
Monochrome STN
100
0110
8-bit mode
4-bit 2-phase mode
000
0100
bit 0
LCDDAT
—
000
0010
bit 1
LCD panel operation mode selection
LCDMOD
0000
bit 2
(Reserved)
W/R
• LCDMOD[3:0]:
• LCDDAT[2:0]:
bit 3
8-bit mode
4-bit 2-phase mode
(Reserved)
—
12-bit mode (pseudo-color)
Color TFT
1001
001
11XX
XXX
16-bit mode (direct color)
(Reserved)
—
‘X’: Don’t care
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[#01h] Display operation mode
Data bit
bit 7
Register
CP
BLK
W/R
W/R
• CPBLK:
bit 6
bit 5
bit 4
bit 3
COLORD
2
1
bit 2
bit 1
DPDMOD
0
1
W/R
bit 0
DPMENB
0
W/R
1
0
W/R
Control of CP clock output during blanking
CPBLK
• COLORD[2:0]:
CP Output during blanking
0
Active
1
Fixed at CP = ‘L’, CPS = ‘H’
Color arrangement sequence of color LCD panel
COLORD[2:0]
Color arrangement sequence
000
R, G, B, R, G, B, • • •
001
G, B, R, G, B, R, • • •
010
B, R, G, B, R, G, • • •
011
(Reserved)
100
(Reserved)
101
R, B, G, R, B, G, • • •
110
G, R, B, G, R, B, • • •
111
B, G, R, B, G, R, • • •
• DPDMOD[1:0]:
LCD data display mode
DPDMOD[1:0]
LCD data display mode
00
Normal
01
Inverted
10
All ‘0’
11
All ‘1’
• DPMENB[1:0]:
Display memory readout control, DISP signal output specification
DPMENB[1:0]
Display memory readout
DISP signal
00
Memory readout stopped
DISP = ‘L’
01
LCD drive stopped
DISP = ‘H’
10
Memory readout operating
DISP = ‘L’
11
LCD drive operating
DISP = ‘H’
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[#02h] Memory operation mode
Data bit
bit 7
bit 6
Register
REF
ENB1
2
W/R
W/R
• REFENB[1:0]:
bit 5
bit 4
bit 3
bit 2
0
REF
ENB0
2
SCRMOD
1
W/R
bit 1
bit 0
IMDBPP
1
W/R
0
W/R
Embedded DRAM refreshing operation enable
REFENB
DRAM refreshing
1
0
0
×
(Reserved)
0
Operation only during blanking
1
Always operating
1
• SCRMOD[2:0]: Screen mode
SCRMOD[2:0]
Screen mode
000
Normal
001
Left/right flip
010
Landscape
011
Left/right and top/bottom flips
100
Normal
101
110
Left/right flip
Portrait
Top/bottom flip
111
• IMDBPP[1:0]:
Top/bottom flip
Left/right and top/bottom flips
Display memory data mode (number of bits per pixel)
Number of displayable
colors
IMDBPP[2:0]
Bits/pixel
00X
(Reserved)
010
4
16 colors
011
8
256 colors
100
16
65,536 colors
Reserved
—
—
101
110
111
Note: The pseudo-color mode using the color palette for 4 or 8 bits/pixel, and
direct color mode for 16 bits/pixel.
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[#03h] Display memory size
Data bit
Register
bit 7
bit 6
3
2
bit 4
bit 3
bit 2
0
3
2
IMASZY
W/R
• IMASZY[3:0]:
• IMASZX[3:0]:
bit 5
bit 1
bit 0
IMASZX
1
W/R
1
0
W/R
Display memory vertical size (2n)
Display memory horizontal size (2n)
IMASZY
Vertical size
(lines)
IMASZX
Horizontal size
(pixels)
0000
64
0000
64
0001
128
0001
128
0010
256
0010
256
0011
512
0011
512
0100
1024
0100
1024
0101
2048
0101
2048
0110
4096
0110
4096
0111
(Reserved)
0111
(Reserved)
1XXX
(Reserved)
1XXX
(Reserved)
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[#04h] LCP (line clock) period (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
LCPCYC
Register
W/R
W/R
[#05h] LCP (line clock) period (MSB) and pulse polarity
Data bit
bit 7
Register
LCP
POL
(Reserved)
W/R
W/R
—
• LCPCYC[10:0]:
bit 6
bit 5
bit 4
LCPCYC
10
9
8
W/R
(LCP signal period - 1)
In units of a CP clock in the STN color 4-bit mode
In units of 2 CP clocks in the STN color 8-bit mode or 4-bit 2-phase mode
In units of 4 CP clocks in the STN monochrome 4-bit mode
In units of 8 CP clocks in the STN monochrome 8-bit mode or 4-bit 2-phase mode
In units of a CP clock in the TFT color mode
• LCPPOL:
LCP Pulse output polarity
LCPPOL
LCP Output polarity
0
Positive pulse
1
Negative pulse
[#06h] LCP (line clock) start position (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
LCPSTA
Register
W/R
W/R
[#07h] LCP (line clock) start position (MSB) and pulse width
Data bit
bit 7
bit 6
3
2
Register
W/R
• LCPSTA[10:0]:
• LCPWID[3:0]:
bit 5
bit 4
LCPWID
1
0
W/R
(Reserved)
—
LCPSTA
10
9
8
W/R
LCP start timing, in units of a CP clock
(LCP pulse width/4 - 1), in units of a CP clock
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[#08h] FRP (frame pulse) period (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
FRPCYC
Register
W/R
W/R
[#09h] FRP (frame pulse) period (MSB) and pulse polarity
Data bit
bit 7
Register
FRP
POL
(Reserved)
W/R
W/R
—
• FRPCYC[10:0]:
• FRPPOL:
bit 6
bit 5
bit 4
FRPCYC
10
9
8
W/R
FRP signal period, in units of a line
FRP pulse output polarity
LCPPOL
FRP pulse output polarity
0
Positive pulse
1
Negative pulse
[#0Ah] FRP (frame pulse) start position (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
FRPSTA
Register
7
6
5
4
W/R
W/R
[#0Bh] FRP (frame pulse) start position (MSB) and pulse width
Data bit
bit 7
bit 6
3
2
Register
W/R
• FRPSTA[10:0]:
• FRPWID[3:0]:
bit 5
bit 4
FRPWID
1
W/R
0
(Reserved)
—
FRPSTA
10
9
8
W/R
FRP start position
(FRP pulse width – 1)
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[#0Ch] DF (AC driving signal) toggle period (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
2
1
0
bit 2
bit 1
bit 0
DFLALT
Register
W/R
3
W/R
[#0Dh] DF (AC driving signal) toggle period (MSB) and toggle mode
Data bit
bit 7
Register
FRP
POL
(Reserved)
W/R
W/R
—
• DFLALT[10:0]:
• DFFALT:
bit 6
bit 5
bit 4
bit 3
DFLALT
10
9
8
W/R
(DF signal toggle period – 1), in units of a line Valid when DFFALT = ‘1’.
DF signal toggle mode
DFFALT
DF toggle mode
0
Reversal at one frame periods
1
Reversal at periods of (DFLALT+1) lines
[#0Eh] General purpose port I/O mode
Data bit
bit 7
bit 6
bit 5
bit 4
Register
(Reserved)
W/R
—
bit 3
bit 2
bit 1
bit 0
PTDDIR
1
0
W/R
[#0Fh] General purpose port data register
Data bit
bit 7
bit 6
bit 5
bit 4
Register
(Reserved)
W/R
—
• PTDDIR[1:0]:
• PTDREG[1:0]:
bit 3
bit 2
bit 1
bit 0
PTDREG
1
0
W/R
General purpose port (PORT1, PORT0) I/O direction setting
General purpose port (PORT1, PORT0) data register
PTDDIR[n]
PORTn
0
Output
PTDREGn → PORTn
1
Input
PTDREGn ← PORTn
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[#10h] Color palette table address
Data bit
Register
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
2
1
0
bit 1
bit 0
COLPTA
W/R
3
W/R
• COLPTA[7:0]:
Color palette table address
Table address when writing table data
The table address is equivalent to the color palette entry number
Incremented automatically every time the table data B is written.
[#11h] Color palette table data R
Data bit
Register
bit 7
bit 6
3
2
bit 5
bit 4
bit 3
COLPDR
1
W/R
bit 2
(Reserved)
0
W only
—
[#12h] Color palette table data G
Data bit
Register
bit 7
bit 6
3
2
bit 5
bit 4
bit 3
COLPDG
1
W/R
bit 2
bit 1
bit 0
(Reserved)
0
W only
—
[#13h] Color palette table data B, table address incrementing
Data bit
Register
W/R
• COLPDR[3:0]:
• COLPDG[3:0]:
• COLPDB[3:0]:
bit 7
bit 6
3
2
bit 5
bit 4
COLPDB
1
0
W only
bit 3
bit 2
bit 1
bit 0
(Reserved)
—
Color palette table data R (red)
Color palette table data G (green)
Color palette table data B (blue)
Contents of the entry specified by the color palette table address.
The table address is incremented automatically when data is written in COLPDB.
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[#15h] FRC table address
Data bit
bit 7
bit 6
bit 5
Register
(Reserved)
W/R
—
• COLPTA[7:0]:
bit 4
bit 3
bit 2
3
2
bit 1
bit 0
FRCTBA
1
0
W only
FRC table address
The address of the table containing the setting of the FRC dot blinking pattern.
Incremented automatically when the table data (MSB) is written.
[#16h] FRC table data (LSB)
Data bit
Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
10
9
8
FRCTBD
7
6
5
4
W/R
W only
[#17h] FRC table data (MSB)
Data bit
Register
bit 7
bit 6
bit 4
FRCTBD
15
14
W/R
• FRCTBD[3:0]:
bit 5
13
12
11
W only
FRC table data
The data of the table containing the setting of the FRC dot blinking pattern.
The table address denotes the gray level for each color of the color palette output, and the
table data specifies the dot blinking pattern for that gradation value.
(Blinking in sequence from FRCTBD[15] to FRCTBD[0].)
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[#18h] Cursor pattern register address
Data bit
bit 7
bit 6
Register
(Reserved)
W/R
—
• CSPTAY[3:0]:
• CSPTAX[3:2]:
bit 5
bit 4
3
2
bit 3
bit 2
bit 1
0
3
CSPTAY
bit 0
CSPTAX
1
2
W only
Cursor pattern register Y address
Cursor pattern register X address
The address of the register for setting the dot pattern of the cursor.
The X address is incremented automatically when the register data is written, and the Y
address is incremented when there is an overflow in the X address.
[#19h] Cursor pattern register data
Data bit
Register
bit 7
bit 6
bit 5
CSPTD0
1
bit 3
CSPTD1
0
1
W/R
• CSPTDO-3[1:0]:
bit 4
bit 2
bit 1
CSPTD2
0
1
bit 0
CSPTD3
0
1
0
W only
Cursol pattern register data
The data of the register for setting the dot pattern of the cursor.
This is the 2 bits/pixel data in the 4-pixel packed format.
CSPTDn
Cursor display data
00
Transparent (display memory contents)
01
Color register 1 (CSCOL1)
10
Color register 2 (CSCOL2)
11
Color register 3 (CSCOL3)
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[#1Dh] Cursor color register 1
Data bit
Register
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
2
1
0
CSCOL1
W/R
W/R
[#1Eh] Cursor color register 2
Data bit
Register
bit 7
bit 6
bit 5
bit 4
7
6
5
4
CSCOL2
W/R
W/R
[#1Fh] Cursor color register 3
Data bit
Register
bit 7
bit 6
bit 5
bit 4
7
6
5
4
CSCOL3
W/R
• CSCOL0-3[1:0]:
3
W/R
Cursor color register 0 to 3
Color data of the cursor. Corresponds to the entry of the color palette.
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[#20h] Main screen horizontal size (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
MSCSZH
Register
W/R
W/R
[#21h] Main screen horizontal size (MSB)
Data bit
bit 7
bit 6
bit 5
bit 4
Register
(Reserved)
W/R
—
• MSCSZH[9:0]:
MSCSZH
9
8
W/R
(Main screen horizontal size – 1), in units of 16 pixels.
[#22h] Main screen vertical size (LSB)
Data bit
Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
MSCSZV
7
6
5
4
W/R
W/R
[#23h] Main screen vertical size (MSB)
Data bit
bit 7
bit 6
bit 5
bit 4
Register
(Reserved)
W/R
—
• MSCSZV[9:0]:
bit 0
MSCSZV
9
8
W/R
(Main screen vertical size – 1), in units of the number of lines.
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[#24h] Sub-screen horizontal size (LSB)
Data bit
Register
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
SSCSZH
W/R
W/R
[#25h] Sub-screen horizontal size (MSB)
Data bit
bit 7
bit 6
bit 5
bit 4
Register
(Reserved)
W/R
—
• SSCSZH[9:0]:
SSCSZH
9
8
W/R
(Sub-screen horizontal size – 1), in units of a pixel.
[#26h] Sub-screen vertical size (LSB)
Data bit
Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
SSCSZV
7
6
5
4
W/R
W/R
[#27h] Sub-screen vertical size (MSB)
Data bit
bit 7
bit 6
bit 5
bit 4
Register
(Reserved)
W/R
—
• SSCSZV[9:0]:
bit 0
SSCSZV
9
8
W/R
(Sub-screen vertical size – 1), in units of the number of lines.
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[#28h] Sub-screen display horizontal position (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
SDPOSH
Register
W/R
W/R
[#29h] Sub-screen display horizontal position (MSB)
Data bit
bit 7
bit 6
bit 5
bit 4
Register
(Reserved)
W/R
—
• SDPOSH[9:0]:
SDPOSH
9
8
W/R
Sub-screen display horizontal position in units of 16 pixels.
The position of displaying the origin of the sub-screen is specified in terms of the display
address within the main screen.
[#2Ah] Sub-screen display vertical position (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
SDPOSV
Register
W/R
W/R
[#2Bh] Sub-screen display vertical position (MSB)
Data bit
bit 7
Register
SSD
ENB
(Reserved)
W/R
W/R
—
• SDPOSV[9:0]:
bit 6
bit 5
bit 4
SDPOSV
9
8
W/R
Sub-screen display vertical position in units of a line.
The position of displaying the origin of the sub-screen is specified in terms of the display
address within the main screen.
• SSDENB:
Sub-screen display enable
SSDENB
Sub-screen
0
Not displayed
1
Displayed
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[#2Ch] Cursor display horizontal position (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
CSPOSH
Register
W/R
W/R
[#2Dh] Cursor display horizontal position (MSB)
Data bit
bit 7
bit 6
bit 5
bit 4
Register
(Reserved)
W/R
—
• CSPOSH[9:0]:
CSPOSH
9
8
W/R
Cursor display horizontal position in units of the number of pixels.
The position of displaying the origin of the cursor is specified in terms of the display
address within the main screen.
[#2Eh] Cursor display vertical position (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
2
1
0
bit 2
bit 1
bit 0
CSPOSV
Register
W/R
3
W/R
[#2Fh] Cursor display vertical position (MSB), Cursor display enable
Data bit
bit 7
Register
CSD
ENB
(Reserved)
W/R
W/R
—
• CSPOSV[9:0]:
bit 6
bit 5
bit 4
bit 3
CSPOSV
9
8
W/R
Cursor display vertical position in units of the number of lines.
The position of displaying the origin of the cursor is specified in terms of the display
address within the main screen.
• CSDENB:
Cursor display enable
CSDENB
Cursor display
0
Disable (Not displayed)
1
Enable (Displayed)
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OKI Semiconductor
ML87V3104
[#30h] Display memory horizontal position for main screen (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
2
1
0
bit 3
bit 2
bit 1
bit 0
11
10
MDPSTX
Register
3
W/R
W/R
[#31h] Display memory horizontal position for main screen (MSB)
Data bit
bit 7
bit 6
bit 5
Register
(Reserved)
W/R
—
• MDPSTX[11:0]:
bit 4
MDPSTX
9
8
W/R
Main screen display memory horizontal position in units of 16 pixels.
The start address of the display memory for displaying in the main screen is specified here.
[#32h] Display memory vertical position for main screen (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
11
10
MDPSTY
Register
W/R
W/R
[#33h] Display memory vertical position for main screen (MSB)
Data bit
bit 7
bit 6
bit 5
Register
(Reserved)
W/R
—
• MDPSTY[11:0]:
bit 4
MDPSTY
9
8
W/R
Main screen display memory vertical position in units of a line.
The start address of the display memory for displaying in the main screen is specified
here.
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FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#34h] Display memory horizontal position for sub-screen (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
11
10
SDPSTX
Register
W/R
W/R
[#35h] Display memory horizontal position for sub-screen (MSB)
Data bit
bit 7
bit 6
bit 5
Register
(Reserved)
W/R
—
• SDPSTX[11:0]:
bit 4
SDPSTX
9
8
W/R
Sub-screen display memory horizontal position in units of 16 pixels.
The start address of the display memory for displaying in the sub-screen is specified here.
[#36h] Display memory vertical position for sub-screen (LSB)
Data bit
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
3
2
1
0
bit 3
bit 2
bit 1
bit 0
11
10
SDPSTY
Register
W/R
W/R
[#37h] Display memory vertical position for sub-screen (MSB)
Data bit
bit 7
bit 6
bit 5
Register
(Reserved)
W/R
—
• SDPSTY[11:0]:
bit 4
SDPSTY
9
8
W/R
Sub-screen display memory vertical position in units of a line.
The start address of the display memory for displaying in the sub-screen is specified here.
56/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#38h] Display memory page number for main screen
Data bit
Register
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
2
1
0
MDPPGA
3
W/R
W/R
• MDPPGA[7:0]:
Main screen display memory page number
This is the page number of the display memory that is to be displayed in the main screen.
[#39h] Display memory page number for sub-screen
Data bit
Register
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
2
1
0
SDPPGA
3
W/R
W/R
• SDPPGA[7:0]:
Sub-screen display memory page number
This is the page number of the display memory that is to be displayed in the sub-screen.
[#3Bh] Display memory page for host access
Data bit
Register
W/R
• HSTPGA[7:0]:
bit 7
bit 6
bit 5
bit 4
7
6
5
4
bit 3
bit 2
bit 1
bit 0
2
1
0
HSTPGA
3
W/R
Host access display memory page number
This is the page number of the display memory to be accessed by the host CPU.
[#3Ch–3Fh] Writing and reading of these registers are prohibited
57/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage (for the internal core)
VDDI
—
–0.5 to +4.6
V
Power supply voltage (for the LCD driving signals)
VDDO
—
–0.5 to +4.6
V
Vout
—
VSS – 0.5 to VDD +0.5
V
Input voltage
Vin
—
VSS – 0.5 to VDD +0.5
V
Output short-circuit current
Ios
—
50
mA
Power dissipation
Pd
Ta = 25°C
1
W
Tstg
—
–55 to +150
°C
Output voltage
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
(VSS = 0 V)
Parameter
Power supply voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
Internal core
VDDI
3.0
3.3
3.6
V
LCD driving signals
VDDO
3.0
3.3
3.6
V
Ta
-40
25
85
°C
Operating temperature range
Note: VDDI and VDDO must be powered up at the same time.
58/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(Ta = -40 to 85°C, VDD = VDDO = VDDI = 3.3 ± 0.3 V, VSS = 0 V)
Parameter
H level input voltage
L level input voltage
H level input voltage
L level input voltage
XOSCI
Others
Symbol
Condition
Min.
Typ.
Max.
Unit
VIH1
—
2.4
—
VDDI+0.3
V
VIL1
—
VSS –0.3
—
0.4
V
VIH
—
2.0
—
5.5
V
VIL
—
VSS –0.3
—
0.8
V
H level output voltage
BSYN,
VOH1
IOH = 8 mA
0.8VDD
—
—
V
L level output voltage
PORT0,1
VOL1
IOL = 8 mA
—
—
0.2VDD
V
VOH2
IOH = 4 mA
0.8VDD
—
—
V
H level output voltage
L level output voltage
Others
VOL2
IOL = 4 mA
—
—
0.2VDD
V
Input leakage current
ILI
—
–10
—
+10
µA
Output leakage current
ILO
—
–10
—
+10
µA
—
—
55
mA
—
—
45
mA
—
—
5
mA
0.4
1.0
2.0
MΩ
Supply current
(internal core)
During operation
IDDI1
Display Off
IDDI2
Clock Stopping
IDDI3
Clock input feedback resistance
RF
fope = 15MHz
—
2. AC Characteristics
(Ta = -40 to 85°C, VDDO = VDDI = 3.3 ± 0.3 V, VSS = 0 V)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating frequency
fope
—
—
—
15.0
MHz
Output rise time (10% to 90%)
tRO
CL = 15 pF
2
—
15
ns
Output fall time (90% to 10%)
tFO
CL = 15 pF
2
—
15
ns
BCLK clock period
tCK1
—
66
—
—
ns
BCLK H level pulse width
tWH1
—
30
—
—
ns
BCLK L level pulse width
tWL1
—
30
—
—
ns
tS1
—
10
—
—
ns
Input setup time (to BCLK)
Input hold time (to BCLK)
tH1
—
8
—
—
ns
Output delay time (from BCLK)*1
tPD1
CL = 15 pF
5
—
20
ns
XOSCI clock period
tCK2
—
66
—
—
ns
XOSCI H level pulse width
tWH2
—
30
—
—
ns
tWL2
—
30
—
—
ns
XOSCI L level pulse width
1
Output delay time (XOSCI to CP, CPS)*
tPD2
CL = 15 pF
2
—
25
ns
Output hold time (from CP, CPS)*2
tHCP
CL = 15 pF
25
—
50
ns
*1: The output timing characteristics are measured at the signal levels of VDD/2.
*2: The output hold time is a relative value, which should be used as a reference value for application
design.
59/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
tCK1
tWH1
tWL1
VIH
BCLK
VIL
VIH
INPUT
VIL
(CSN, BSN, DSN,
WEN, REN,
REGS, A, AD, D)
VIH
VIL
tS1
tH1
tS1
tH1
OUTPUT
(BSYN, AD, D)
tPD1
tPD1
(a) Host interface
tCK2
tWH2
tWL2
VIH
XOSCI
VIL
CP, CPS
tPD2
tPD2
CP, CPS
OUTPUT
(DDAn, DDBn,
DDCn, DDDn,
LCP, FRP, DF)
tHCP
(b) LCD interface
Fig. A1 AC characteristics
60/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
TIMING DIAGRAMS
1. LCD Interface
1.1 Color STN, 4-bit mode
LCP
TCP
CP
DDA3
Gn-3
Bn-2
R0
DDA2
Bn-3
Rn-1
G0
DDA1
Rn-2
Gn-1
B0
DDA0
Gn-2
Bn-1
R1
G2
G1
B2
R4
G5
B6
R8
B1
R3
G4
R2
G3
B4
B3
R5
G6
G9
B10
B5
R7
G8
B9
R11
Bn-3
Rn-1
R6
G7
B8
R10
G11
Rn-2
Gn-1
B7
R9
G10
B11
Gn-2
Bn-1
Gn-3
Bn-2
(MSCSZH+1) × 3/4 [TCP]
(LCPCYC+1) [TCP]
TCP = TX (TX is the XOSCI input clock period)
1.2 Color STN, 8-bit mode
LCP
TCP
CP
DDA3
Gn-3
R0
B2
G5
R8
B10
DDA2
Bn-3
G0
R3
B5
G8
R11
Bn-3
DDA1
Rn-2
B0
G3
R6
B8
G11
Rn-2
Gn-2
Gn-3
DDA0
Gn-2
R1
B3
G6
R9
B11
DDB3
Bn-2
G1
R4
B6
G9
R12
Bn-2
DDB2
Rn-1
B1
G4
R7
B9
G12
Rn-1
DDB1
Gn-1
R2
B4
G7
R10
B12
Gn-1
DDB0
Bn-1
G2
R5
B7
G10
R13
Bn-1
(MSCSZH+1) × 3/8 [TCP]
(LCPCYC+1) [TCP]
TCP = 2TX (TX is the XOSCI input clock period)
61/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.3 Color STN, 4-bit 2-phase mode
LCP
TCP TCP
1/2TCP
CP
CPS
DDA3
Gn-3 Bn-2
R0
G0
B2
R3
G5
B5
R8
G8
B10
Gn-3 Bn-2
DDA2
Bn-3
Rn-1
B0
R1
G3
B3
R6
G6
B8
R9
G11
Bn-3
DDA1
Rn-2 Gn-1
G1
B1
R4
G4
B6
R7
G9
B9
R12
Rn-2 Gn-1
DDA0
Gn-2 Bn-1
R2
G2
B4
R5
G7
B7
R10
G10
B12
Gn-2 Bn-1
Rn-1
(MSCSZH+1) × 3/4 [TCP]
(LCPCYC+1) [TCP]
TCP = TX (TX is the XOSCI input clock period)
62/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.4 Monochrome STN, 4-bit mode
LCP
TCP
CP
DDA3
n-8
n-4
0
4
8
12
16
20
24
28
32
n-8
n-4
DDA2
n-7
n-3
1
5
9
13
17
21
25
29
33
n-7
n-3
DDA1
n-6
n-2
2
6
10
14
18
22
26
30
34
n-6
n-2
DDA0
n-5
n-1
3
7
11
15
19
23
27
31
35
n-5
n-1
(MSCSZH+1) / 4 [TCP]
(LCPCYC+1) [TCP]
TCP = 4TX (TX is the XOSCI input clock period)
1.5 Monochrome STN, 8-bit mode
LCP
TCP
CP
DDA3
n-8
0
8
16
24
32
n-8
DDA2
n-7
1
9
17
25
33
n-7
DDA1
n-6
2
10
18
26
34
n-6
DDA0
n-5
3
11
19
27
35
n-5
DDB3
n-4
4
12
20
28
36
n-4
DDB2
n-3
5
13
21
29
37
n-3
DDB1
n-2
6
14
22
30
38
n-2
DDB0
n-1
7
15
23
31
39
n-1
(MSCSZH+1) / 8 [TCP]
(LCPCYC+1) [TCP]
TCP = 8TX (TX is the XOSCI input clock period)
63/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.6 Monochrome STN, 4-bit 2-phase mode
LCP
TCP TCP
1/2TCP
CP
CPS
DDA3
n-8
n-7
0
1
8
9
16
17
24
25
32
n-8
n-7
DDA2
n-6
n-5
2
3
10
11
18
19
26
27
34
n-6
n-5
DDA1
n-4
n-3
4
5
12
13
20
21
28
29
36
n-4
n-3
DDA0
n-2
n-1
6
7
14
15
22
23
30
31
38
n-2
n-1
(MSCSZH+1) / 4 [TCP]
(LCPCYC+1) [TCP]
TCP = 4TX (TX is the XOSCI input clock period)
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FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.7 Color TFT, 12-bit mode
LCP
T CP
CP
CPS
DDA 3 (R3)
DDA2 (R2)
DDA1 (R1)
DDA0 (R0)
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
DDB 3 (G3)
DDB2 (G2)
DDB1 (G1)
DDB0 (G0)
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
DDC 3 (B3)
DDC2 (B2)
DDC1 (B1)
DDC0 (B0)
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
(DPSCH+1) [TCP ]
(DCYCH+1) [TCP ]
TCP = TX (TX is the XOSCI input clock period)
1.8 Color TFT, 16-bit mode
LCP
TCP
CP
CPS
DDA3 (R5)
DDA2 (R4)
DDA1 (R3)
DDA0 (R2)
DDB3 (R1)
n-2
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
n-1
0
0
0
0
0
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
6
7
7
7
7
7
8
8
8
8
8
n-2
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
n-1
DDB2 (G5)
DDB1 (G4)
DDB0 (G3)
DDC3 (G2)
DDC2 (G1)
DDC1 (G0)
n-2
n-2
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
n-1
n-1
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8
n-2
n-2
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
n-1
n-1
DDC0 (B5)
DDD3 (B4)
DDD2 (B3)
DDD1 (B2)
DDD0 (B1)
n-2
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
n-1
0
0
0
0
0
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
6
7
7
7
7
7
8
8
8
8
8
n-2
n-2
n-2
n-2
n-2
n-1
n-1
n-1
n-1
n-1
(DPSCH+1) [TCP]
(DCYCH+1) [TCP]
TCP = TX (TX is the XOSCI input clock period)
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FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.9 STN vertical timing
FRP
(FRPSTA+1) [TLCP]
TLCP
LCP
DDA3-0
Line 0
Line 1
Line 2
Line 3
Line 4
DDB3-0
Line 0
Line 1
Line 2
Line 3
Line 4
DDC3-0
Line 0
Line 1
Line 2
Line 3
Line 4
DDD3-0
Line 0
Line 1
Line 2
Line 3
Line 4
(MSCSZV+1) [TLCP]
(FRPCYC+1) [TLCP]
1.10 TFT vertical timing
FRP
(FRPSTA + 1) [TLCP]
TLCP
FRPWID
LCP
CPS
DDA3-0
Line 0
Line 1
Line 2
Line 3
DDB3-0
Line 0
Line 1
Line 2
Line 3
DDC3-0
Line 0
Line 1
Line 2
Line 3
DDD3-0
Line 0
Line 1
Line 2
Line 3
(MSCSZV+1) [TLCP]
(FRPCYC+1) [TLCP]
66/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
PACKAGE DIMENSIONS
TQFP100-P-1414-0.50-K
(Unit: mm)
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.55 TYP.
4/Oct. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
67/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
REVISION HISTORY
Document
No.
Date
Page
Previous Current
Edition
Edition
FEDL87V3104-01
Feb., 2001
–
–
FEDL87V3104-02
Nov., 2001
67
67
FEDL87V3104-03
Nov. 28, 2003
Description
First version released
1
1
Fixed the memory size descriptions
4
4
Added the pin types
5, 17
5, 17
Added the notations
10
10
Fixed the behavior at the Portrait mode
19
19
COLORD[1:0] Æ [2:0]
20
20
“352” Æ “360”
27
27
Added the descriptions
36
36
Added the descriptions of the bit number
40
40
LCDDAT[1:0] Æ [2:0]
42
42
58, 59
–
42
42
58, 59
68, 69
#02h bit3 “—” Æ “W/R”
IMDBPP[1:0] Æ [2:0]
Temp. ranges 0 to 70°C Æ -45 to 85°C
Added “REV. HISTORY” and “NOTICE” pages
68/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of property, or
death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
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