MICRONAS VCT3802A

ADVANCE INFORMATION
MICRONAS
Edition Oct. 17, 2000
6251-518-1AI
VCT 38xxA
Video/Controller/Teletext
IC Family
MICRONAS
VCT 38xxA
ADVANCE INFORMATION
Contents
Page
Section
Title
7
1.
Introduction
8
1.1.
Features
8
8
8
8
8
8
1.1.1.
1.1.2.
1.1.3.
1.1.4.
1.1.5.
1.1.6.
Video Features
Microcontroller Features
OSD Features
Teletext Features
Audio Features
General Features
9
1.2.
Chip Architecture
10
1.3.
System Application
11
2.
Video Processing
11
2.1.
Introduction
11
2.2.
Video Front-end
11
11
11
11
12
12
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.2.6.
Input Selector
Clamping
Automatic Gain Control
Analog-to-Digital Converters
Digitally Controlled Clock Oscillator
Analog Video Output
12
2.3.
Adaptive Comb Filter
13
2.4.
Color Decoder
13
14
14
14
14
14
15
15
16
16
2.4.1.
2.4.2.
2.4.3.
2.4.4.
2.4.5.
2.4.6.
2.4.7.
2.4.8.
2.4.9.
2.4.10.
IF-Compensation
Demodulator
Chrominance Filter
Frequency Demodulator
Burst Detection / Saturation Control
Color Killer Operation
Automatic Standard Recognition
PAL Compensation/ 1-H Comb Filter
Luminance Notch Filter
Skew Filtering
16
2.5.
Horizontal Scaler
16
2.6.
Black-line Detector
17
2.7.
Test Pattern Generator
17
2.8.
Video Sync Processing
18
2.9.
Macrovision Detection
18
2.10.
Display Processing
18
18
19
21
21
21
21
22
22
22
22
23
23
23
2.10.1.
2.10.2.
2.10.3.
2.10.4.
2.10.5.
2.10.6.
2.10.7.
2.10.8.
2.10.9.
2.10.10.
2.10.11.
2.10.12.
2.10.13.
2.10.14.
Luma Contrast Adjustment
Black-Level Expander
Dynamic Peaking
Digital Brightness Adjustment
Soft Limiter
Chroma Interpolation
Chroma Transient Improvement
Inverse Matrix
RGB Processing
OSD Color Look-up Table
Picture Frame Generator
Priority Decoder
Scan Velocity Modulation
Display Phase Shifter
2
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ADVANCE INFORMATION
VCT 38xxA
Contents, continued
Page
Section
Title
25
2.11.
Video Back-end
25
26
27
27
27
2.11.1.
2.11.2.
2.11.3.
2.11.4.
2.11.5.
CRT Measurement and Control
SCART Output Signal
Average Beam Current Limiter
Analog RGB Insertion
Fast-Blank Monitor
29
2.12.
Synchronization and Deflection
29
29
29
30
30
31
2.12.1.
2.12.2.
2.12.3.
2.12.4.
2.12.5.
2.12.6.
Deflection Processing
Angle and Bow Correction
Horizontal Phase Adjustment
Vertical and East/West Deflection
EHT Compensation
Protection Circuitry
31
2.13.
Reset Function
31
2.14.
Standby and Power-On
32
2.15.
I2C Bus Slave Interface
32
44
46
2.15.1.
2.15.1.1.
2.15.1.2.
Control and Status Registers
Scaler Adjustment
Calculation of Vertical and East-West Deflection Coefficients
47
3.
Text and OSD Processing
47
3.1.
Introduction
47
3.2.
SRAM Interface
47
3.3.
Text Controller
49
3.4.
Teletext Acquisition
49
3.5.
Teletext Page Management
49
50
50
52
52
3.5.1.
3.5.2.
3.5.3.
3.5.4.
3.5.5.
Memory Manager
Memory Organization
Page Table
Ghost Row Organization
Subpage Manager
53
3.6.
WST Display Controller
55
3.7.
Display Memory
57
3.8.
Character Generator
58
59
60
61
62
63
3.8.1.
3.8.2.
3.8.3.
3.8.4.
3.8.5.
3.8.6.
Character Code Mapping
Character Font ROM
Latin Font Mapping
Cyrillic Font Mapping
Arabic Font Mapping
Character Font Structure
64
3.9.
National Character Mapping
66
3.10.
Four-Color Mode
67
3.11.
OSD Layer
68
3.12.
Command Language
76
3.13.
I/O Register
82
3.14.
I2C-Bus Slave Interface
82
82
83
83
83
84
3.14.1.
3.14.1.1.
3.14.1.2.
3.14.1.3.
3.14.1.4.
3.14.1.5.
Subaddressing
CPU Subaddressing
DRAM Subaddressing
Command Subaddressing
Data Subaddressing
Hardware Identification
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VCT 38xxA
ADVANCE INFORMATION
Contents, continued
Page
Section
Title
85
4.
Audio Processing
85
4.1.
Introduction
85
4.2.
Input Select
85
4.3.
Volume Control
85
4.4.
I2C-Bus Slave Interface
86
5.
TV Controller
86
5.1.
Introduction
86
5.2.
CPU
86
5.2.1.
CPU Slow Mode
87
5.3.
RAM and ROM
87
87
5.3.1.
5.3.2.
Address Map
Bootloader
87
5.4.
Control Register
89
5.5.
Standby Registers
90
5.6.
Test Registers
90
5.7.
Reset Logic
90
90
91
91
91
92
92
93
94
94
94
5.7.1.
5.7.2.
5.7.2.1.
5.7.2.2.
5.7.3.
5.7.3.1.
5.7.3.2.
5.7.3.3.
5.7.4.
5.7.5.
5.7.6.
Alarm Function
Software Reset
From Standby into Normal Mode
From Normal into Standby Mode
Internal Reset Sources
Supply Supervision
Clock Supervision
Watchdog
External Reset Sources
Summary of Module Reset States
Reset Registers
95
5.8.
Memory Banking
95
5.8.1.
Banking Register
96
5.9.
DMA Interface
98
5.9.1.
DMA Registers
99
5.10.
Interrupt Controller
99
99
99
99
99
101
101
103
103
104
106
5.10.1.
5.10.2.
5.10.3.
5.10.4.
5.10.5.
5.10.6.
5.10.7.
5.10.8.
5.10.8.1.
5.10.9.
5.10.10.
Features
General
Initialization
Operation
Inactivation
Precautions
Interrupt Registers
Interrupt Assignment
Interrupt Multiplexer
Port Interrupt Module
Interrupt Timing
107
5.11.
Memory Patch Module
107
107
107
108
108
5.11.1.
5.11.2.
5.11.3.
5.11.4.
5.11.5.
Features
General
Initialization
Patch Operation
Patch Registers
109
5.12.
I2C-Bus Master Interface
111
5.12.1.
I2C Bus Master Interface Registers
4
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ADVANCE INFORMATION
VCT 38xxA
Contents, continued
Page
Section
Title
113
5.13.
Timer T0 and T1
113
113
114
5.13.1.
5.13.2.
5.13.3.
Features
Operation
Timer Registers
115
5.14.
Capture Compare Module (CAPCOM)
115
116
116
116
117
118
5.14.1.
5.14.2.
5.14.3.
5.14.3.1.
5.14.4.
5.14.5.
Features
Initialization
Operation of CCC
Operation of Subunit
Inactivation
CAPCOM Registers
120
5.15.
Pulse Width Modulator
120
120
120
120
120
5.15.1.
5.15.2.
5.15.3.
5.15.4.
5.15.5.
Features
General
Initialization
Operation
PWM Registers
121
5.16.
Tuning Voltage Pulse Width Modulator
121
121
122
122
122
5.16.1.
5.16.2.
5.16.3.
5.16.4.
5.16.5.
Features
General
Initialization
Operation
TVPWM Registers
123
5.17.
A/D Converter (ADC)
123
123
124
124
125
5.17.1.
5.17.2.
5.17.3.
5.17.4.
5.17.5.
Features
Operation
Measurement Errors
Comparator
ADC Registers
126
5.18.
Ports
126
127
127
128
128
129
129
130
130
131
131
5.18.1.
5.18.2.
5.18.2.1.
5.18.2.2.
5.18.3.
5.18.4.
5.18.4.1.
5.18.5.
5.18.5.1.
5.18.6.
5.18.6.1.
Port Assignment
Universal Ports P1 to P3
Features
Universal Port Mode
Universal Port Registers
I2C Ports P40 and P41
Features
Audio Ports P42 to P46
Features
CLK20 Output Port
Features
132
5.19.
I/O Register Cross Reference
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VCT 38xxA
ADVANCE INFORMATION
Contents, continued
Page
Section
Title
136
6.
Specifications
136
6.1.
Outline Dimensions
138
6.2.
Pin Connections and Short Descriptions
142
6.3.
Pin Descriptions for PSDIP64 package
144
6.4.
Pin Descriptions for PMQFP128 package
145
6.5.
Pin Configuration
147
6.6.
Pin Circuits
150
6.7.
Electrical Characteristics
150
150
150
151
152
153
153
153
154
154
155
155
155
156
158
159
159
159
159
160
160
160
160
161
161
164
164
165
165
166
6.7.1.
6.7.2.
6.7.2.1.
6.7.2.2.
6.7.2.3.
6.7.3.
6.7.3.1.
6.7.3.2.
6.7.3.3.
6.7.3.4.
6.7.3.5.
6.7.3.6.
6.7.3.7.
6.7.3.8.
6.7.3.9.
6.7.3.10.
6.7.3.11.
6.7.3.12.
6.7.3.13.
6.7.3.14.
6.7.3.15.
6.7.3.16.
6.7.3.17.
6.7.3.18.
6.7.3.19.
6.7.3.20.
6.7.3.21.
6.7.3.22.
6.7.3.23.
6.7.3.24.
Absolute Maximum Ratings
Recommended Operating Conditions
General Recommendations
Analog Input and Output Recommendations
Recommended Crystal Characteristics
Characteristics
General Characteristics
Test Input
Reset Input
I2C Bus Interface
20-MHz Clock Output
Analog Video Output
A/D Converter Reference
Analog Video Front-End and A/D Converters
Analog RGB and FB Inputs
Horizontal Flyback Input
Horizontal Drive Output
Vertical Safety Input
Vertical Protection Input
Vertical and East/West D/A Converter Output
Interlace Output
Sense A/D Converter Input
Range Switch Output
D/A Converter Reference
Analog RGB Outputs, D/A Converters
Scan Velocity Modulation Output
Analog Audio Inputs and Outputs
ADC Input Port
Universal Port
Memory Port
167
7.
Application
171
8.
Glossary of Abbreviations
171
9.
References
172
10.
Data Sheet History
6
Micronas
VCT 38xxA
ADVANCE INFORMATION
Video/Controller/Teletext IC Family
Release Note: This data sheet describes functions
and characteristics of the VCT 38xxA-B2.
1. Introduction
The VCT 38xxA is an IC family of high-quality singlechip TV processors. Modular design and a submicron
technology allow the economic integration of features
in all classes of TV sets. The VCT 38xxA family is
based on functional blocks contained and approved in
existing products like VDP 3120B, TPU 3050S, and
CCZ 3005K.
The VCT 38xxA family offers a rich feature set, covering the whole range of state-of-the-art 50/60-Hz TV
applications.
✔
VCT 3803A
✔
✔
✔
VCT 3804A
✔
✔
✔
VCT 3811A
✔
VCT 3831A
✔
VCT 3832A
✔
✔
VCT 3833A
✔
✔
✔
VCT 3834A
✔
✔
✔
10 Page Teletxt
1 Page Teletxt
ext. Prog. Memory
✔
PMQFP128
VCT 3802A
ext. Page Memory
✔
PMQFP128
VCT 3801A
Panorama Scaler
Adaptive Comb Filter
Picture Improvements
(Color Transient Improv.,
Soft Limiter,
Black-Level Expander)
VCT 38xxA
Family
8-Bit Microcontroller
96 kB ROM, 1 kB RAM
Flash Option
Color Decoder
Tube Control
OSD Generator
Audio Control
Each member of the family contains the entire video,
display and deflection processing for 4:3 and 16:9 50/
60-Hz TV sets. The integrated microcontroller is supported by a powerful OSD generator with integrated
teletext acquisition which can be upgraded with onchip page memory. With volume control and audio
input select the basic audio features for mono TV sets
are integrated. An overview of the VCT 38xxA singlechip TV processor family is given in Fig. 1–1 on
page 7.
✔
✔
✔
✔
✔
✔
✔
Fig. 1–1: VCT 38xxA family overview
Micronas
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VCT 38xxA
ADVANCE INFORMATION
1.1. Features
1.1.1. Video Features
1.1.3. OSD Features
– four composite video inputs, two S-VHS inputs
– 3 kB OSD RAM on chip
– analog YCrCb input
– WST level 1.5 compliant
– composite video monitor
– WST level 2 parallel attributes
– multistandard color decoder (1 crystal)
– 32 foreground/background colors
– multistandard sync decoder
– programmable color look-up table
– black-line detector
– 1024 mask programmable characters
– adaptive 2H comb filter Y/C separator
– 24 national languages
(Latin, Cyrillic, Greek, Arabic, Farsi, Hebrew)
– horizontal scaling (0.25 to 4)
– Panoramavision
– black-level expander
– dynamic peaking
– character matrix 8x8, 8x10, 8x13, 10x8, 10x10, 10x13
– vertical soft scroll
– 4-color mode for user font
– soft limiter (gamma correction)
– color transient improvement
– programmable RGB matrix
– analog RGB/Fastblank input
– half-contrast switch
– picture frame generator
– scan velocity modulation output
– high-performance H/V deflection
– angle and bow correction
– separate ADC for tube measurements
– EHT compensation
1.1.2. Microcontroller Features
– 8-bit, 10-MHz CPU (65C02)
– 96 kB program ROM on chip
– 1 kB program RAM on chip
– memory banking
1.1.4. Teletext Features
– four programmable video inputs
– acquisition is independent from display part
– adaptive data slicer
– signal quality detection
– WST, PDC, VPS, and WSS acquisition
– high-level command language
– EPG, FLOF, and TOP support
– 10 pages memory on chip
– up to 500 pages with external SRAM
1.1.5. Audio Features
– three mono inputs
– two mono outputs
– programmable channel select
– volume control for one mono channel
– 16-input, 16-level interrupt controller
– patch modul for 10 ROM locations
– two 16-bit reloadable timers
– capture compare modul
– watchdog timer
– 14-bit PWM for voltage synthesis
– four 8-bit PWMs
– 10-bit ADC with 15:1 input MUX
1.1.6. General Features
– submicron CMOS technology
– low-power standby mode
– single 20.25-MHz crystal
– 64-pin PSDIP package
– 128-pin PMQFP package
– emulator chip for software development
– I2C bus master interface
– 24 programmable I/O ports
8
Micronas
VCT 38xxA
ADVANCE INFORMATION
VIN
CIN
2
4
3
Video
Front-end
Comb
Filter
Panorama
Scaler
Color
Decoder
2
RSW
GNDM
VRD
XREF
SENSE
HFLB
VERT
EW
PROT
HOUT
GNDD
VCT 38xx
VSUPD
GNDAF
VSUPAF
SGND
VRT
1.2. Chip Architecture
2
Display
Processor
3
Video
Back-end
Pict.Improv.
VOUT
RGBOUT
SVM
4
RGBIN
Video
VSUPAB
GNDAB
I2C
MSync
Color, Prio
8
2
Audio
3
AOUT
AIN
VSync
I2C Master
BE
TPU
DMA
CPU
RDY
24
24 kB ROM
kB
2
I2C
8-bit PWM
14-bit PWM
1 kB
CPU RAM
3 3kB
kB
OSD
OSDRAM
15:1 Mux
10-bit ADC
2 Timer
Reset
Logic
RESQ
Clock
Oscillator
XTAL1
TEST
2 CapCom
96 kB
CPU ROM
Watchdog
24 IO Ports
31
ADB, DB, CB
GNDP1
VSUPP1
GNDS
VSUPS
XTAL2
CLK20
12
Pxy
16 kB
Text RAM
Fig. 1–2: Block diagram of the VCT 38xxA (shaded blocks are optional)
Micronas
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VCT 38xxA
ADVANCE INFORMATION
1.3. System Application
Analog RGB
R
G
B
FB
Analog Audio
20.25 MHz
Tuner/SCART/FrontAV
CVBS1
Analog Video
Loudspeaker
CVBS2
Y
Cr
VCT 38xxA
Cb
Y
CRT
C
WE2 OE2 CE
CE OE1 WE1
DB
512 kB
SRAM
ADB
512 kB
ROM/
FLASH
optional memory extension
Fig. 1–3: Single-chip TV with VCT 38xxA
10
Micronas
VCT 38xxA
ADVANCE INFORMATION
2. Video Processing
2.2.2. Clamping
2.1. Introduction
All processing is done digitally, the video front-end and
video back-end are interfacing to the analog world.
Most functions of the VDP can be controlled by software via I2C bus slave interface (see Section 2.15. on
page 32).
The composite video input signals are AC-coupled to
the IC. The clamping voltage is stored on the coupling
capacitors and is generated by digitally controlled current sources. The clamping level is the back porch of
the video signal. S-VHS chrominance is also AC-coupled. The input pin is internally biased to the center of
the ADC input range. The chrominance inputs for
YCrCb need to be AC-coupled by 220 nF clamping
capacitors. It is strongly recommended to use 5-MHz
anti-alias low-pass filters on each input. Each channel
is sampled at 10.125 MHz with a resolution of 8 bit and
a clamping level of 128.
2.2. Video Front-end
2.2.3. Automatic Gain Control
This block provides the analog interfaces to all video
inputs and mainly carries out analog-to-digital conversion for the following digital video processing. A block
diagram is given in Fig. 2–1.
Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO). The
control loops are closed by the Fast Processor (‘FP’)
embedded in the video decoder.
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in
64 logarithmic steps to the optimal range of the ADC.
The gain of the video input stage including the ADC is
213 steps/V with the AGC set to 0 dB. The gain of the
chrominance path in the YCrCb mode is fix and
adapted to a nominal amplitude of 0.7 Vpp. However, if
an overflow of the ADC occurs an extended signal
range from 1 Vpp can be selected.
2.2.1. Input Selector
2.2.4. Analog-to-Digital Converters
Up to seven analog inputs can be connected. Four
inputs are for input of composite video or S-VHS luma
signal. These inputs are clamped to the sync back
porch and are amplified by a variable gain amplifier.
Two chroma inputs can be used for connection of
S-VHS carrier-chrominance signal. These inputs are
internally biased and have a fixed gain amplifier. For
analog YCrCb signals (e.g. from DVD players) one of
the selected luminance inputs is used together with
CBIN and CRIN inputs.
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the
required reference voltages for the converters. The two
ADCs are of a 2-stage subranging type.
The VCT 38xxA includes complete video, display, and
deflection processing. In the following sections the
video processing part of the VCT 38xxA will be named
VDP for short.
CVBS/Y
CVBS/Y
CVBS/Y
Chroma
Chroma
VIN1
3
Clamp
VIN2
VIN3
VIN4
CIN1
Bias
CIN2
CRIN
CBIN
ADC
digital CVBS or Luma
ADC
digital Chroma
Gain
Clamp
Chroma
AGC
+6/–4.5 dB
System Clocks
mux
CVBS/Y
VOUT
Input
Mux
CVBS/Y
Reference
Generation
DVCO
±150
ppm
Frequency
20.25 MHz
Fig. 2–1: Video front-end
Micronas
11
VCT 38xxA
ADVANCE INFORMATION
2.2.5. Digitally Controlled Clock Oscillator
The clock generation is also a part of the analog frontend. The crystal oscillator is controlled digitally by the
control processor. The clock frequency can be
adjusted within ±150 ppm.
The comb filter uses the middle line as reference,
therefore, the comb filter delay is one line. If the comb
filter is switched off, the delay lines are used to pass
the luma/ chroma signals from the A/D converters to
the luma/ chroma outputs. Thus, the comb filter delay
is always one line.
Various parameters of the comb filter are adjustable,
hence giving to the user the ability to adjust his own
desired picture quality.
The input signal of the Luma ADC is available at the
analog video output pin. The signal at this pin must be
buffered by a source follower. The output voltage is
2 V, thus the signal can be used to drive a 75-Ω line.
The magnitude is adjusted with an AGC in 8 steps
together with the main AGC.
2.3. Adaptive Comb Filter
The adaptive comb filter is used for high-quality luminance/chrominance separation for PAL or NTSC signals. The comb filter improves the luminance resolution (bandwidth) and reduces interferences like
cross-luminance and cross-color artifacts. The adaptive algorithm can eliminate most of the mentioned
errors without introducing new artifacts or noise.
A block diagram of the comb filter is shown in Fig. 2–2.
The filter uses two line delays to process the information of three adjacent video lines. To have a fixed
phase relationship of the color subcarrier in the three
channels, the system clock (20.25 MHz) is fractionally
locked to the color subcarrier. This allows the processing of all color standards and substandards using a
single crystal frequency.
The CVBS signal in the three channels is filtered at the
subcarrier frequency by a set of bandpass/notch filters. The output of the three channels is used by the
adaption logic to select the weighting that is used to
reconstruct the luminance/chrominance signal from
the 4 bandpass/notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption
algorithm are completely suppressed.
Two parameters (KY, KC) set the global gain of luma
and chroma comb separately; these values directly
weigh the adaption algorithm output. In this way, it is
possible to obtain a luma/chroma separation ranging
from standard notch/bandpass to full comb decoding.
The parameter KB allows to choose between the two
proposed comb booster modes. This so-called feature
widely improves vertical high-to-low frequency transitions areas, the typical example being a multiburst to
DC change. For KB=0, this improvement is kept moderate, whereas, in case of KB=1, it is maximum, but
the risk to increase the “hanging dots” amount for
some given color transitions is higher.
Using the default setting, the comb filter has separate
luma and chroma decision algorithms; however, it is
possible to switch the chroma comb factor to the current luma adaption output by setting CC to 1.
Another interesting feature is the programmable limitation of the luma comb amount; proper limitation, associated to adequate luma peaking, gives rise to an
enhanced 2-D resolution homogeneity. This limitation
is set by the parameter CLIM, ranging from 0 (no limitation) to 31 (max. limitation).
The DAA parameter (1:off, 0:on) is used to disable/
enable a very efficient built-in “rain effect” suppressor;
many comb filters show this side effect which gives
some vertical correlation to a 2-D uniform random
area, due to the vertical filtering. This unnatural-looking phenomenon is mostly visible on tuner images,
since they are always corrupted by some noise; and
this looks like rain.
Bandpass
Filter
CVBS Input
1H Delay Line
1H Delay Line
Bandpass/
Notch
Filter
Bandpass
Filter
Luma / Chroma Mixers
Adaption Logic
2.2.6. Analog Video Output
Luma Output
Chroma Output
Chroma Input
Fig. 2–2: Block diagram of the adaptive comb filter (PAL mode)
12
Micronas
VCT 38xxA
ADVANCE INFORMATION
2.4. Color Decoder
If the adaptive comb filter is used for luma chroma separation, the color decoder uses the S-VHS mode processing. The output of the color decoder is YCrCb in a
4:2:2 format.
In this block, the standard luma/chroma separation and
multi-standard color demodulation is carried out. The
color demodulation uses an asynchronous clock, thus
allowing a unified architecture for all color standards.
A block diagram of the color decoder is shown in Fig.
2–3. The luma as well as the chroma processing, is
shown here. The color decoder provides also some
special modes, e.g. wide band chroma format which is
intended for S-VHS wide bandwidth chroma.
Notch
Filter
MUX
Luma / CVBS
1 H Delay
Luma
Chroma
CrossSwitch
MUX
ACC
Chroma
IF Compensation
Mixer
DC-Reject
Low-pass Filter
Phase/Freq
Demodulator
ColorPLL/ColorACC
Fig. 2–3: Color decoder
2.4.1. IF-Compensation
With off-air or mistuned reception, any attenuation at
higher frequencies or asymmetry around the color
subcarrier is compensated. Four different settings of
the IF-compensation are possible:
– flat (no compensation)
– 6 dB/octave
– 12 dB/octave
– 10 dB/MHz
The last setting gives a very large boost to high frequencies. It is provided for SECAM signals that are
decoded using a SAW filter specified originally for the
PAL standard.
Micronas
Fig. 2–4: Frequency response of chroma IF-compensation
13
VCT 38xxA
ADVANCE INFORMATION
2.4.2. Demodulator
2.4.4. Frequency Demodulator
The entire signal (which might still contain luma) is
now quadrature-mixed to the baseband. The mixing
frequency is equal to the subcarrier for PAL and NTSC,
thus achieving the chroma demodulation. For SECAM,
the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated
chroma. After the mixer, a low-pass filter selects the
chroma components; a downsampling stage converts
the color difference signals to a multiplexed half-rate
data stream.
The frequency demodulator for demodulating the
SECAM signal is implemented as a CORDIC structure.
It calculates the phase and magnitude of the quadrature components by coordinate rotation.
The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore, substandards such as PAL 3.58 or NTSC 4.43 can also be
demodulated.
2.4.3. Chrominance Filter
The demodulation is followed by a low-pass filter for
the color difference signals for PAL/NTSC. SECAM
requires a modified low-pass function with bell-filter
characteristic. At the output of the low-pass filter, all
luma information is eliminated.
The low-pass filters are calculated in time multiplex for
the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard.
For PAL/NTSC, a wide band chroma filter can be
selected. This filter is intended for high bandwidth
chroma signals, e.g. a non-standard wide bandwidth
S-VHS signal.
The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After
the deemphasis filter, the Dr and Db signals are scaled
to standard CrCb amplitudes and fed to the crossover
switch.
2.4.5. Burst Detection / Saturation Control
In the PAL/NTSC-system the burst is the reference for
the color signal. The phase and magnitude outputs of
the CORDIC are gated with the color key and used for
controlling the phase-locked-loop (APC) of the demodulator and the automatic color control (ACC) in PAL/
NTSC.
The ACC has a control range of +30... −6 dB.
Color saturation can be selected once for all color
standards. In PAL/NTSC it is used as reference for the
ACC. In SECAM the necessary gains are calculated
automatically.
For SECAM decoding, the frequency of the burst is
measured. Thus, the current chroma carrier frequency
can be identified and is used to control the SECAM
processing. The burst measurements also control the
color killer operation; they are used for automatic standard detection as well.
2.4.6. Color Killer Operation
PAL/NTSC
The color killer uses the burst-phase/burst-frequency
measurement to identify a PAL/NTSC or SECAM color
signal. For PAL/NTSC, the color is switched off (killed)
as long as the color subcarrier PLL is not locked. For
SECAM, the killer is controlled by the toggle of the
burst frequency. The burst amplitude measurement is
used to switch-off the color if the burst amplitude is
below a programmable threshold. Thus, color will be
killed for very noisy signals. The color amplitude killer
has a programmable hysteresis.
SECAM
Fig. 2–5: Frequency response of chroma filters
14
Micronas
VCT 38xxA
ADVANCE INFORMATION
2.4.7. Automatic Standard Recognition
CVBS
The burst-frequency measurement is also used for
automatic standard recognition (together with the status of horizontal and vertical locking) thus allowing a
completely independent search of the line and color
standard of the input signal. The following standards
can be distinguished:
PAL B,G,H,I; NTSC M; SECAM; NTSC 44; PAL M;
PAL N; PAL 60
Y
Notch
filter
8
For error handling the recognition algorithm delivers
the following status information:
Y
8
Chroma
Process.
Cr C b
a) conventional
chroma
8
Chroma
Process.
Cr C b
b) S-VHS
CVBS
Y
Notch
filter
8
Chroma
Process.
For a preselection of allowed standards, the recognition can be enabled/disabled via I2C bus for each standard separately.
If at least one standard is enabled, the VCT 38xxA regularly checks the horizontal and vertical locking of the
input signal and the state of the color killer. If an error
exists for several adjacent fields a new standard
search is started. Depending on the measured line
number and burst frequency, the current standard is
selected.
Luma
Cr C b
1H
Delay
c) compensated
8
Y
Notch
filter
CVBS
1H
Delay
Cr C b
Chroma
Process.
d) comb filter
Fig. 2–6: NTSC color decoding options
– search active (busy)
– search terminated, but failed
– found standard is disabled
CVBS
8
Y
Notch
filter
– vertical standard invalid
Chroma
Process.
– no color found
Cr C b
1H
Delay
a) conventional
Luma
2.4.8. PAL Compensation/1-H Comb Filter
The color decoder uses one fully integrated delay line.
Only active video is stored.
The delay line application depends on the color standard:
– NTSC:
1-H comb filter or color compensation
– PAL:
color compensation
– SECAM: crossover switch
In the NTSC compensated mode, (Fig. 2–6c), the color
signal is averaged for two adjacent lines. Thus,
cross-color distortion and chroma noise is reduced. In
the NTSC comb filter mode, (Fig. 2–6d), the delay line
is in the composite signal path, thus allowing reduction
of cross-color components, as well as cross-luminance. The loss of vertical resolution in the luminance
channel is compensated by adding the vertical detail
signal with removed color information.
Micronas
Y
8
Chroma
8
Chroma
Process.
Cr C b
1H
Delay
b) S-VHS
Fig. 2–7: PAL color decoding options
CVBS
8
Y
Notch
filter
Chroma
Process.
1H
Delay
MUX
Cr C b
Fig. 2–8: SECAM color decoding
15
VCT 38xxA
ADVANCE INFORMATION
2.4.9. Luminance Notch Filter
2.5. Horizontal Scaler
If a composite video signal is applied, the color information is suppressed by a programmable notch filter.
The position of the filter center frequency depends on
the subcarrier frequency for PAL/NTSC. For SECAM,
the notch is directly controlled by the chroma carrier
frequency. This considerably reduces the cross-luminance. The frequency responses for all three systems
are shown in Fig. 2–9.
The 4:2:2 YCrCb signal from the color decoder is processed by the horizontal scaler. The scaler block
allows a linear or nonlinear horizontal scaling of the
input video signal in the range of 0.25 to 4. Nonlinear
scaling, also called “Panoramavision”, provides a geometrical distortion of the input picture. It is used to fit a
picture with 4:3 format on a 16:9 screen by stretching
the picture geometry at the borders. Also, the inverse
effect can be produced by the scaler. A summary of
scaler modes is given in Table 2–1.
10
dB
The scaler contains a programmable decimation filter,
a 1-line FIFO memory, and a programmable interpolation filter. The scaler input filter is also used for pixel
skew correction (see Section 2.4.10. on page 16). The
decimator/interpolator structure allows optimal use of
the FIFO memory. The controlling of the scaler is done
by the internal Fast Processor.
0
–10
–20
–30
–40
0
2
4
6
8
10
MHz
PAL/NTSC notch filter
10
Table 2–1: Scaler modes
Mode
Scale
Factor
Description
Compression
4:3 → 16:9
0.75
linear
4:3 source displayed on
a 16:9 tube,
with side panels
Panorama
4:3 →16:9
nonlinear
compr
4:3 source displayed on
a 16:9 tube,
Borders distorted
Zoom
4:3 → 4:3
1.33
linear
Letterbox source (PAL+)
displayed on a 4:3 tube,
vertical overscan with
cropping of side panels
Panorama
4:3 → 4:3
nonlinear
zoom
Letterbox source (PAL+)
displayed on a 4:3 tube,
vertical overscan, borders distorted, no cropping
dB
0
–10
–20
–30
–40
0
2
4
6
8
10
MHz
SECAM notch filter
Fig. 2–9: Frequency responses of the luma
notch filter for PAL, NTSC, SECAM
2.4.10.Skew Filtering
The system clock is free-running and not locked to the
TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCrCb signals are
converted to an orthogonal sampling raster by the
skew filters, which are part of the scaler block.
The skew filters allow the application of a group delay
to the input signals without introducing waveform or
frequency response distortion.
The amount of phase shift of this filter is controlled by
the horizontal PLL1. The accuracy of the filters is 1/32
clocks for luminance and 1/4 clocks for chroma. Thus
the 4:2:2 YCrCb data is in an orthogonal pixel format
even in the case of nonstandard input signals such as
VCR.
16
2.6. Black-line Detector
In case of a letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas at the upper and lower
part of the picture are visible. It is suitable to remove or
reduce these areas by a vertical zoom and/or shift
operation.
The VCT 38xxA supports this feature by a letterbox
detector. The circuitry detects black video lines by
measuring the signal amplitude during active video.
For every field the number of black lines at the upper
and lower part of the picture are measured, compared
to the previous measurement and the minima are
stored in the I2C-register BLKLIN. To adjust the picture
Micronas
VCT 38xxA
ADVANCE INFORMATION
amplitude, the external controller reads this register,
calculates the vertical scaling coefficient and transfers
the new settings, e.g. vertical sawtooth parameters,
horizontal scaling coefficient etc., to the VCT 38xxA.
Letterbox signals containing logos on the left or right
side of the black areas are processed as black lines,
while subtitles, inserted in the black areas, are processed as non-black lines. Therefore, the subtitles are
visible on the screen. To suppress the subtitles, the
vertical zoom coefficient is calculated by selecting the
larger number of black lines only. Dark video scenes
with a low contrast level compared to the letterbox area
are indicated by the BLKPIC bit.
sures the falling edge of sync, as well as the integrated
sync pulse.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it
thus counts synchronously to the video signal.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/minimum of the video signal. This information is processed
by the FP and used for gain control and clamping.
For vertical sync separation, the sliced video signal is
integrated. The FP uses the integrator value to derive
vertical sync and field information.
2.7. Test Pattern Generator
The YCrCb outputs can be switched to a test mode
where YCrCb data are generated digitally in the
VCT 38xxA. Test patterns include luma/chroma ramps
and flat fields.
The information extracted by the video sync processing is multiplexed onto the hardware front sync signal
(FSY) and is distributed to the rest of the video processing system.
The data for the vertical deflection, the sawtooth, and
the East-West correction signal is calculated by the
VCT 38xxA. The data is buffered in a FIFO and transferred to the back-end by a single wire interface.
2.8. Video Sync Processing
Fig. 2–10 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase low-pass filter eliminates
all noise and video contents above 1 MHz. The sync is
separated by a slicer; the sync phase is measured. A
variable window can be selected to improve the noise
immunity of the slicer. The phase comparator mea-
Frequency and phase characteristics of the analog
video signal are derived from PLL1. The results are fed
to the scaler unit for data interpolation and orthogonalization and to the clock synthesizer for line-locked
clock generation. Horizontal and vertical syncs are
latched with the line-locked clock.
PLL1
low-pass
1 MHz
&
sync slicer
Horizontal
Sync
Separation
Phase
Separator
&
Low-pass
counter
Front
Sync
Generator
Front-end
Timing
Clock
Synthesizer
Syncs
Front Sync
Skew
Vblank
Field
video
input
Clock
H/V Syncs
Clamp &
Signal
Meas.
clamping, colorkey, FIFO_write
Vertical
Sync
Separation
Sawtooth
Parabola
Calculation
FIFO
Vertical
Serial
Data
Vertical
E/W
Sawtooth
Fig. 2–10: Sync separation block diagram
Micronas
17
VCT 38xxA
ADVANCE INFORMATION
2.9. Macrovision Detection
2.10.2.Black-Level Expander
Video signals from Macrovision encoded VCR tapes
are decoded without loss of picture quality. However, it
might be necessary in some applications to detect the
presence of Macrovision encoded video signals. This
is possible by reading the Macrovision status register
(FP-RAM 0x170).
The black-level expander enhances the contrast of the
picture. Therefore the luminance signal is modified
with an adjustable, non-linear function. Dark areas of
the picture are changed to black, while bright areas
remain unchanged. The advantage of this black-level
expander is that the black expansion is performed only
if it will be most noticeable to the viewer.
Macrovision encoded video signals typically have AGC
pulses and pseudo sync pulses added during VBI. The
amplitude of the AGC pulses is modulated in time. The
Macrovision detection logic measures the VBI lines
and compares the signal against thresholds.
The window wherein the video lines are checked for
Macrovision pulses can be defined in terms of start
and stop line (e.g. 6-15 for NTSC).
The black-level expander works adaptively. Depending
on the measured amplitudes ‘Lmin’ and ‘Lmax’ of the
low-pass-filtered luminance and an adjustable coefficient BTLT, a tilt point ‘Lt’ is established by
Lt = Lmin + BTLT (Lmax - Lmin).
Above this value there is no expansion, while all luminance values below this point are expanded according
to:
2.10.Display Processing
Lout = Lin + BAM (Lin - Lt)
In the display processing the conversion from digital
YCrCb to analog RGB is carried out. A block diagram is
shown in Fig. 2–18 on page 24. In the luminance processing path, contrast and brightness adjustments and
a variety of features, such as black-level expansion,
dynamic peaking and soft limiting, are provided. In the
chrominance path, the CrCb signals are converted to
4:4:4 format and filtered by a color transient improvement circuit. The YCrCb signals are converted by a
programmable matrix to RGB color space.
A second threshold, Ltr, can be programmed, above
which there is no expansion. The characteristics of the
black-level expander are shown in Fig. 2–11and Fig.
2–12.
Lmax
Lout
Ltr
The display processor provides separate control settings for two pictures, i.e. different coefficients for a
‘main’ and a ‘side’ picture.
The digital OSD insertion circuit allows the insertion of
a 5-bit OSD signal. The color space for this signal is
controlled by a partially programmable color look-up
table (CLUT) and contrast adjustment.
The OSD signals and the display clock are synchronized to the horizontal flyback. For the display clock, a
gate delay phase shifter is used. In the analog backend, three 10-bit digital-to-analog converters provide
the analog output signals.
2.10.1.Luma Contrast Adjustment
The contrast of the luminance signal can be adjusted
by multiplication with a 6-bit contrast value. The contrast value corresponds to a gain factor from 0 to 2,
where the value 32 is equivalent to a gain of 1. The
contrast can be adjusted separately for main picture
and side picture.
18
Lt
BAM
BTLT
Lmin
Ltr
BTHR
Lin
Fig. 2–11: Characteristics of the black-level expander
The tilt point Lt is a function of the dynamic range of
the video signal. Thus, the black-level expansion is
only performed when the video signal has a large
dynamic range. Otherwise, the expansion to black is
zero. This allows the correction of the characteristics of
the picture tube.
Micronas
VCT 38xxA
ADVANCE INFORMATION
dB
Lmax
a)
20
15
10
Lt
Lmin
5
0
–5
–10
–15
b)
–20
MHz
0
Lt
2
4
6
8
10
Fig. 2–13: Dynamic peaking frequency response
Fig. 2–12: Black-level expansion
a) luminance input
b) luminance input and output
2.10.3.Dynamic Peaking
Especially with decoded composite signals and notch
filter luminance separation, as input signals, it is necessary to improve the luminance frequency characteristics. With transparent, high-bandwidth signals, it is
sometimes desirable to soften the image.
In the VCT 38xxA, the luma response is improved by
‘dynamic’ peaking. The algorithm has been optimized
regarding step and frequency response. It adapts to
the amplitude of the high-frequency part. Small AC
amplitudes are processed, while large AC amplitudes
stay nearly unmodified.
The dynamic range can be adjusted from −14 to
+14 dB for small high-frequency signals. There is separate adjustment for signal overshoot and for signal
undershoot. For large signals, the dynamic range is
limited by a non-linear function that does not create
any visible alias components. The peaking can be
switched over to “softening” by inverting the peaking
term by software.
The center frequency of the peaking filter is switchable
from 2.5 MHz to 3.2 MHz. For S-VHS and for notch filter
color decoding, the total system frequency responses
for both PAL and NTSC are shown in Fig. 2–14.
Transients, produced by the dynamic peaking when
switching video source signals, can be suppressed via
the priority bus.
Micronas
19
VCT 38xxA
ADVANCE INFORMATION
dB
dB
20
20
CF=3.2 MHz
15
10
5
5
S-VHS
0
0
-5
-5
-10
-10
-15
-20
-15
0
2
4
6
8
10
MHz
-20
dB
0
2
4
6
8
10
MHz
dB
20
20
CF=3.2 MHz
15
CF=2.5 MHz
15
10
10
5
5
PAL/SECAM
0
0
-5
-5
-10
-10
-15
-20
CF=2.5 MHz
15
10
-15
0
2
4
6
8
10
MHz
-20
0
2
4
6
8
10
MHz
dB
dB
20
20
CF=3.2 MHz
15
CF=2.5 MHz
15
10
10
5
5
NTSC
0
0
-5
-5
-10
-10
-15
-15
-20
MHz
0
2
4
6
8
10
-20
MHz
0
2
4
6
8
10
Fig. 2–14: Total frequency response for peaking filter and S-VHS, PAL, NTSC
20
Micronas
VCT 38xxA
ADVANCE INFORMATION
2.10.4.Digital Brightness Adjustment
Part 1 includes adjustable tilt point and gain. The gain
before the tilt value is 1. Above the tilt value, a part
(0...15/16) of the input signal is subtracted from the
input signal itself. Therefore, the gain is adjustable
from 16/16 to 1/16, when the slope value varies from
0 to 15. The tilt value can be adjusted from 0 to 511.
The DC-level of the luminance signal can be adjusted
by adding an 8-bit number in the luminance signal path
in front of the softlimiter.
With a contrast adjustment of 32 (gain+1) the signal
can be shifted by 100 %. After the brightness addition,
the negative going signals are limited to zero. It is
desirable to keep a small positive offset with the signal
to prevent undershoots produced by the peaking from
being cut. The digital brightness adjustment works
separately for main and side picture.
Part 2 has the same characteristics as part 1. The subtracting part is also relative to the input signal, so the
total differential gain will become negative if the sum of
slope 1 and slope 2 is greater than 16 and the input
signal is above the both tilt values (see characteristics).
2.10.5.Soft Limiter
Finally, the output signal of the soft limiter will be
clipped by a hard limiter adjustable from 256 to 511.
The dynamic range of the processed luma signal must
be limited to prevent the CRT from overload. An appropriate headroom for contrast, peaking and brightness
can be adjusted by the TV manufacturer according to
the CRT characteristics. All signals above this limit will
be ‘soft’-clipped. A characteristic diagram of the soft
limiter is shown in Fig. 2–15. The total limiter consists
of three parts:
Output
511
Part 1
Hard limiter
0
2
4
6
0
2
4
400
8
10
12
6
8
10
12
200
A linear phase interpolator is used to convert the
chroma sampling rate from 10.125 MHz (4:2:2) to
20.25 MHz (4:4:4). All further processing is carried out
at the full sampling rate.
Part 2
slope 1
[0...15]
300
2.10.6.Chroma Interpolation
range=
256...511
14
slope 2
[0...15]
14
tilt 2 [ 0...511]
0
0
100
200
300
400
500
600
Y Input
Black Level
Contrast
Dig. Brightness
BLE
Peaking
16...235 (ITUR)
16 (constant)
63
20
off
off
Limiter input signal:
(Yin-Black Level)⋅Contr./32 + Brightn.
(235-16) ⋅ 63/32 + 20 = 451
100
tilt 1 [ 0...511]
Calculation Example for the
Softlimiter Input Amplitude.
(The real signal processing in
the limiter is 2 bit more than
described here)
700
800
900
Limiter Input
1023
Fig. 2–15: Characteristic of soft limiter A and B and hard limiter
2.10.7.Chroma Transient Improvement
sharpened chroma signals are limited to a proper
value automatically.
The intention of this block is to enhance the chroma
resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be selected according to the signal bandwidth,
e.g. for PAL/NTSC/SECAM or digital component signals, respectively. The amplitude of the correction signal is adjustable. Small noise amplitudes in the correction signal are suppressed by an adjustable coring
circuit. To eliminate ‘wrong colors’, which are caused
by over and undershoots at the chroma transition, the
Micronas
21
VCT 38xxA
ADVANCE INFORMATION
2.10.9.RGB Processing
a)
After adding the post-processed luma, the digital RGB
signals are limited to 10 bits. Three multipliers are
used to digitally adjust the white drive. Using the same
multipliers an average beam current limiter is implemented (see Section 2.11.1. on page 25).
Cr in
Cb in
t
b)
The VCT 38xxA has five input lines for an OSD signal.
This signal forms a 5-bit address for a color look-up
table (CLUT). The CLUT is a memory with 32 words
where each word holds a RGB value.
Ampl.
t
c)
Cr out
Cb out
t
Fig. 2–16: Digital color transient improvement
2.10.8.Inverse Matrix
A 6-multiplier matrix transcodes the Cr and Cb signals
to R-Y, B-Y, and G-Y. The multipliers are also used to
adjust color saturation in the range of 0 to 2. The coefficients are signed and have a resolution of 9 bits.
There are separate matrix coefficients for main and
side pictures. The matrix computes:
R−Y= MR1*Cb+MR2*Cr
G−Y= MG1*Cb+MR2*Cr
B−Y= MB1*Cb+MR2*Cr
The initialization values for the matrix are computed
from the standard ITUR (CCIR) matrix:
=
1
1
1
0
−0.345
1.773
1.402
−0.713
0
Y
Cb
Cr
For a contrast setting of CTM+32, the matrix values
are scaled by a factor of 64 (see Table 2–4 on
page 34).
22
Bits 0 to 3 (bit 4=0) form the addresses for the ROM
part of the OSD, which generates full RGB signals (bit
0 to 2) and half-contrast RGB signals (bit 3).
Bit 4 addresses the RAM part of the OSD with 16
freely programmable colors, addressable with bit 0 to
3. The programming is done via the I2C bus.
a) CrCb input of DTI
b) CrCb input + correction signal
c) sharpened and limited CrCb
R
G
B
2.10.10.OSD Color Look-up Table
The amplitude of the CLUT output signals can be
adjusted separately for R, G, and B via the I2C bus.
The switchover between video RGB and OSD RGB is
done via the priority decoder.
2.10.11.Picture Frame Generator
When the picture does not fill the total screen (height
or width too small) it is surrounded with black areas.
These areas (and more) can be colored with the picture frame generator. This is done by switching over
the RGB signal from the matrix to the signal from the
OSD color look-up table.
The width of each area (left, right, upper, lower) can be
adjusted separately. The generator starts on the right,
respectively lower side of the screen and stops on the
left, respectively upper side of the screen. This means,
it runs during horizontal, respectively vertical flyback.
The color of the complete border can be stored in the
programmable OSD color look-up table in a separate
address. The format is 3 x 4-bit RGB. The contrast can
be adjusted separately.
The picture frame generator includes a priority master
circuit. Its priority is programmable and the border is
generated only if the priority is higher than the priority
of the other sources (video/OSD). Therefore, the border can be underlay or overlay depending on the picture source.
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2.10.12.Priority Decoder
2.10.13.Scan Velocity Modulation
The priority decoder selects the picture source
depending on the programmed priorities. Up to eight
levels can be selected for OSD and the picture frame –
where 0 is the highest. The video source always has
the lowest priority. A 5-bit information is attached to
each priority (see Table 2–4 on page 34). These bits
are programmable via the I2C bus and have the following meanings:
The RGB input signal of the SVM is converted to Y in a
simple matrix. Then the Y signal is differentiated by a
filter of the transfer function 1-Z-N, where N is programmable from 1 to 6. With a coring, some noise can be
suppressed. This is followed by a gain adjustment and
an adjustable limiter. The analog output signal is generated by an 8-bit D/A converter.
The signal delay can be adjusted by ±3.5 clocks in
half-clock steps. For the gain and filter adjustment
there are two parameter sets. The switching between
these two sets is done with the same RGB switch signal that is used for switching between video-RGB and
OSD-RGB for the RGB outputs (see Fig. 2–17).
– one of two contrast, brightness and matrix values for
main and side picture
– RGB from video signal or color look-up table
– disable/enable black-level expander
– disable/enable peaking transient suppression when
signal is switched
– disable/enable analog Fast-Blank input
R
G
B
Matrix and
Shaping
Modulation
Notch
RGB Switch
N1
N2
Differentiator
1-Z-Nx
Coring
Coring
adjustment
Gain1
Gain2
Gain
adjustment
Limit
Delay
Limiter
Delay
adjustment
D/A
Converter
Output
Fig. 2–17: SVM Block diagram
2.10.14.Display Phase Shifter
A phase shifter is used to partially compensate the
phase differences between the video source and the
flyback signal. By using the described clock system,
this phase shifter works with an accuracy of approximately 1 ns. It has a range of 1 clock period which is
equivalent to ±24.7 ns at 20.25 MHz. The large
amount of phase shift (full clock periods) is realized in
the front-end circuit.
Micronas
23
Dynamic
peaking
CLOCK
prio
dig.
Y in
Softlimiter
8
luma insert
for CRTmeasurement
5
CLUT,
Contrast
BlackLevel
Expander
Matrix
R’
prio
Cr
White-Drive R
x beam Curr. Lim.
PRIO
Decoder
select
Coefficients
10
dig.
Gout
10
G
White-Drive
x Beam Curr. Lim.
Matrix
B’
Phase
Shift
0...1 Clock
dig.
Bout
10
B
Main Picture
Scan
Velocity
Modulation
Micronas
Matrix
Saturation
SVMout
ADVANCE INFORMATION
PRIO in
Phase
Shift
0...1 Clock
DTI
(Cb)
Side Picture
dig.
Rout
White-Drive G
x Beam curr. Lim.
Matrix
G’
Cb
Horizontal
Flyback
R
DTI
(Cr)
Interpol
4:4:4
3
& Clock
Control
Phase
Shift
0...1 Clock
8
dig.
CrCb in
Display
Picture
Frame
Generator
Y
dig. OSD in
Blanking
for CRT Measurement
VCT 38xxA
Fig. 2–18: Digital back-end
24
White-Drive
Measurement
Brightness
+ Offset
Contrast
VCT 38xxA
ADVANCE INFORMATION
2.11.Video Back-end
Cutoff and white-drive current measurement are carried out during the vertical blanking interval. They
always use the small bandwidth setting. The current
range for the cutoff measurement is set by connecting
a sense resistor to the MADC input. For the white-drive
measurement, the range is set by using another sense
resistor and the range select switch 2 output pin
(RSW2). During the active picture, the minimum and
maximum beam current is measured. The measurement range can be set by using the range select
switch 1 pin (RSW1) as shown in Fig. 2–19 and Fig. 2–
20. The timing window of this measurement is programmable. The intention is, to automatically detect
letterbox transmission or to measure the actual beam
current. All control loops are closed via the external
control microprocessor.
The digital RGB signals are converted to analog RGBs
using three video digital-to-analog converters (DAC)
with 10-bit resolution. An analog brightness value is
provided by three additional DACs. The adjustment
range is 40 % of the full RGB range.
Controlling the white-drive/analog brightness and also
the external contrast and brightness adjustments is
done via the Fast Processor, located in the front-end.
Control of the cutoff DACs is done via I2C bus registers.
Finally cutoff and blanking values are added to the
RGB signals. Cutoff (dark current) is provided by three
9-bit DACs. The adjustment range is 60 % of full scale
RGB range.
Beam Current
The analog RGB-outputs are current outputs with current-sink characteristics. The maximum current drawn
by the output stage is obtained with peak white RGB.
An external half contrast signal can be used to reduce
the output current of the RGB outputs to 50 %.
A
D
MADC
SENSE
RSW1
R2
RSW2
R3
2.11.1.CRT Measurement and Control
The display processor is equipped with an 8-bit
PDM-ADC for all measuring purposes. The ADC is
connected to the SENSE input pin, the input range is 0
to 1.5V. The bandwidth of the PDM filter can be
selected; it is 40/80 kHz for small/large bandwidth setting. The input impedance is more than 1 MΩ.
R1
Fig. 2–19: MADC range switches
CR + IBRM + WDRV⋅WDR
CR + IBRM
white
drive
R
cutoff
R
black
ultra black
R
CG + IBRM
cutoff
G
CB + IBRM
active measurement resistor
R1||R2||R3
R1
RSW1=on, RSW2=on
PICTURE MEAS.
Lines
PMSO
G
cutoff
B
B
R1||R3
R1||R2||R3
RSW2
=on
RSW1=on, RSW2=on
TUBE MEASUREMENT
TML
PICTURE MEAS.
PMST
Fig. 2–20: MADC measurement timing
Micronas
25
VCT 38xxA
ADVANCE INFORMATION
In each field two sets of measurements can be taken:
tube measurement
picture meas. start
a) The picture tube measurement returns results for
– cutoff R
– cutoff G
active video
field 1/ 2
– cutoff B
picture meas. end
– white-drive R or G or B (sequentially)
b) The picture measurement returns data on
– active picture maximum current
small window for tube
measurement (cutoff, white drive)
– active picture minimum current
large window for active picture
The tube measurement is automatically started when
the cutoff blue result register is read. Cutoff control for
RGB requires one field only, whereas a complete
white-drive control requires three fields. If the measurement mode is set to ‘offset check’, a measurement
cycle is run with the cutoff/white-drive signals set to
zero. This allows to compensate the MADC offset as
well as input the leakage currents. During cutoff and
white-drive measurements, the average beam current
limiter function (see Section 2.11.3. on page 27) is
switched off and a programmable value is used for the
brightness setting. The start line of the tube measurement can be programmed via I2C bus, the first line
used for the measurement, i.e. measurement of cutoff
red, is 2 lines after the programmed start line.
The picture measurement must be enabled by the control microprocessor after reading the min./max. result
registers. If a ‘1’ is written into bit 2 in subaddress 25,
the measurement runs for one field. For the next measurement a ‘1’ has to be written again. The measurement is always started at the beginning of active video.
picture meas. start
Fig. 2–21: Windows for tube and picture measurements
2.11.2.SCART Output Signal
The RGB output of the VCT 38xxA can also be used to
drive a SCART output. In the case of the SCART signal, the parameter CLMPR (clamping reference) has to
be set to 1. Then, during blanking, the RGB outputs
are automatically set to 50 % of the maximum brightness. The DC offset values can be adjusted with the
cutoff parameters CR, CG, and CB. The amplitudes
can be adjusted with the drive parameters WDR,
WDG, and WDB.
The vertical timing for the picture measurement is programmable, and may even be a single line. Also the
signal bandwidth is switchable for the picture measurement.
Two horizontal windows are available for the picture
measurement. The large window is active for the entire
active line. Tube measurement is always carried out
with the small window. Measurement windows for picture and tube measurement are shown in Fig. 2–21.
26
Micronas
VCT 38xxA
ADVANCE INFORMATION
2.11.3.Average Beam Current Limiter
2.11.4.Analog RGB Insertion
The average beam current limiter (BCL) uses the
SENSE input for the beam current measurement. The
BCL uses a different filter to average the beam current
during the active picture. The filter bandwidth is
approx. 2 kHz. The beam current limiter has an automatic offset adjustment that is active two lines before
the first cutoff measurement line.
The VCT 38xxA allows insertion of external analog
RGB signals. The RGB signal is key-clamped and
inserted into the main RGB by the Fast-Blank switch.
The external RGB input can be overlaid or underlaid to
the digital picture. The external RGB signals can be
adjusted independently as regards DC level (brightness) and magnitude (contrast).
The beam current limiter function is located in the
front-end. The data exchange between the front-end
and the back-end is done via a single-wire serial interface.
All signals for analog RGB insertion (RIN, GIN, BIN,
FBLIN) must be synchronized to the horizontal flyback,
otherwise a horizontal jitter will be visible. The
VCT 38xxA has no means for timing correction of the
analog RGB input signals.
The beam current limiter allows the setting of a threshold current. If the beam current is above the threshold,
the excess current is low-pass filtered and used to
attenuate the RGB outputs by adjusting the white-drive
multipliers for the internal (digital) RGB signals, and
the analog contrast multipliers for the analog RGB
inputs, respectively. The lower limit of the attenuator is
programmable, thus a minimum contrast can always
be set. During the tube measurement, the ABL attenuation is switched off. After the white-drive measurement line it takes 3 lines to switch back to BCL limited
drives and brightness.
Typical characteristics of the ABL for different loop
gains are shown in Fig. 2–22; for this example the tube
has been assumed to have square law characteristics.
2.11.5.Fast-Blank Monitor
The presence of external analog RGB sources can be
detected by means of a Fast-Blank monitor. The status
of the Fast-Blank input can be monitored via an I2C
bus register. There is a 2 bit information, giving static
and dynamic indication of a Fast-Blank signal. The
static bit is directly reading the Fast-Blank input line,
whereas the dynamic bit is reading the status of a
flip-flop triggered by the negative edge of the FastBlank signal.
With this monitor logic it is possible to detect if there is
an external RGB source active and if it is a full screen
insertion or only a box. The monitor logic is connected
directly to the FBLIN pin.
Fig. 2–22: Beam current limiter characteristics:
beam current output vs. drive
BCL threshold: 1
Micronas
27
VCT 38xxA
digital
SVM in
8
ADVANCE INFORMATION
8-bit
DAC
SVM
1.88 mA
analog
SVM out
10-bit
DAC
Video
3.75 mA
int. brightness *
white drive B
10
digital
B in
10
9-bit
DAC
2.2 mA
blanking
750 µA
9 bit
DAC
2.2 mA
blanking
750 µA
9 bit
DAC
2.2 mA
blanking
750 µA
analog
R out
9-bit
DAC
1.5 mA
cutoff G
digital
G in
cutoff R
10-bit
DAC
Video
3.75 mA
int. brightness *
white drive G
10
9-bit
DAC
1.5 mA
9-bit
DAC
1.5 mA
cutoff B
digital
R in
int. brightness *
white drive R
0.94 mA
10-bit
DAC
Video
3.75 mA
analog
G out
analog
B out
9-bit
DAC
1.5 mA
blank &
measurem.
timing
9-bit
DAC
1.5 mA
ext. brightness
key
9-bit
U/I-DAC
3.75 mA
ext. contrast *
white drive B *
beam current lim.
ext. contrast
9-bit
U/I-DAC
3.75 mA
ext. contrast *
white drive G *
beam current lim.
int . brightness
ext. contrast *
white drive R *
beam current lim.
white drive G
white drive B
9-bit
U/I-DAC
3.75 mA
clamp
clamp
clamp
analog
analog
G in
analog
B in
R in
V
fast
blank in
8 bit
ADC
measurm.
measurement
buffer
white drive R
9-bit
DAC
1.5 mA
ext. brightness *
white drive B
serial interface
ext. brightness *
white drive G
ext. brightness *
white drive R
H
SENSE
Input
I/O
Fig. 2–23: Video back-end
28
Micronas
ADVANCE INFORMATION
VCT 38xxA
2.12.Synchronization and Deflection
2.12.3.Horizontal Phase Adjustment
The synchronization and deflection processing is distributed over front-end and back-end. The video
clamping, horizontal and vertical sync separation and
all video related timing information are processed in
the front-end. Most of the processing that runs at the
horizontal frequency is programmed on the internal
Fast Processor (FP). Also the values for vertical and
East/West deflection are calculated by the FP software.
This section describes a simple way to align PLL
phases and the horizontal frame position.
The generation of horizontal and vertical drive signals
can be synchronized to the video timing extracted in
the front-end or to a free running line counter in the
back-end.
2.12.1.Deflection Processing
The deflection processing generates the signals for the
horizontal and vertical drive (see Fig. 2–24). This block
contains two phase-locked loops:
– PLL2 generates the horizontal and vertical timing,
e.g. blanking, clamping and composite sync. Phase
and frequency are synchronized by the front sync
signal.
– PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal output stage. Phase and frequency are synchronized
by the oscillator signal of PLL2.
1. With HDRV the duration of the horizontal drive pulse
has to be adjusted
2. With POFS2 the delay between input video and display timing (e.g. clamping pulse for analog RGB)
has to be adjusted
3. With CSYDEL the delay between video and analog
RGB (OSD) has to be adjusted.
4. With CSYDEL and HPOS the horizontal position of
both, the digital and analog RGB signal (from
SCART) relative to the clamping pulse has to be
adjusted to the correct position, e.g. the pedestal of
the generator signal.
5. With POFS3 the position of horizontal drive/flyback
relative to RGB has to be adjusted
6. With NEWLIN the position of a scaled video picture
can be adjusted (left, middle, center, etc; versions
with panorama scaler only).
7. With HBST and HBSO, the start and stop values for
the horizontal blanking have to be adjusted.
Note: The processing delay of the internal digital video
path differs depending on the comb filter option of the
VCT 38xxA. The versions with comb filter have an
additional delay of 34 clock cycles.
The horizontal drive circuitry uses a digital sine wave
generator to produce the exact (subclock) timing for
the drive pulse HOUT. The generator runs at 1 MHz.
Under control of the EHPLL bit and the internal voltage
supervision it is either synchronized by the deflection
PLL or it is free running. In the output stage the frequency is divided down to give drive-pulse period and
width. The drive pulse width is programmable. The
horizontal drive uses an open drain output transistor.
After power on or during reset the HOUT generation is
switched to a free running mode with a fix duty cycle of
50 %. For normal operation the EHPLL bit has to be
set first. During the switch the actual period of HOUT
can vary by up to 1 µs.
2.12.2.Angle and Bow Correction
The Angle and Bow correction is part of the horizontal
drive PLL. This feature allows a shift of the horizontal
drive pulse phase depending on the vertical position
on the screen. The phase correction has a linear
(angle) and a quadratic term (bow).
Micronas
29
VCT 38xxA
ADVANCE INFORMATION
HFLB
PLL3
Skew
Measurement
Phase
Comparator
&
Low-pass
DCO
+
Angle &
Bow
Sinewave DAC
Generator &
LPF
1:64
&
Output
Stage
HOUT
blanking, clamping, etc.
MSY
FSY
Main
Sync
Generator
Display
Timing
Front
Sync
Interface
Phase
Comparator
&
Low-pass
PLL2
DCO
vertical reset
VDATA
Sync
Generation
INTLC
Clock & Control
VPROT
Line
Counter
E/W
correction
PWM
15-bit
Sawtooth
PWM
15-bit
EW
Vertical
Data
VERT
VERTQ
Fig. 2–24: Deflection processing block diagram
2.12.4.Vertical and East/West Deflection
The calculations of the vertical and East/West deflection waveforms is done by the internal Fast Processor
(FP). The algorithm uses a chain of accumulators to
generate the required polynomial waveforms. To produce the deflection waveforms, the accumulators are
initialized at the beginning of each field. The initialization values must be computed by the TV control processor and are written to the front-end once. The
waveforms are described as polynomials in x, where x
varies from 0 to 1 for one field.
P: a + b(x-0.5) + c(x-0.5)2 + d(x-0.5)3 + e(x-0.5)4
In order to get a faster vertical retrace timing, the output impedance of the vertical D/A-converter can be
reduced by 50 % during the retrace.
2.12.5.EHT Compensation
The vertical waveform can be scaled according to the
average beam current. This is used to compensate the
effects of electric high-tension changes due to beam
current variations. EHT compensation for East/West
deflection is done with an offset corresponding to the
average beam current.
The initialization values for the accumulators a0..a3 for
vertical deflection and a0..a4 for East/West deflection
are 12-bit values.
Fig. 2–25 shows several vertical and East/West deflection waveforms. The polynomial coefficients are also
stated.
30
Micronas
VCT 38xxA
ADVANCE INFORMATION
2.12.6.Protection Circuitry
Picture tube and drive stage protection is provided
through the following measures:
– Vertical flyback protection input:
This pin searches for a negative edge in every field,
otherwise the RGB drive signals are blanked.
– Drive shutoff during flyback:
This feature can be selected by software.
– Safety input pin:
This input has two thresholds. Between zero and the
lower threshold, normal functioning takes place.
Between the lower and the higher threshold, the
RGB signals are blanked. Above the higher threshold, the RGB signals are blanked and the horizontal
drive is shut off. Both thresholds have a small hysteresis.
Vertical:
a,b,c,d
0,1,0,0
0,1,1,0
0,1,0,1
East/West:
a,b,c,d,e
0,0,1,0,0
0,0,0,0,1
0,0,1,1,1
Fig. 2–25: Vertical and East/West deflection waveforms
2.13.Reset Function
Reset of all VDP functions is performed by the RESQ
pin. When this pin becomes active, all internal registers and counters are lost. The TV controller can activate the RESQ pin by software (see Section 5.7.2. on
page 90).
When the RESQ pin is released, the internal reset is
still active for 4 µs. After that time, the initialization of
all required registers is performed by the internal Fast
Processor. This takes approximately 60 µs. During this
initialization procedure it is not possible to access the
VDP via the I2C interface.
for the digital circuits (VSUPD) goes below ~2.5 V for
more than 50 ns. This reset signal is extended by
50 µs after VSUPD is back again.
2.14.Standby and Power-On
The VDP does not have a standby mode. To disable all
the analog and digital video functions, it is necessary
to switch off the supplies for analog front-end
(VSUPAF), analog back-end (VSUPAB) and digital
circuitry (VSUPD).
The VDP has clock and voltage supervision circuits to
generate a stable HOUT signal. The voltage supervision activates an internal reset signal when the supply
Micronas
31
VCT 38xxA
ADVANCE INFORMATION
2.15.I2C Bus Slave Interface
Communication between the VDP and the TV controller is done via I2C bus. For detailed information on the
I2C bus please refer to the Philips manual ‘I2C bus
Specification’.
The VDP has two I2C bus slave interfaces (for compatibility with VPC/DDP applications) − one in the
front-end and one in the back-end. Both I2C bus interfaces use I2C clock synchronization to slow down the
interface if required. Both I2C bus interfaces use one
level of subaddress: the I2C bus chip address is used
to address the VDP and a subaddress selects one of
the internal registers. The I2C bus chip addresses are
given below:
Fig. 2–26 shows I2C bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip
address with read command set.
2.15.1.Control and Status Registers
Table 2–3 gives definitions of the VDP control and status registers. The number of bits indicated for each
register in the table is the number of bits implemented
in hardware, i.e. a 9-bit register must always be
accessed using two data bytes but the 7 MSB will be
‘don’t care’ on write operations and ‘0’ on read operations. Write registers that can be read back are indicated in Table 2–3.
Functions implemented by software in the on-chip control microprocessor (FP) are explained in Table 2–5.
Table 2–2: I2C chip addresses
Chip
Address
A6
A5
A4
A3
A2
A1
A0
R/W
front-end
1
0
0
0
1
1
1
1/0
back-end
1
0
0
0
1
0
1
1/0
The registers of the VDP have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
A hardware reset initializes all control registers to 0.
The automatic chip initialization loads a selected set of
registers with the default values given in Table 2–3.
The register modes given in Table 2–3 are
– w:
write only register
– w/r:
write/read data register
– r:
read data from VDP
– v:
register is latched with vertical sync
– h:
register is latched with horizontal
S
1000 111
W Ack
0111 1100
Ack 1 or 2 byte Data
S
1000 111
W Ack
0111 1100
Ack S
1000 111
I2C write access
subaddress 7c
P
R
low byte Data
1
0
SDA
S
SCL
P
I2C read access
subaddress 7c
high byte Data Ack
W
R
Ack
Nak
S
P
Nak P
=
=
=
=
=
=
0
1
0
1
Start
Stop
Fig. 2–26: I2C bus protocols
32
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 2–3: I2C control and status registers of the video front-end
I2C Sub
address
Number
of bits
Mode
Function
Default
Name
FP Interface
h’35
8
r
FP status
bit [0]
bit [1]
bit [2]
write request
read request
busy
FPSTA
h’36
16
w
bit[8:0]
bit[11:9]
9-bit FP read address
reserved, set to zero
FPRD
h’37
16
w
bit[8:0]
bit[11:9]
9-bit FP write address
reserved, set to zero
FPWR
h’38
16
w/r
bit[11:0]
FP data register, reading/writing to this
register will autoincrement the FP read/
write address. Only 16 bit of data are
transferred per I2C telegram.
FPDAT
Black Line Detector
h’12
16
r
read only register, do not write to this register!
after reading, LOWLIN and UPLIN are reset to 127 to start a
new measurement
bit[6:0]
number of lower black lines
bit[7]
always 0
bit[14:8]
number of upper black lines
bit[15]
normal/black picture
BLKLIN
LOWLIN
UPLIN
BLKPIC
Miscellaneous
h’29
h’22
Micronas
16
16
w/r
w/r
Test pattern generator:
bit[10:0]
reserved (set to 0)
bit[11]
0/1
disable/enable test pattern generator
bit[13:12]
output mode:
00
Y/C = ramp (240 ... 17)
01
Y/C = 16
10
Y/C = 90
11
Y/C = 240
bit[15:14] 0/1
reserved (set to 0)
NEWLINE (available for versions with panorama scaler only):
bit[10:0]
NEWLINE register
This register defines the readout start of
the next line in respect to the value of the
sync counter.
bit [15:11]
reserved (set to 0)
TPG
0
0
0
TPGEN
TPGMODE
0
NEWLIN
0
33
VCT 38xxA
ADVANCE INFORMATION
Table 2–4: I2C control and status registers of the video back-end
I2C Sub
address
Number
of bits
Mode
Function
Default
Name
1)
priority mask register
If bit[x] is set to 1 then the function is active for the respective signal priority
Luminance Channel
h’61
9
wv
bit [5:0]
0..63/32
main picture contrast
32 CTM
h’65
9
wv
bit [5:0]
0..63/32
side picture contrast
32 CTS
h’51
9
wv
bit [8:0]
−256..255
main picture brightness
0 BRM
h’55
9
wv
bit [8:0]
−256..255
side picture brightness
0 BRS
h’75
9
wv
luma channel, priority mask register
bit [7:0]
0/1
select contrast, brightness, matrix
for main/side picture
0 PBCT 1)
h’71
9
wv
luma channel, priority mask register
bit [7:0]
0/1
select main (video) / external (via CLUT)
RGB
0 PBERGB 1)
Black-Level Expander
h’59
9
wv
black-level expander
bit [3:0]
0..15
bit [8:4]
0...31
tilt coefficient
amount
BLE1
8 BTLT
12 BAM
h’5d
9
wv
black-level expander, threshold:
bit [8:0]
0..511
disable expansion, threshold value
BLE2
200 BTHR
h’73
9
wv
black-level expander, measurement
bit[0]
0/1
50/60 Hz measurement windowlength
bit [8:1]
0..255 vstart/2
start line = vstart
stop line = 336/283 − vstart
or vertical blanking
BLE3
0 BWL
15 BVST
h’7d
9
wv
black-level expander, priority mask register
bit [7:0]
0/1
enable/disable black-level expander
0 PBBLE 1)
Dynamic Peaking
h’69
h’6d
h’79
34
9
9
9
wv
wv
wv
luma peaking filter, the gain at high frequencies and small signal
amplitudes is: 1 + (k1+k2)/8
bit [3:0]
0..15
k1: peaking level undershoot
bit [7:4]
0..15
k2: peaking level overshoot
bit [8]
0/1
peaking value normal/inverted
(peaking/softening)
PK1
4 PKUN
4 PKOV
0 PKINV
luma peaking filter, coring
bit [4:0]
0..31
coring level
bit [7:5]
reserved
bit [8]
0/1
peaking filter center frequency high/
low
PK2
3 COR
luma peaking filter, priority mask register
bit [7:0]
0/1
disable/enable peaking transient
suppression when signal is switched
0 PBPK 1)
0 PFS
Micronas
VCT 38xxA
ADVANCE INFORMATION
I2C Sub
address
Number
of bits
Mode
Function
Default
Name
Soft Limiter
h’41
9
wv
luma soft limiter, slope A and B
bit [3:0]
slope segment A
bit [7:4]
slope segment B
LSL1
0 LSLSA
0 LSLSB
h’45
9
wv
luma soft limiter, absolute limit
bit [7:0]
luma soft limiter absolute limit
(unsigned)
bit [8]
0/1
modulation off/on
LSL2
255 LSLAL
1 LSLM
h’49
9
wv
bit [8:0]
luma soft limiter segment B tilt point (unsigned)
300 LSLTB
h’4d
9
wv
bit [8:0]
luma soft limiter segment A tilt point (unsigned)
250 LSLTA
Chrominance Channel
h’14
8
w/r
luma/chroma matching
bit [2:0]
−3...3 variable chroma delay
bit [7:3]
reserved, set to 0
LCM
0 CDEL
h’5e
9
wv
digital transient improvement
bit [3:0]
0..15
coring value
bit [7:4]
0..15
DTI gain
bit [8]
0/1
narrow/wide bandwidth mode
DTI
1 DTICO
5 DTIGA
1 DTIMO
Inverse Matrix
h’7c
h’74
9
9
wv
wv
main picture matrix coefficient R−Y = MR1M*CB + MR2M*CR
bit [8:0]
−256/128 ... 255/128
−256/128 ... 255/128
bit [8:0]
0 MR1M,
86 MR2M
h’6c
h’64
9
9
wv
wv
main picture matrix coefficient G−Y = MG1M*CB + MG2M*CR
bit [8:0]
−256/128 ... 255/128
−256/128 ... 255/128
bit [8:0]
−22 MG1M,
−44 MG2M
h’5c
h’54
9
9
wv
wv
main picture matrix coefficient B−Y = MB1M*CB + MB2M*CR
bit [8:0]
−256/128 ... 255/128
−256/128 ... 255/128
bit [8:0]
113 MB1M,
0 MB2M
h’78
h’70
9
9
wv
wv
side picture matrix coefficient R−Y = MR1S*CB + MR2S*CR
bit [8:0]
−256/128 ... 255/128
−256/128 ... 255/128
bit [8:0]
0 MR1S,
73 MR2S
h’68
h’60
9
9
wv
wv
side picture matrix coefficient G−Y = MG1S*CB + MG2S*CR
bit [8:0]
−256/128 ... 255/128
−256/128 ... 255/128
bit [8:0]
−19 MG1S,
−37 MG2S
h’58
h’50
9
9
wv
wv
side picture matrix coefficient B−Y = MB1S*CB + MB2S*CR
bit [8:0]
−256/128 ... 255/128
−256/128 ... 255/128
bit [8:0]
97 MB1S,
0 MB2S
Micronas
35
VCT 38xxA
I2C Sub
address
Number
of bits
ADVANCE INFORMATION
Mode
Function
Default
Name
Color Lookup Table
h’00−
h’0f
16
wh
color look-up table : 16 entries, 12 bit wide,
The CLUT registers are initialized at power-up
bit [3:0]
0..15
blue amplitude
bit [7:4]
0..15
green amplitude
bit [11:8]
0..15
red amplitude
h’4c
9
wv
digital OSD insertion contrast for R (amplitude range: 0 to 255)
bit [3:0]
0..13
R amplitude = CLUTn ⋅ (DRCT + 4)
14,15 invalid
picture frame insertion contrast for R (ampl. range: 0 to 255)
bit [7:4]
0..13
R amplitude = PFCR ⋅ (PFRCT + 4)
14,15 invalid
RCT
8 DRCT
digital OSD insertion contrast for G (amplitude range: 0 to 255)
bit [3:0]
0..13
G amplitude = CLUTn ⋅ (DGCT + 4)
14,15 invalid
picture frame insertion contrast for G (ampl. range: 0 to 255)
bit [7:4]
0..13
G amplitude = PFCG ⋅ (PFGCT + 4)
14,15 invalid
GCT
8 DGCT
digital OSD insertion contrast for B (amplitude range: 0 to 255)
bit [3:0]
0..13
B amplitude = CLUTn ⋅ (DBCT + 4)
14,15 invalid
picture frame insertion contrast for B (ampl. range: 0 to 255)
bit [7:4]
0..13
B amplitude = PFCB ⋅ (PFBCT + 4)
14,15 invalid
BCT
8 DBCT
h’48
h’44
9
9
wv
wv
000h CLUT0
f00h
0f0h
ff0h
00fh
f0fh
0ffh
fffh
7ffh
700h
070h
770h
007h
707h
077h
777h CLUT15
8 PFRCT
8 PFGCT
8 PFBCT
Picture Frame Generator
h’11
36
16
wh
picture frame color
bit [3:0]
0..15
bit [7:4]
0..15
bit [11:8]
0..15
blue amplitude
green amplitude
red amplitude
picture frame generator priority id
enable prio id for picture frame generator
PFC
0 PFCB
0 PFCG
0 PFCR
h’47
9
wv
bit [2:0]
bit [8]
0 PFGID
PFGEN
h’4F
9
wv
bit [8:0] horizontal picture frame begin
code 0 = picture frame generator horizontally disabled
code 1FF = full frame
0 PFGHB
h’53
9
wv
bit [8:0] horizontal picture frame end
0 PFGHE
h’63
9
wv
bit [8:0] vertical picture frame begin
code 0 = picture frame generator vertically disabled
h’6f
9
wv
bit [8:0] vertical picture frame end
270 PFGVB
56 PFGVE
Micronas
VCT 38xxA
ADVANCE INFORMATION
I2C Sub
address
Number
of bits
Mode
Function
Default
Name
Scan Velocity Modulation
h’5a
9
wv
video mode coefficients
bit [5:0]
gain1
bit [8:6]
differentiator delay 1 (0= filter off, 1...6= delay)
SVM1
60 SVG1
4 SVD1
h’56
9
wv
text mode coefficients
bit [5:0]
gain 2
bit [8:6]
differentiator delay 2 (0= filter off, 1...6= delay)
SVM2
60 SVG2
4 SVD2
h’52
9
wv
limiter
bit [6:0]
bit [8:5]
h’4e
9
wv
limit value
not used, set to “0”
delay and coring
bit [3:0]
adjustable delay, in 1/2 display clock steps,
(value 5 : delay of SVMOUT is the same as for
RGBOUT
bit [7:4]
coring value
bit [8]
not used, set to “0”
SVM3
100 SVLIM
0
SVM4
7 SVDEL
0 SVCOR
Display Controls
h’4a
h’46
h’42
9
9
9
wv
wv
wv
cutoff Red
cutoff Green
cutoff Blue
0 CR
0 CG
0 CB
Tube- and Picture-Measurements
h’7b
h’6b
h’7f
h’25
h’13
Micronas
9
9
9
8
16
wv
wv
wv
w/r
w/r
picture measurement start line
bit [8:0]
(TML+9)..511
first line of picture measurement
23
picture measurement stop line
bit [8:0]
(PMST+1)..511 last line of picture measurement
308
tube measurement line
bit [8:0]
0..511 start line for tube measurement
tube and picture measurement control
bit [0]
0/1
disable/enable tube measurement
bit [1]
0/1
80/40 kHz bandwidth for
picture measurement
bit [2]
0/1
disable/enable picture measurement
(writing a ’1’ starts one measurement
cycle)
bit [3]
0/1
large/small picture measurement window,
will be disabled from bit[3] in address h’32
bit [4]
0/1
measure / offset check for adc
bit [7:5]
reserved
white drive measurement control
bit [9:0]
0..1023 RGB values for white drive beam current
measurement
bit [10]
reserved
bit [11]
0/1
RGB values for white drive beam current
measurement disabled/enabled
PMST
PMSO
TML
15
0 TPM
TMEN
PMBW
PMEN
PMWIN
OFSEN
WDM
512 WDRV
0 EWDM
37
VCT 38xxA
I2C Sub
address
Number
of bits
8
ADVANCE INFORMATION
Mode
r
h’18
h’19
h’1a
h’1d
h’1c
h’1b
h’1e
8
r
Function
Default
Name
measurement result registers
minimum in active picture
maximum in active picture
white drive
cutoff/leakage red
cutoff/leakage green
cutoff/leakage blue,
read pulse starts tube measurement
−
measurement adc status and Fast-Blank input status
− PMS
MRMIN
MRMAX
MRWDR
MRCR
MRCG
MRCB
measurement status register
bit [0]
0/1
tube measurement active / complete
bit [2:1]
white drive measurement cycle
00
red
01
green
10
blue
11
reserved
bit [3]
0/1
picture measurement active / complete
bit [4]
0/1
Fast-Blank input Low / High (static)
bit [5]
1
Fast-Blank input negative transition since
last read (bit reset at read)
bit [7:6]
reserved
Vertical Timing
h’67
h’77
h’5f
9
9
9
wv
wv
wv
vertical blanking start
bit [8:0]
0..511 first line of vertical blanking
305
VBST
vertical blanking stop
bit [8:0]
0..511 last line of vertical blanking
25
vertical free run period
bit [8:0] free running field period = (value+4) lines
309
VBSO
VPER
Horizontal Deflection and Timing
38
h’7a
9
wv
quadratic term of angle & bow correction
bit [8:0]
−256..+255
(± 500 ns)
0 BOW
h’76
9
wv
linear term of angle & bow correction
bit [8:0]
−256..+255
(± 500 ns)
0 ANGLE
h’6e
9
wv
adjustable delay of PLL2, clamping, and blanking (relative to
front sync)
adjust clamping pulse for analog RGB input
bit [8:0]
−256..+255
(± 8 µs)
h’72
9
wv
adjustable delay of flyback, main sync, csync and analog RGB
(relative to PLL2)
adjust horizontal drive or csync
−256..+255
(± 8 µs)
bit [8:0]
h’7e
9
wv
adjustable delay of main sync (relative to flyback)
adjust horizontal position for digital picture
bit [8:0]
20 steps=1 µs
h’5b
9
wv
start of horizontal blanking
bit [8:0]
0..511
−141 POFS2
0 POFS3
120 HPOS
1 HBST
Micronas
VCT 38xxA
ADVANCE INFORMATION
I2C Sub
address
Number
of bits
h’57
9
wv
h’62
h’66
h’6a
9
9
9
wv
wv
wv
h’15
16
w/r
h’9d
8
Mode
w/r
Function
Default
end of horizontal blanking
bit [8:0]
0..511
PLL2/3 filter coefficients, 1of5 bit code (n+ set bit number)
bit [5:0]
proportional coefficient PLL3, 2−n−1
bit [5:0]
proportional coefficient PLL2, 2−n−1
bit [5:0]
integral coefficient PLL2, 2−n−5
horizontal drive and vertical signal control register
bit [5:0]
0..63
horizontal drive pulse duration in µs
(internally limited to 4..61)
bit [6]
0/1
disable/enable horizontal PLL2 and PLL3
bit [7]
0/1
1: disable horizontal drive pulse during
flyback
bit [8]
reserved, set to ’0’
bit [9]
0/1
enable/disable ultra black blanking
bit [10]
0/1
0: all outputs blanked
1: normal mode
bit [11]
0/1
enable/disable clamping for analog RGB
input
bit [12]
0/1
disable/enable vertical free running mode
(FIELD is set to field2, no interlace)
bit [13]
0/1
enable/disable vertical protection
bit [14]
reserved, set to ’0’
bit [15]
0/1
disable/enable phase shift of display clock
sync output control
bit [0]
invert INTLC
bit [4:1]
reserved, set to ’0’
bit [5]
force INTLC to polarity defined in ‘INTLCINV’
Name
48 HBSO
2 PKP3
1 PKP2
2 PKI2
HVC
32 HDRV
0 EHPLL
0 EFLB
0
0 DUBL
1 EBL
0 DCRGB
0 SELFT
0 DVPR
0
1 DISKA
0 SYCTRL
INTLCINV
INTLCFO
Miscellaneous
h’32
h’4b
Micronas
8
9
w/r
wv
Fast-Blank interface mode
bit [0]
0
internal Fast-Blank from FBLIN pin
1
force internal Fast-Blank signal to High
bit [1]
0/1
internal Fast-Blank active High/Low
bit [2]
0/1
disable/enable clamping reference for
RGB outputs
bit [3]
1
full line MADC measurement window,
disables bit [3] in address h’25
bit [4]
0/1
horizontal flyback input active High/Low
bit [6:5]
reserved (set to 0)
bit [7]
vertical output select
0
VERTQ output
1
INTLC output
0 FBMOD
FBFOH
Fast-Blank input, priority mask register
bit [7:0]
0/1
disable/enable analog Fast-Blank input
0 PBFB 1)
FBPOL
CLMPR
FLMW
FLPOL
VOS
39
VCT 38xxA
ADVANCE INFORMATION
Table 2–5: Control registers of the Fast Processor for control of the video front-end functions
− default values are initializied at reset
FP Subaddress
Function
Default
Name
Standard Selection
h’20
Standard select:
bit[2:0]
standard
0
PAL B,G,H,I (50 Hz)
4.433618
1
NTSC M
(60 Hz)
3.579545
2
SECAM
(50 Hz)
4.286
3
NTSC44
(60 Hz)
4.433618
4
PAL M
(60 Hz)
3.575611
5
PAL N
(50 Hz)
3.582056
6
PAL 60
(60 Hz)
4.433618
7
NTSC COMB (60 Hz)
3.579545
bit[3]
0/1 standard modifier
PAL modified to simple PAL
NTSC modified to compensated NTSC
SECAM modified to monochrome 625
NTSCC modified to monochrome 525
bit[4]
reserved (set to 0)
bit[5]
0/1 2-H comb filter off/on
bit[6]
0/1 S-VHS mode off/on (2-H comb is switched off)
0
PAL
NTSC
SECAM
NTSC44
PALM
PALN
PAL60
NTSCC
SDTMOD
COMB
SVHS
Option bits allow to suppress parts of the initialization, this can be used
for color standard search:
h’148
bit[7]
bit[8]
bit[9]
bit[10]
no hpll setup
no vertical setup
no acc setup
2-H comb filter set-up only
bit[11]
status bit, normally write 0. After the FP has switched to a
new standard, this bit is set to 1 to indicate operation
complete. Standard is automatically initialized when the
insel register is written.
Enable automatic standard recognition (ASR)
bit[0]
0/1 PAL B,G,H,I
(50 Hz)
4.433618
bit[1]
0/1 NTSC M
(60 Hz)
3.579545
bit[2]
0/1 SECAM
(50 Hz)
4.286
bit[3]
0/1 NTSC44
(60 Hz)
4.433618
bit[4]
0/1 PAL M
(60 Hz)
3.575611
bit[5]
0/1 PAL N
(50 Hz)
3.582056
bit[6]
0/1 PAL 60
(60 Hz)
4.433618
bit[10:7] reserved set to 0
bit[11]
1
reset status information ‘switch’ in asr_status
(cleared automatically)
SDT
SDTOPT
0
ASR_ENA
0: disable recognition; 1: enable recognition
Note: For correct operation don’t change FP reg. 20h and 21h, while
ASR is enabled!
40
Micronas
VCT 38xxA
ADVANCE INFORMATION
FP Subaddress
Function
h’14e
Status of automatic standard recognition
bit[0]
1
error of the vertical standard (neither 50 nor 60 Hz)
bit[1]
1
detected standard is disabled
bit[2]
1
search active
bit[3]
1
search terminated, but failed
bit[4]
1
no color found
bit[5]
1
standard has been switched (since last reset of this
flag with bit[11] of asr_enable)
bit[4:0]
Default
Name
0
ASR_STATUS
VWINERR
DISABLED
BUSY
FAILED
NOCOLOR
SWITCH
00000 all ok
00001 search not started, because vwin error detected
(no input or SECAM L)
00010 search not started, because detected vert. standard
0x1x0
01x00
01x10
10000
h’21
Input select:
bit[1:0]
00
01
10
11
bit[2]
0
1
bit[4:3]
00
01
10
11
bit[6:5]
bit[7]
bit[8]
bit[10:9]
00
01
10
11
0/1
0/1
00
01
10
11
bit[11]
h’22
not enabled
search started and still active
search failed (found standard not correct)
search failed, (detected color standard not enabled)
no color found (monochrome input or switch betw.
CVBS/SVHS necessary)
writing to this register will also initialize the standard
luma selector
VIN1
VIN2
VIN3
VIN4
chroma selector
CIN1
CIN2
IF compensation
off
6 dB/Okt
12 dB/Okt
10 dB/MHz only for SECAM
chroma bandwidth selector
narrow
normal
broad
wide
adaptive/fixed SECAM notch filter
enable luma lowpass filter
hpll speed
no change
terrestrial
vcr
mixed
status bit, write 0, this bit is set to 1 to indicate
operation complete.
Available for versions with panorama scaler only!
INSEL
00
VIS
0
CIS
00
IFC
01
CBW
FNTCH
LOWP
HPLLMD
0
SFIF
0
LDLY
picture start position, this register sets the start point of active video,
this can be used e.g. for panning. The setting is updated when ’sdt’
register is updated.
h’23
Micronas
luma/chroma delay adjust. The setting is updated when ’sdt’ register is
updated.
bit[5:0]
reserved, set to zero
bit[11:6]
luma delay in clocks, allowed range is +1 ... −7
41
VCT 38xxA
ADVANCE INFORMATION
FP Subaddress
Function
Default
h’2f
YCrCb mode control register
bit[6:0]
reserved (set to 0)
bit[7]
1
ADC over-/underflow
(has to be reset after read if used)
bit[8]
0
disable/enable YCrCb
bit[9]
ADC range
0
nominal input amplitude (±350 mV)
1
extented input amplitude (±500 mV)
bit[11:10]
reserved (set to 0)
Name
0
YCrCb
0
CMB_UC
CC
0
DAA
1
KB
3
2
0
KC
KY
CLIM
Note: Activate the YCrCb mode by
− enabling YCrCb
− selecting simple PAL or NTSC M, svhs=1, comb=0 in the std register
− setting cbw=2 in the insel register
Comb Filter
h’27
comb filter control register
bit[0]
0
comb coefficients are calculated for luma/chroma
1
comb coefficients for luma are used for luma and
chroma
bit[1]
0
luma comb strength depends on signal amplitude
1
luma comb strength is independent of amplitude
bit[2]
0
reduced comb booster
1
max comb booster
bit[4:3]
0..3 comb strength for chroma signal
bit[6:5]
0..3 comb strength for luma signal
bit[11:7]
0..31 overall limitation of the calculated comb coefficients
0
no limitation
31
max limitation (1/2)
Color Processing
h’30
Saturation control
bit[11:0]
0...4094 (2070 corresponds to 100% saturation)
4095
disabled (test mode only)
h’39
amplitude killer level (0:killer disabled)
h’3a
h’dc
2070
ACC_SAT
25
KILVL
amplitude killer hysteresis
5
KILHY
NTSC tint angle, ±512 = ±π/4
0
TINT
DVCO
h’f8
crystal oscillator center frequency adjust, −2048 ... 2047
h’f9
crystal oscillator center frequency adjustment value for line-lock mode
True adjust value is DVCO − ADJUST. For factory crystal alignment,
using standard video signal: set DVCO = 0, set lock mode, read crystal
offset from ADJUST register and use negative value for initial center
frequency adjustment via DVCO.
h’f7
crystal oscillator line-locked mode, lock command/status
write: 100
enable lock
0
disable lock
read: 0
unlocked
>2047
locked
h’b5
crystal oscillator line-locked mode, autolock feature. If autolock is
enabled, crystal oscillator locking is started automatically.
bit[11:0]
threshold; 0: autolock off
42
−720
read only
0
400
DVCO
ADJUST
XLCK
AUTOLOCK
Micronas
VCT 38xxA
ADVANCE INFORMATION
FP Subaddress
Function
Default
Name
FP Status
h’12
general purpose control bits
bit[2:0]
reserved, do not change
bit[3]
vertical standard force
bit[8:4]
reserved, do not change
bit[9]
disable flywheel interlace
bit[11:10]
reserved, do not change
to enable vertical free run mode set vfrc to 1 and dflw to 0
GPC
0
VFRC
1
DFLW
−
ASR
h’13
standard recognition status
bit[0]
1
vertical lock
bit[1]
1
horizontally locked
bit[2]
no signal detected
bit[3]
1
color amplitude killer active
bit[4]
1
disable amplitude killer
bit[5]
1
color ident killer active
bit[6]
1
disable ident killer
bit[7]
1
interlace detected
bit[8]
1
no vertical sync detection
bit[9]
1
spurious vertical sync detection
bit[11:10]
reserved
h’14
input noise level
read only
NOISE
h’cb
number of lines per field, P/S: 312, N: 262
read only
NLPF
h’15
vertical field counter, incremented per field
h’74
measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC)
read only
SAMPL
h’36
measured burst amplitude
read only
BAMPL
h’f0
firmware version number
bit[7:0]
internal revision number
bit[11:8]
firmware release
read only
SW_VERSION
h’170
status of macrovision detection
bit[0]
AGC pulse detected
bit[1]
pseudo sync detected
read only
MCV_STATUS
h’171
bit[11:0]
first line of macrovision detection window
6
h’172
bit[11:0]
last line of macrovision detection window
15
VCNT
MCV_START
MCV_STOP
Horizontal Scaler
1)
h’40
Micronas
these registers are updated when the scaler mode register is written
scaler mode register
bit[1:0]
scaler mode
0
linear scaling mode
1
nonlinear scaling mode, ’panorama’
2
nonlinear scaling mode, ’waterglass’
3
reserved
bit[10:2]
reserved, set to 0
bit[11]
scaler update
0
start scaler update command,
when the registers are updated the bit is set to 1
0
SCMODE
MODE
SCUP
43
VCT 38xxA
FP Subaddress
Function
h’41
luma offset register 1)
bit[6:0]
luma offset 0..127
ITU-R output format:
CVBS output format:
ADVANCE INFORMATION
Default
57
YOFFS
57
4
h’42
active video length for 1-h FIFO 1)
bit[11:0]
length in pixels
h’43
scaler1 compression coefficient 1)
For compression by a factor c the value c*1024 is required.
bit[11:0]
allowed values from 1024..4095
h’44
Name
1080
FFLIM
SCINC1
1024
scaler2 expansion coefficient 1)
For expansion by a factor c the value 1/c*1024 is required.
bit[11:0]
allowed values from 256..1024
SCINC2
1024
h’45
scaler1/2 nonlinear scaling coefficient 1)
0
SCINC
h’47 −
h’4b
scaler1 window controls 1)
5 12-bit registers for control of the nonlinear scaling
0
SCW1_0 − 4
h’4c −
h’50
scaler2 window controls 1)
5 12-bit registers for control of the nonlinear scaling
0
SCW2_0 − 4
2.15.1.1. Scaler Adjustment
In case of linear scaling, most of the scaler registers
need not be set. Only the scaler mode, active video
length, and the fixed scaler increments (scinc1/scinc2)
must be written.
Table 2–6: Set-up values for nonlinear scaler modes
Register
‘waterglass’
border 35%
‘panorama’
border 30%
center compression
The adjustment of the scaler for nonlinear scaling
modes should use the parameters given in Table 2–6.
44
Scaler Modes
3/4
5/6
4/3
6/5
scinc1
1643
1427
1024
1024
scinc2
1024
1024
376
611
scinc
90
56
85
56
fflim
945
985
921
983
scw1 − 0
110
115
83
94
scw1 − 1
156
166
147
153
scw1 − 2
317
327
314
339
scw1 − 3
363
378
378
398
scw1 − 4
473
493
461
492
scw2 − 0
110
115
122
118
scw2 − 1
156
166
186
177
scw2 − 2
384
374
354
363
scw2 − 3
430
425
418
422
scw2 − 4
540
540
540
540
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 2–7: Control Registers of the Fast Processor for control of the video backend functions
− default values are initializied at reset
FP Subaddress
Function
Default
Name
FP Display Control Register
h’130
White Drive Red
(0...1023)
700
WDR 1)
h’131
White Drive Green
(0...1023)
700
WDG 1)
h’132
White Drive Blue
(0...1023)
700
WDB 1)
h’139
Internal Brightness, Picture (0...511), the center value is 256, the range
allows for both increase and reduction of brightness.
256
IBR
h’13c
Internal Brightness, Measurement (0...511), the center value is 256, the
brightness for measurement can be set to measure at higher cutoff current. The measurement brightness is independent of the drive values.
256
IBRM
h’13a
Analog Brightness for external RGB (0...511), the center value is 256, the
range allows for both increase and reduction of brightness.
256
ABR
h’13b
Analog Contrast for external RGB (0...511)
350
ACT
1)
The white drive values will become active only after writing the blue value WDB, latching of new values is indicated by setting the MSB of WDB.
FP Display Control Register, BCL
h’144
BCL threshold current, 0...2047 (max ADC output ~1152)
h’142
BCL time constant 0...15 ➠13 ... 1700 msec
h’143
BCL loop gain. 0..15
h’145
BCL minimum contrast 0...1023
h’105
Test register for BCL/EHT comp. function, register value:
0
normal operation
1
stop ADC offset compensation
x>1 use x in place of input from Measurement ADC
1000
BCLTHR
15
BCLTM
0
BCLG
307
BCLMIN
0
BCLTST
FP Display Control Register, Deflection
h’103
interlace offset, −2048..2047
This value is added to the SAWTOOTH output during one field.
0
INTLC
h’102
discharge sample count for deflection retrace,
SAWTOOTH DAC output impedance is reduced for DSCC lines after vertical retrace.
7
DSCC
h’11f
vertical discharge value,
SAWTOOTH output value during discharge operation, typically same as
A0 init value for sawtooth.
−1365
DSCV
h’10b
EHT compensation vertical gain coefficient, 0...511
0
EHTV
h’10a
EHT compensation time constant, 0...15 --> 3.2..410 msec
15
EHTTM
h’10f
EHT compensation east/west gain coefficient, −1024...1023
15
EHTEW
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VCT 38xxA
ADVANCE INFORMATION
FP Display Control Register, Vertical Sawtooth
h’110
DC offset of SAWTOOTH output
This offset is independent of EHT compensation.
0
OFS
h’11b
accu0 init value
−1365
A0
h’11c
accu1 init value
900
A1
h’11d
accu2 init value
0
A2
h’11e
accu3 init value
0
A3
FP Display Control Register, East-West Parabola
h’12b
accu0 init value
−1121
A0
h’12c
accu1 init value
219
A1
h’12d
accu2 init value
479
A2
h’12e
accu3 init value
−1416
A3
h’12f
accu4 init value
1052
A4
2.15.1.2. Calculation of Vertical and East-West
Deflection Coefficients
Vertical Deflection 60 Hz
In Table 2–8 the formula for the calculation of the
deflection initialization parameters from the polynominal coefficients a,b,c,d,e is given for the vertical and
East-West deflection. Let the polynomial be:
a0
a
b
c
d
128
–1365.3
+682.7
–682.7
1083.5
–1090.2
+1645.5
429.9
–1305.8
a1
a2
P = a + b(x – 0.5) + c(x – 0.5)2 + d(x – 0.5)3 + e(x – 0.5)4
a3
The initialization values for the accumulators a0..a3 for
vertical deflection and a0..a4 for East-West deflection
are 12-bit values. The coefficients that should be used
to calculate the initialization values for different field
frequencies are given below, the values must be
scaled by 128, i.e. the value for a0 of the 50 Hz vertical
deflection is:
1023.5
East-West Deflection 50 Hz
a0
a
b
c
d
e
128
–341.3
1365.3
–85.3
341.3
111.9
–899.6
84.8
–454.5
586.8
–111.1
898.3
72.1
–1171.7
a1
a0 = (a · 128 – b · 1365.3 + c · 682.7 – d · 682.7) / 128
a2
a3
a4
Table 2–8: Calculation of Initialization values for
Vertical Sawtooth and East-West Parabola
756.5
East-West Deflection 60 Hz
Vertical Deflection 50 Hz
a0
a1
a2
a3
a
b
c
d
128
–1365.3
+682.7
–682.7
a0
899.6
–904.3
+1363.4
a1
296.4
–898.4
a2
585.9
a3
a4
46
a
b
c
d
e
128
–341.3
1365.3
–85.3
341.3
134.6
–1083.5
102.2
–548.4
849.3
–161.2
1305.5
125.6
–2046.6
1584.8
Micronas
VCT 38xxA
ADVANCE INFORMATION
3. Text and OSD Processing
3.1. Introduction
3.3. Text Controller
The VCT 38xxA includes a World System Teletext
(WST) decoder, whose display capabilities are also
used for OSD generation. In the following sections the
text and OSD processing part of the VCT 38xxA will be
named TPU for short.
The TPU operates with its own 65C02 core running at
10.125 MHz. The core can address up to 64 kBytes of
memory.
With integrated CPU, RAM and ROM, an adaptive data
slicer, a display controller, and a number of interfaces,
the TPU offers acquisition and display of various teletext and data services such as WST, PDC, VPS, and
WSS. Fig. 3–1 shows the functional block diagram of
the TPU.
The TPU operates independently from the TV controller and can be controlled by software via I2C bus interface (see Section 3.14. on page 82). The TV controller
is not burdened with the task of teletext decoding and
communicates with the TPU via a high-level command
language.
The CPU memory contains 640 Bytes RAM, 12 kBytes
program ROM and 12 kBytes character ROM. The
character ROM holds the font data and is separated
from the program ROM to save CPU time. The CPU
can still access the character ROM via a DMA interface including wait cycles. The display controller can
also access the CPU memory via the same DMA interface. By this means it is possible to locate part of the
character font in program ROM or part of the program
code in character ROM.
Table 3–1: Memory map of text controller
Interrupt Vector
Absolute Address
(High Byte, Low Byte)
The TPU performs the following tasks:
– teletext data acquisition
(hardware)
IRQ
FFFF, FFFE
– teletext data decoding
(software)
Reset
FFFD, FFFC
– page generation
(software)
NMI
FFFB, FFFA
– page memory management
(software)
Control Word
FFF9
– page display
(hardware)
– user interface
(software)
Memory Segment
Absolute Address
Zero Page
0000 − 00FF
3.2. SRAM Interface
Stack Page
0100 − 01FF
The SRAM interface connects a standard SRAM to the
internal bus structure. The address bus is 19 bit wide,
addressing SRAMs up to 4 Mbit. Smaller SRAMs can
also be connected.
OSD Buffer
0100 − 019F
I/O Page
0200 − 02FF
Extra Page
0300 − 037F
The SRAM interface has to handle 3 asynchronous
data streams. The CPU needs access to every memory location of the SRAM. During VBI the slicer writes
up to 22 teletext lines of 43 Bytes into the acquisition
scratch memory. During text display the display controller copies teletext rows from display memory into its
internal row buffer.
Character ROM
5000 − 7FFF
Program ROM
D000 − FFFF
On VCT 38xxA the SRAM interface of the TPU is connected to the memory bus of the TV controller. This is
done to save pins and to give the TV controller faster
access to the display memory. Refer to DMA Interface
(chapter 5.9. on page 96) for more details.
After reset the TPU will not use the SRAM interface
until receiving the I2C command “DRAM_MODE” (see
Section 3.12. on page 68).
Micronas
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VCT 38xxA
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TPU
Clamping
AGC
ADC
I2C Bus
Interface
Program
RAM
Timer
Interrupt
Watchdog
Sync
Interface
Slicer
Program
ROM
65C02
DMA
Interface
WST
Layer
Character
ROM
OSD
Layer
SRAM
Interface
Color &
Prio
Interface
Fig. 3–1: Block diagram of the TPU
48
Micronas
VCT 38xxA
ADVANCE INFORMATION
3.5. Teletext Page Management
0000
Zero Page
As a state-of-the-art teletext decoder, the TPU is able
to store and manage a sufficient number of teletext
pages to absorb the annoying transmission cycle
times. The number of available pages is only limited by
the memory size. With an intelligent software and a
4-Mbit SRAM it is possible to store and to control more
than 500 teletext pages.
Stack Page
I/O Page
Extra Page
1000
12K
Character ROM
8000
D000
12K
Program ROM
A stored teletext page cannot be displayed directly,
because of the row-adaptive transmission and the
level 2 enhancements (row 26−29). Therefore, the
CPU has to transfer the selected teletext page into a
display page buffer, adding extra data such as character set extension and non-spacing attributes.
DMA
Interface
ADR
DATA
DATA
ADR
3.5.1. Memory Manager
BE
65C02
The management of such a data base is a typical software task and is therefore performed by the 65C02.
Using a fixed length page table with one entry for every
possible page, the software distributes the content of
the acquisition scratch buffer among the page memory.
The page size is fixed to 1 kByte, only ghost rows are
chained in 128-Byte segments to avoid unused memory space.
Display
RDY
BUSREQ
The Memory manager is the core of the internal TPU
firmware. Most of the acquisition and display related
functions are controlled by this management.
Fig. 3–2: Memory environment of text controller
3.4. Teletext Acquisition
Acquisition
The only task of the slicer circuit is to extract teletext
lines from the incoming composite video signal and to
store them into the acquisition scratch buffer of the
internal/external SRAM. No page selection is done at
this hardware level.
Four analog sources can be connected, thus it is possible to receive text from one channel while watching
another on the screen. After clamping and AGC amplifier the analog video signal is converted into binary
data. Sync separation is done by a sync slicer and a
horizontal PLL, which generate the horizontal and vertical timing. By these means, no external sync signals
are needed and any available signal source can be
used for teletext reception.
The teletext information itself is acquired using adaptive slicers on bit and byte level with soft error detection to decrease the bit error rate under bad reception
conditions. The slicer can be programmed to different
bit rates for reception of PAL, NTSC or MAC world system teletext as well as VPS, WSS, or CAPTION signals.
Scratch
Memory
Page
Table
Memory
Manager
Page
Memory
Display
Memory
Display
Controller
Fig. 3–3: Memory Manager
Micronas
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ADVANCE INFORMATION
3.5.2. Memory Organization
The upper end of the memory is defined by the SRAM
size, the lower end can be defined with the
PAGE_MEMORY command. Default memory organization is shown in Fig. 3–4.
08 00 00 = 4Mbit
SRAM
02 00 00 = 1Mbit
The memory organization depends on available SRAM
size. If external SRAM is not available, there is only
one display bank for OSD and teletext and the page
memory starts at a different location (see Table 3–1).
3.5.3. Page Table
The memory management is based on a fixed size
page table, which has entries for every hexadecimal
page number from 100 to 8FF. The page table starts
with page 800 and contains a 2-Byte page pointer for
every page.
The page table can be read with the command
READ_PAGE_INFO sending the page number and
reading the 2-Byte page pointer containing:
Page Memory
– SRAM pointer
n x 1 kByte
00 80 00 = 256Kbit
– cycle flag
– memory flag
– subpage flag
00 40 00
– update flag
Display Bank
– protection flag
4 kBytes
The SRAM pointer gives the location where the page
is stored in memory. The page size is fixed to 1 kByte,
only ghost rows are allocated dynamically.
00 30 00
TTX Display Bank
4 kBytes
The cycle flag will be set as soon as this page is
detected in the transmission cycle even if it cannot be
stored in memory. Only if the page is really stored in
memory, the memory flag will be set. The subpage flag
will be set for every page in cycle if the page subcode
is different from 0000H or 3F7FH. The update flag is
set every time a page is stored and will be reset only
for the display page after updating the display memory.
A page with protection flag set will never be removed
from memory.
00 20 00
Acquisition
Scratch
4 kBytes
00 10 00
Page Table
4 kBytes
The memory manager uses page priorities to decide
which pages should be stored or removed from memory. If no more memory is available, pages with lowest
priority are removed automatically and the higher priority pages are stored at their place. By setting the page
priority the programmer has control over the memory
management.
00 00 00
Fig. 3–4: Memory organization
Table 3–1: Memory Organisation
Memory
Segment
Address
≥128k
19k
16k
3k
Display Bank
h’3000
h’4000
h’3000
h’0000
TTX Bank
h’2000
h’4000
h’3000
h’0000
Page Table
h’0000
h’0000
h’0000
no
Acquisition Scratch
h’1000
h’1000
h’1000
no
Page Memory
h’4000
h’1800
h’1800
no
50
SRAM Size
The page table is fully controlled by the memory manager and should never be written by external software.
To change the page table flags the command
CHANGE_PAGE_INFO can be used.
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 3–2: Page Table Format
Index
2-Byte Page Pointer
000
start magazine 8
001
...
100
Cycle
Flag
Memory
Flag
Subpage
Flag
11-bit SRAM Pointer
Update
Flag
Protect
Flag
...
1F0
hexadecimal pages (e.g. TOP)
...
7FE
7FF
priority
end magazine 7
status
subcode req
subcode in
control language
4−11
row flag row flag row flag row flag
12−14
8 Byte
0−7
packet x/00
8−15
16−23
24−31
ghost row pointer subpage pointer
8 Byte
packet x/01
1 kByte page data
packet x/24
24 Byte
mag
page
index
subcode subcode
high
low
Fig. 3–5: Page format
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VCT 38xxA
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3.5.4. Ghost Row Organization
Page-related ghost rows are stored in blocks of
128 Bytes. These ghost blocks are linked together
using 2-Byte ghost row pointers. The first pointer can
be found in the basic page, all following pointers are
part of the block header. A zero pointer indicates the
end of the chain.
ghost
pointer
Page Table
page pointer
Table 3–3: Ghost Row Identification
Row Number Tag
Row
000
empty
001
row 25
010
row 26
011
row 27
100
row 28
101
row 29
110
row 30
111
row 31
page 100
ghost
pointer
ghost block
4-bit designation code
3-bit row number
0000
ghost block
‘aa’
‘aa’
‘aa’
row 1
row 2
row 3
ghost row pointer
Fig. 3–6: Ghost row organization
Every ghost block contains 3 ghost rows which can be
identified by 3 row identification bytes in the block
header. The row identification contains designation
code and row number. The row number is reduced to a
3-bit tag. All ghost rows in one block belong to the
same page. If the memory manager removes a page
from memory, the linked ghost blocks will also be
removed.
8 Byte block header
40 Byte row 1 data
40 Byte row 2 data
40 Byte row 3 data
Fig. 3–7: Ghost block structure
3.5.5. Subpage Manager
Any page in cycle can have a number of subpages,
identified by subcode. In normal mode the subpage
manager will acquire only one subpage of every
requested page. This subpage can be any if subcode
FFFF is requested or it will be selected according to
the requested subcode.
After a PAGE_REQUEST command with subcode
F0xx, the subpage manager will acquire all subpages
of the requested page. The subpages will be chained
in the same order as they are transmitted, i.e. every
new subcode will be added at the end of chain. The
page table entry points to the subpage which was
transmitted first after the page request. The
52
READ_PAGE_INFO command will reply the page
table pointer and the actual number of subpages in
chain.
After a PAGE_REQUEST command with subcode
F1xx, the subpage manager will acquire all subpages
of the requested page but will allocate only a limited
amount of memory to store these subpages. The
parameter “page subcode low” will define the length (in
number of subpages) of a ring buffer in page memory
which will hold the recently received subpages. In this
case, the READ_PAGE_INFO command will return an
index pointing to the most recently updated subpage in
chain, together with the subcode of this page.
Micronas
VCT 38xxA
ADVANCE INFORMATION
The DISPLAY_PAGE_REQUEST command searches
and displays a page according to the requested display subcode. The search starts from page table and
continues through the subpage chain if there is any. A
rolling header will be displayed if the requested subpage cannot be found in memory.
A requested display subcode FFFF (don’t care subcode) will only search and display the first subpage in
chain, thus there is no rolling subpage anymore. A
DISPLAY_PAGE_REQUEST command with subcode
F0xx (follow subcode) will search and display the last
received subpage in chain, thus it is possible to
request all subpages in background while still showing
rolling subpages in display.
Page Table
page pointer
subpage
pointer
page 100
subcode 0003
subpage
pointer
page 100
subcode 0001
3.6. WST Display Controller
The display controller reads data from a display page
buffer in the internal/external SRAM. The display page
buffer is organized in rows which are separated into
level 1 data such as character codes and spacing
attributes and into level 2 data, such as character set
extension and non-spacing attributes. To limit the
memory amount for level 2 data, a slightly modified
stack model is used, in which one pointer bit for every
character location indicates the presence of additional
parallel attributes. Fig. 3–9 shows the organization of
the stack row buffer. In this stack model the number of
non-spacing attributes per row is limited to 40, which
agrees with the WST and CEPT specification.
Level 2 Buffer
Pointer
Level 1 Buffer
1 Char 3 Attr.
0
Char 1
1 Char 3 Attr.
0
Char 2
1 Char 3 Attr.
1
Char 3
0 Char 3 Attr.
0
Char 4
1 Char 6Attr.
0
Char 5
1 Char 6 Attr.
1
Char 6
0 Char 6 Attr.
0
Char 7
1 Char 10 Attr.
0
Char 8
1 Char 10 Attr.
0
Char 9
1 Char 10 Attr.
1
Char 10
0 Char 36 Attr.
1
Char 36
0
0
Char 37
0
0
Char 38
0
0
Char 39
0
0
Char 40
0000
page 100
subcode 0002
Fig. 3–8: Subpage organization
Fig. 3–9: Stack Row Buffer
The display controller includes two row buffers. The
first row buffer holds a copy of a teletext row from the
display page buffer. This decreases the data rate
through the SRAM interface by a factor of 10 or 8,
because new teletext row data is needed only after
10 lines in PAL or 8 lines in NTSC mode. The second
row buffer stores all display attributes in parallel, to
allow level 2 display without additional decoding.
Micronas
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VCT 38xxA
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To present a WST level 2 display, the teletext display
controller has to evaluate the following attributes in
parallel, that is for every character location:
– 10-bit character code
– 5-bit foreground color
– 5-bit background color
– 2-bit size
– 5-bit flash
– 1-bit invert
– 1-bit separated
– 1-bit conceal
– 1-bit underline
– 1-bit boxing/window
Additional attributes are defined to improve the display
of CAPTION and OSD text:
– 1-bit italics
– 1-bit shadow
– 1-bit color mode
The display controller delivers 5-bit digital color information, a shadow signal for contrast reduction, and a
fast blank signal. The color bus is used to address the
color-lookup-table (CLUT) in the video processor. By
this means, the full level 2 color spectrum can be displayed.
54
Micronas
VCT 38xxA
ADVANCE INFORMATION
3.7. Display Memory
The TPU supports a variable number of display memories, each 4 kBytes large. One bank is used to store
the display information of the selected teletext page.
The bank location can be defined with the command
DISPLAY_TTX_POINTER. Other banks can be used
to store any kind of display data in level 1 or level 2 format. Switching between these banks is fast and can be
programmed with the command DISPLAY_POINTER.
Bank switching allows generation of OSD menus without affecting the teletext display.
autoincrement
Row 0
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
Row 1
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
Display Bank
Row 46
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
Row 0
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
Row 1
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
TTX Display Bank
Row 25
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
SRAM
Fig. 3–10: Display memory organization (level 2)
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Table 3–5: Full row attribute
+ 55H
Bit
7
6
5
4 to 0
Table 3–7: Level 2 parallel attributes
R/W
Full Row Attribute
7
6
5
Reset
Function
P
0
0
Color
Foreground Color
P
0
1
Color
Background Color
P
1
0
P
1
1
0
0
L
1 = row is displayed in double height
0 = row is displayed in normal height
P
1
1
0
1
0
DH
DW
Size
P
1
1
0
1
1
0
U
Underline/Separated
1 = row is displayed in level 2 mode
0 = row is displayed in level 1 mode
P
1
1
0
1
1
1
I
Inverted
P
1
1
1
0
0
0
C
Conceal
5-bit value defining full row background color
P
1
1
1
0
0
1
W
Window/Boxing
P
1
1
1
0
1
0
S
Shadow
P
1
1
1
0
1
1
IT
Italic
P
1
1
1
1
0
0
CM
Color Mode
-
1 = row is displayed blank
0 = row is displayed using row data
Table 3–6: Level 1 spacing attributes
Code
00
Function
Action
Alpha Black
01
Alpha Red
02
Alpha Green
03
Alpha Yellow
4
3
2
1
0
Flash
Flash Mode
Set
Character Set
Notes
set alpha
mode and
foreground
color of
following alpha
characters
Table 3–8: Color look-up table
4
3
2
1
0
Display Color
0
0
0
0
0
Black
0
0
0
0
1
Red
0
0
0
1
0
Green
0
0
0
1
1
Yellow
0
0
1
0
0
Blue
04
Alpha Blue
05
Alpha Magenta
06
Alpha Cyan
0
0
1
0
1
Magenta
Alpha White
0
0
1
1
0
Cyan
0
0
1
1
1
White
0
1
0
0
0
Transparent
07
Function
select
character set 0
08
Flash Normal
09
Flash Off
set at
0
1
0
0
1
Reduced Red
0A
Boxing Off
set at double
0
1
0
1
0
Reduced Green
set at double
0
1
0
1
1
Reduced Yellow
0
1
1
0
0
Reduced Blue
0
1
1
0
1
Reduced Magenta
0B
Boxing On
0C
Size Normal
0D
Size Double Height
0
1
1
1
0
Reduced Cyan
0E
Size Double Width
0
1
1
1
1
Reduced White
0F
Size Double
1
x
x
x
x
Programmable
10
Mosaic Black
11
Mosaic Red
12
Mosaic Green
13
Mosaic Yellow
14
Mosaic Blue
15
Mosaic Magenta
16
Mosaic Cyan
set at
set mosaic
mode and
foreground
color of
following
mosaic
characters
select
character set 1
Table 3–4: Flash modes
4
3
2
1
0
Function
0
0
0
0
0
Off
0
0
0
0
1
Normal
0
0
1
0
1
Normal Fast Phase 1
0
1
0
0
1
Normal Fast Phase 2
0
1
1
0
1
Normal Fast Phase 3
0
0
0
1
0
Inverted
17
Mosaic White
18
Conceal
set at
0
0
1
1
0
Inverted Fast Phase 1
19
Contiguous Mosaic
set at
0
1
0
1
0
Inverted Fast Phase 2
1A
Separated Mosaic
set at
0
1
1
1
0
Inverted Fast Phase 3
0
0
0
1
1
Color Table
0
0
1
1
1
Color Table Phase 1
1B
ESC
1C
Black Background
set at
0
1
0
1
1
Color Table Phase 2
1D
New Background
set at
0
1
1
1
1
Color Table Phase 3
1
0
0
x
x
Incremental
1
0
1
x
x
Decremental
1E
1F
Hold Mosaic
set at
Release Mosaic
Shaded attributes are default at start of each display row.
56
Micronas
VCT 38xxA
ADVANCE INFORMATION
3.8. Character Generator
Characters are addressed using a 10-bit character
code. The 2 MSBs of the character code define 1 of 4
character sets. Character set selection is done using
level 2 parallel attributes (see Table 3–7 on page 56).
Each character set contains 224 characters. The first
32 characters in each character set are reserved for
control codes (see Table 3–6 on page 56). On a single
screen, 896 different characters can be displayed.
Characters can be displayed in several pixel resolutions provided that the according font is available. The
character generator supports horizontal resolution of
8 or 10 pixel/char and vertical resolution of 8, 10, or
13 lines/char. Characters can be combined without
separating borders to create more complex character
definitions (e.g. kanji or icons).
Table 3–9: Character resolutions
matrix
(h x v)
char/sc
reen
(PAL)
char/sc
reen
(NTSC)
osd
width
# char in
12k font
# char in
20k font
single character
8x8
40 x 32
40 x 28
32µs
1600
2560
10 x 8
40 x 32
40 x 28
40µs
1280
2048
8 x 10
40 x 26
40 x 22
32µs
1280
2048
10 x 10
40 x 26
40 x 22
40µs
1024
1638
8 x 13
40 x 20
40 x 17
32µs
800
1280
10 x 13
40 x 20
40 x 17
40µs
640
1024
combined character (2 x 2)
16 x 16
20 x 16
20 x 14
32µs
400
640
20 x 16
20 x 16
20 x 14
40µs
320
512
16 x 20
20 x 13
20 x 11
32µs
320
512
20 x 20
20 x 13
20 x 11
40µs
256
409
16 x 26
20 x 10
20 x 8.5
32µs
200
320
20 x 26
20 x 10
20 x 8.5
40µs
160
256
combined character (2 x 1)
16 x 10
20 x 26
20 x 22
32µs
640
1024
16 x 13
20 x 20
20 x 17
32µs
400
640
20 x 13
20 x 20
20 x 17
40µs
320
512
The pixel clock can be either 10.125 MHz or
20.25 MHz. To get 10-bit pixel information from the
character font, two memory cycles are needed. The
character font is part of the mask-programmable ROM,
but supplied with its own bus structure (see Fig. 3–2 on
page 49). By this means the data transfer between
character ROM and teletext display controller does not
stop the CPU.
Both bus structures are connected via a memory interface which allows cross-connections using DMA or
wait cycles. If the character font size exceeds
12 kBytes, part of the character font can be shifted into
the program ROM which causes DMA cycles. Therefore only less frequently used characters should be
placed into the program ROM. Vice versa seldom used
CPU code can be put into the character ROM.
The WST specification defines a number of 7-bit code
tables, which are filled with 96 characters only (the
MSB is used for parity check). In the G0 code table
some characters have several language dependent
variations. Additionally characters from the G0 code
table can be combined with diacritical marks from the
G2 code table (row 26). Furthermore different code
tables are defined for languages like cyrillic, greek or
arabic. Thus it is not possible to simply transform the
code tables into a continuous character font ROM without getting unused ROM space and multiple defined
character fonts.
This problem is solved by implementing a character
code mapping (see Fig. 3–11 on page 58). The
5 MSBs of each character code are mapped into
another 5-bit code which is then used to address the
character font ROM. By this means the whole character font is subdivided into 32 blocks of 32 characters
which can freely be distributed over the 4 character
sets.
The character code mapping is implemented as RAM
and can be programmed by software. After reset the
TPU initializes the mapping RAM for standard WST
latin code tables.
The TV controller can select predefined mappings for
latin, cyrillic and arabic teletext via the command
DISPLAY_MODE (see Table 3–16 on page 70). The
same command allows selection of a user defined
mapping which has to programmed in advance using
command USER_MAPPING.
combined character (1x 2)
10 x 16
Micronas
40 x 16
40 x 14
40µs
640
1024
57
VCT 38xxA
ADVANCE INFORMATION
3.8.1. Character Code Mapping
10-bit Character Code = 2-bit Character Set (level 2) + 8-bit Character Value (level 1)
Character Set 0
000H
080H
00
G0
G0
G0
National
National
National
National
01
02
Character ROM
03
04
05
06
12800 Byte
Font Pointer
00
01
07
02
Character Set 1
100H
180H
G1
G0
G1
National
National
National
National
03
08
04
09
05
10
06
11
07
12
08
13
09
14
10
15
11
Mapping RAM
32 x 5 bit
Character Set 2
200H
280H
G2
G2
G2
User
User
User
User
12
13
16
14
17
15
18
16
19
17
18
20
19
21
22
20
23
21
22
Character Set 3
300H
380H
G3
G3
G3
User
User
User
User
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
block of 32 char
G0
G0
G0
National
National
National
National
G1
G1
G2
G2
G2
User
User
User
User
G3
G3
G3
Greek
Greek
Cyrillic
Cyrillic
Cyrillic
Hebrew
Arabic
Arabic
Arabic
Farsi
31
Fig. 3–11: Character code mapping
58
Micronas
ADVANCE INFORMATION
VCT 38xxA
3.8.2. Character Font ROM
The character font ROM is mask-programmable.
Design of customer specific characters (user font) is
supported by a Windows™ based PC tool named
MOFA (Micronas OSD and Font Assembler). In combi-
nation with the VCT 38xxA emulator board it is possible to download character fonts and verify them on the
TV screen.
Fig. 3–12: Character font ROM
Micronas
59
VCT 38xxA
ADVANCE INFORMATION
3.8.3. Latin Font Mapping
Fig. 3–13: Latin font mapping
60
Micronas
ADVANCE INFORMATION
VCT 38xxA
3.8.4. Cyrillic Font Mapping
Fig. 3–14: Cyrillic font mapping
Micronas
61
VCT 38xxA
ADVANCE INFORMATION
3.8.5. Arabic Font Mapping
Fig. 3–15: Arabic font mapping
62
Micronas
VCT 38xxA
ADVANCE INFORMATION
3.8.6. Character Font Structure
MSB
9
LSB
0
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
LSB
0
MSB
7
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Line 11
Line 12
Line 13
Character Font
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘A‘
‘A‘
‘A‘
‘A‘
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Line 1
Line 2
Line 3
Line 4
Character Font
Extension Font
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Line 1
Line 2
Line 3
Line 4
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘D‘
‘D‘
‘D‘
‘D‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘E‘
‘E‘
‘E‘
‘E‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘F‘
‘F‘
‘F‘
‘F‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘G‘
‘G‘
‘G‘
‘G‘
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Line 11
Line 12
Line 13
Line 14
Line 15
Line 16
‘P‘
‘P‘
‘P‘
‘P‘
‘P‘
‘P‘
‘P‘
‘P‘
‘P‘
‘P‘
Line 1
Line 2
Line 3
‘Q‘
‘Q‘
‘Q‘
‘P‘
‘P‘
‘P‘
Fig. 3–17: Font structure 8 x 13
Fig. 3–16: Font Structure 10 x 10
Micronas
63
VCT 38xxA
ADVANCE INFORMATION
3.9. National Character Mapping
Table 3–10: Character set options
Option Bits
Character Set
6
C14,C13,C12
38
40
55
70
128
000
English
Polish
English (US)
English
English (US)
programmable
001
French
French
French
French
Slovakian
programmable
010
Swedish
Swedish
Swedish
Swedish
Hungarian
programmable
011
Czech
Czech
Czech
Turkish
Serbian
programmable
100
German
German
German
German
Albanian
programmable
101
Spanish
Serbian
Spanish
Spanish
Polish
programmable
110
Italian
Italian
Italian
Italian
Turkish
programmable
111
Estonian
Estonian
Estonian
Estonian
Rumanian
programmable
Table 3–11: Language codes
Code
0
English
1
French
2
Swedish, Finnish
3
Czech
4
German
5
Spanish
6
Italian
7
Estonian, Finnish
8
English (US)
9
Slovakian
10
Hungarian
11
Serbian, Croatian, Slovene
12
Albanian
13
Polish
14
Turkish
15
Rumanian
16
Cyrillic (Russian, Bulgarian)
17
Greek
18
Cyrillic (Serbian, Montenegro)
19
YU Latin
20
Arabic
21
Hebrew
22
Farsi
23
Lettish, Lithuanian
24
Cyrillic (Ukrainian)
25−255
64
Language
not defined
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 3–12: National option mapping
Language
G0/G1 Table Position
2/3
2/4
4/0
5/11
5/12
5/13
5/14
5/15
6/0
7/11
7/12
7/13
7/14
Albanian
5/15
2/4
13/12
13/2
12/12
12/3
11/12
9/1
13/13
13/3
12/13
13/1
11/13
Czech
5/15
12/9
13/13
10/11
12/13
12/11
8/4
15/13
9/3
8/3
12/0
9/2
11/13
English
2/3
2/4
4/0
5/11
5/12
5/13
5/14
5/15
6/0
7/11
7/12
7/13
7/14
English (US)
5/15
2/4
4/0
14/4
13/5
15/4
14/6
13/0
14/7
14/5
15/6
15/5
15/7
Estonian, Finnish
5/15
11/11
11/12
8/13
8/14
12/12
8/15
11/10
11/13
8/10
8/11
12/13
8/12
French
9/3
8/1
8/5
9/1
9/7
8/2
8/8
5/15
9/5
8/7
9/8
8/9
9/0
German
5/15
2/4
15/0
8/13
8/14
8/15
14/6
13/0
14/0
8/10
8/11
8/12
9/10
Hungarian
5/15
9/2
9/14
8/4
8/14
10/1
12/15
11/15
9/3
9/4
8/11
8/3
8/12
Italian
2/3
2/4
9/3
14/0
9/0
5/13
5/14
5/15
8/2
8/5
9/6
9/5
8/6
Polish
5/15
14/3
13/15
13/8
12/7
15/8
13/3
9/4
10/9
13/9
13/7
15/9
13/11
Rumanian
5/15
14/1
10/14
10/5
14/14
14/11
10/6
15/1
10/15
8/7
14/15
12/5
8/8
Serbian, Croatian
5/15
2/4
13/12
13/2
12/12
12/3
11/12
13/0
13/13
13/3
12/13
13/1
11/13
Slovakian
5/15
12/9
13/13
10/11
12/13
12/11
8/4
15/13
9/3
8/3
12/0
9/2
11/13
Spanish
9/0
2/4
9/15
8/3
9/3
8/4
9/4
9/2
9/9
8/12
9/11
9/5
8/5
Swedish, Finnish
5/15
14/1
9/14
8/13
8/14
9/13
8/15
13/0
9/3
8/10
8/11
9/12
8/12
Turkish
13/6
10/13
10/8
14/14
8/14
8/0
8/15
10/12
15/1
14/15
8/11
9/0
8/12
YU Latin
5/15
2/4
13/12
13/2
12/12
12/3
11/12
13/0
13/13
13/3
12/13
13/1
11/13
Micronas
65
VCT 38xxA
ADVANCE INFORMATION
3.10.Four-Color Mode
In “Four-Color Mode” the color depth of single or multiple characters can be increased to 4 colors (e.g. to display icons or 3-D effects). A special font organization is
required because two consecutive characters will be
combined. The number of 4-colored characters is only
limited by font size.
The “Four-Color Mode” is controlled via the level 2 parallel attribute “Color Mode”. Setting the bit CM to 1
activates the “Four-Color Mode” until the end of row or
until the bit CM is set to 0 again. At the start of each
display row the “Four-Color Mode” is disabled.
A character with active “Four-Color Mode” attribute will
be combined with its font neighbor to define a 2
bit/pixel character matrix. The 2 additional colors are
derived from the active foreground and background
colors by inverting bit 3 of the color code. Using the
programmable part of the CLUT it is possible to display
characters in 4 out of 4096 colors.
If the “Four-Color Mode” attribute is set for a character
with even character code n, this character is combined
with its font neighbor addressed by code n + 1. If the
“Four-Color Mode” attribute is set for a character with
Matrix of Character n
odd character code, this character is combined with
itself.
The neighbor character does not change the definition
of foreground and background pixel which is used to
control flash and mix mode.
Table 3–13: Color Allocation
Pixel Definition
Character
n
Character
n+1
0
0
background
1
0
foreground
0
1
background .xor. 8
1
1
foreground .xor. 8
Matrix of Character n+1
+
Color Allocation
4 Color Display
00
10
01
11
=
Fig. 3–18: Four-color mode
66
Micronas
VCT 38xxA
ADVANCE INFORMATION
3.11.OSD Layer
Apart from the WST layer, there is an additional OSD
layer on chip. The OSD layer accesses the CPU memory via DMA to read text, display attributes, and character font information. The color outputs of the OSD
layer can have higher priority than the WST layer outputs. Thus, it is possible to overlay the teletext display
with an additional layer for user guidance (see Fig. 3–
19).
Full Screen Layer
WST Layer
Code
Function
Notes
01
Underline On
only for 13 scanlines/character
02
Underline Off
03
Flash On
04
Flash Off
05
Italics On
06
Italics Off
07
Transparent
layer becomes transparent
08
Shadow
layer becomes transparent and
contrast is reduced to 66%
0C
END
end of layer
0D
CR
end of text line
0E − 7F
ASCII Character
using font 1 or font 2
80 − FF
Control Code
Only one control code per character
is allowed. Depending on OSD
Mode, the control code defines
either color or character set.
Color
bit 0 = foreground color blue
bit 1 = foreground color green
bit 2 = foreground color red
bit 3 = background color blue
bit 4 = background color green
bit 5 = background color red
bit 6 = replace white by transparent
bit 7 = 1
Character Set
bit 0 = bit 7 of character code
bit 1 = bit 8 of character code
bit 2 = bit 9 of character code
bit 3 =
bit 4 =
bit 5 =
bit 6 = latching shift to character set
bit 7 = 1
OSD Layer
Fig. 3–19: Display layer
The OSD layer reads text strings addressed by a programmable text pointer. Codes smaller than 80h will
address the character font, codes greater or equal 80h
are interpreted as control codes to change color or
character set (see Table 3–14). After reading a control
code the OSD layer will do an additional read to get the
next character code.
Micronas
Shaded attributes are default at start of each text line.
67
VCT 38xxA
ADVANCE INFORMATION
3.12.Command Language
The TPU supports a command language, allowing the
TV controller to start complex processing inside the
TPU with simple commands. The TV controller is not
burdened with time consuming tasks like page searching or data shuffling.
The application software has to send commands to the
TPU via I2C bus using the command subaddresse
SUB4 (see Section 3.14.1.3. on page 83).
Table 3–15 lists all available commands. For a more
detailed description of the command language see
Table 3–16.
Table 3–15: Command language cross reference
Code Dec.
68
Code Hex.
Command Name
No. Write
Parameter
No. Read
Parameter
Status Register
0
00
Dummy
0
0
x000 0000
1
01
Reset
0
0
x000 0000
2
02
Escape
0
0
x000 0000
3
03
Version
0
2
x000 0000
4
04
Test
0
0
x000 0000
5
05
Test
0
0
x000 0000
6
06
DRAM Mode
3
0
x000 0000
7
07
Acquisition Mode
5
2
x000 0000
8
08
Display Mode
4
0
x000 0000
9
09
Display TTX Pointer
2
0
x000 0000
10
0a
Display Pointer
3
0
x000 0000
11
0b
Display Clear
2
0
x000 0000
12
0c
Page Request
8
3
x0x0 0000
13
0d
Display Time Pointer
2
0
x000 0000
14
0e
Read DRAM Size
0
3
x000 0000
15
0f
Read VPS
0
15
x0x0 0000
16
10
Read Quality
0
4
x000 0000
17
11
Read Display Mode
0
4
x000 0000
18
12
Read Reset Source
0
1
x000 0000
19
13
Read Rolling Header
0
24
x000 0000
20
14
Read Page Info
2
7
x000 0000
21
15
Read Page Row
5
40
x0x0 0000
22
16
Change Page Info
3
0
x000 0000
23
17
Search MPET
0
1 + (n*4)
x0x0 0000
24
18
Read Display Page
0
4
x000 0000
25
19
Page Memory
2
0
x000 0000
26
1a
Display Page Request
5
0
x000 0000
27
1b
Page Table Reset
0
0
x000 0000
28
1c
Search Next Page
3
6
x0x0 0000
29
1d
Read Page Cycle
0
9
x000 0000
30
1e
Read TOP Code
2
2
x000 0000
31
1f
Read Rolling Time
0
8
x000 0000
32
20
Copy Page Row
8
0
x0x0 0000
33
21
Copy Data
7
0
x000 0000
34
22
Search Next TOP Code
3
4
x0x0 0000
35
23
Read Ghost Row
6
40
x0x0 0000
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 3–15: Command language cross reference
Code Dec.
Code Hex.
Command Name
No. Write
Parameter
No. Read
Parameter
Status Register
36
24
Read 8/30 Row
1
40
x0x0 0000
37
25
Read Priority
0
5
x000 0000
38
26
Page Priority
2
0
x000 0000
39
27
Search AIT
0
1 + (n*4)
x0x0 0000
40
28
Read TOP Status
0
2
x000 0000
41
29
Search AIT Title
2
17
x0x0 0000
42
2a
Reset Ghost Row Status
0
0
x000 0000
43
2b
Search MPT
0
1 + (n*4)
x0x0 0000
44
2c
Copy AIT Title
5
17
x0x0 0000
45
2d
Search Direct Choice
1
1 + (n*2)
x0x0 0000
46
2e
Read Hamming
1
1
x000 0000
47
2f
Read Hamming 2
3
3
x000 0000
3+length
0
x000 0000
4
0
x000 0000
48
30
Display Column
49
31
Display Fill
50
32
Read BTTL
0
9
x0x0 0000
51
33
Read Next Page
2
2
x000 0000
52
34
Change BTT magazine
1
0
x000 0000
53
35
Read WSS
0
15
x0x0 0000
54
36
Read CAPTION 1
0
7
x0x0 0000
55
37
Read CAPTION 2
0
7
x0x0 0000
56
38
OSD Font Pointer
5
0
x000 0000
57
39
Display Read Column
3
length
x000 0000
58
3a
User Character Set
8
0
x000 0000
59
3b
User ESC Character Set
8
0
x000 0000
60
3c
Full Row Attribute
3
0
x000 0000
61
3d
User Mapping
32
0
x000 0000
Micronas
69
VCT 38xxA
ADVANCE INFORMATION
Note:
If not otherwise designated, all parameters in the following table are specified as single bytes. As write
parameter magazine numbers 8 and 0 have the same meaning, as read parameter the magazine number is a
true 4-bit number (e.g. magazine 8= 00001000). For write parameters the values in parentheses indicate
default values after reset (in hex notation). For compatibility reasons every undefined bit in a write parameter should be set to ‘0’. Undefined bits in a read parameter should be treated as “don’t care”.
Table 3–16: Command language
Code
Function
Write Parameter
Read Parameter
Notes
Operational & Test Commands
00
Dummy
no action
01
Reset
software reset of 65C02
02
Escape
03
Version
04
Test
05
Test
06
DRAM Mode
dram mode
flash inc
control enable
(06)
(05)
(FF)
07
Acquisition Mode
acquisition mode
init subcode high
init subcode low
gain max
filter max
(00)
(FF)
(FF)
(1F)
(1F)
14
Read DRAM Size
25
Page Memory
27
Page Table Reset
escape to other codes
CPU pointer high
CPU pointer low
show version in OSD layer
CPU pointer to text in ROM
reserved for testing
reserved for testing
dram mode = I/O page register 028EH
flash freq = flash inc / (256 * 0.00324)
control enable:
bit0 = C4 erase page
bit1 = C5 news flash
bit2 = C6 subtitle
bit3 = C7 suppress header
bit4 = C8 update indicator
bit5 = C9 interrupted sequence
bit6 = C10 inhibit display
bit7 = C11 magazine parallel
gain
filter
acquisition mode:
bit0 = no slicer adaption
bit1 = no bit error in framing code
bit2 = limit slicer adaption
init subcode:
automatic subcode request after
page table reset
gain max:
only used if bit2 = 1
filter max:
only used if bit2 = 1
Memory Management Commands
70
dram size high
dram size low
dram mode
dram bank
dram high
(00)
(40)
dram size:
000CH =
3kByte SRAM
004CH = 19kByte SRAM
0200H = 128kByte SRAM
0240H = 144kByte SRAM
0400H = 256kByte SRAM
0800H = 512kByte SRAM
dram mode:
see I/O page register 028EH
start of page memory
execute page table reset
reset page table
reset ghost row status
reset data service status
reset cycle count
reset memory count
reset ghost count
reset priorities
clear rolling header
clear VPS data
clear WSS data
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 3–16: Command language, continued
Code
Function
42
Reset Ghost Row Status
29
Read Page Cycle
Write Parameter
Read Parameter
Notes
ghost row status:
bit0 = row 24 in cycle
bit1 = row 25 in cycle
bit2 = row 26 in cycle
bit3 = row 27 in cycle
bit4 = row 28 in cycle
bit5 = row 29 in cycle
bit6 = row 30 in cycle
bit7 = row 31 in cycle
ghost row status
2 Byte cycle count
2 Byte memory count
2 Byte ghost count
data service status
memory status
enable
border
(00)
(FF)
= number of pages in cycle
= number of pages in memory
= number of ghost blocks in memory
data service status:
bit0 = 8/30 format 1 updated
bit1 = 8/30 format 2 updated
bit2 = VPS updated
bit3 = WSS updated
bit4 = CAPTION 1st field updated
bit5 = CAPTION 2nd field updated
memory status:
bit0 = memory full
38
Page Priority
enable:
bit0 = enable priority manager
border:
min/max border for page priorities
37
Read Priority
12
Page Request
magazine number
page number
page subcode high
page subcode low
priority
quantity
start magazine number
start page number
number of open requests
removed magazine
number
removed page number
remove pages from memory beginning
at start page if page priority is disabled,
ignores start page if page priority is
enabled
magazine number:
bit0−3 = magazine number
bit4
= not used
bit5
= hex request
bit6
= backward request
bit7
= forced request
= ignore cycle flag
20
Read Page Info
magazine number
page number
page pointer high
page pointer low
subpage count
ghost row count
ring buffer index
page subcode high
page subcode low
= pointer from page table
highest priority
lowest priority
border priority
magazine number
page number
= max priority in page memory
= min priority in page memory
= min/max border for page priorities
= page with lowest priority
Page Related Commands
22
Micronas
Change Page Info
magazine number
page number
page table flags
= number of subpages in chain
= number of ghost rows in chain
if page request with subcode F1xx
page table flags:
bit0 = protection
bit1 = update
bit2 = not used
bit3 = not used
bit4 = not used
bit5 = subpage
bit6 = memory
bit7 = cycle
71
VCT 38xxA
ADVANCE INFORMATION
Table 3–16: Command language, continued
Code
Function
Write Parameter
Read Parameter
Notes
28
Search Next Page
magazine number
page number
search code
magazine number
page number
page pointer high
page pointer low
subpage count
ghost row count
search in page table for cycle flag
magazine number:
bit0−3 = magazine number
bit4
= take search code
bit5
= hex search
bit6
= backward search
bit7
= include start page
search code:
bit0
= search protection flag
bit1
= search update flag
bit2−4 = not used
bit5
= search subpage flag
bit6
= search memory flag
bit7
= search cycle flag
51
Read Next Page
magazine number
page number
magazine number
page number
calculate next page number
magazine number:
bit0−3 = magazine number
bit4
= not used
bit5
= hex calculation
bit6
= backward calculation
bit7
= not used
21
Read Page Row
magazine number
page number
subpage number high
subpage number low
row number
40 Byte row data
row 0 − 24
32
Copy Page Row
magazine number
page number
subpage number high
subpage number low
row number
destination dram bank
destination dram high
destination dram low
35
Read Ghost Row
magazine number
page number
subpage number high
subpage number low
row number
designation code
40
Read TOP Status
30
Read TOP Code
50
Read BTTL
52
Change BTT magazine
43
Search MPT
copy 40Byte text row from page
memory into DRAM
40 Byte row data
row 25 − 28
TOP Commands
72
magazine number
page number
magazine number
TOP status 1
TOP status 2
TOP status 1:
bit0 = not used
bit1 = MPT link in PLT
bit2 = MPET link in PLT
bit3 = AIT link in PLT
bit4 = BTT in memory
bit5 = MPT in memory
bit6 = MPET in memory
bit7 = AIT in memory
TOP status 2:
bit0−5 = not used
bit6
= all MPET in memory
bit7
= all AIT in memory
BTT code
MPT code
code:
bit0−3 = data
bit6
= hamming error
BTTL error
8 Byte BTTL data
BTTL error:
bit6
= hamming error in BTTL
BTTL data:
bit0−3 = data
bit6
= hamming error
(01)
all TOP commands then refer to this
magazine
number of MPTs
magazine number
page number
subpage number high
subpage number low
...
search in PLT
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 3–16: Command language, continued
Code
Function
Read Parameter
Notes
23
Search MPET
number of MPETs
magazine number
page number
subpage number high
subpage number low
...
search in PLT
39
Search AIT
number of AITs
magazine number
page number
subpage number high
subpage number low
...
search in PLT
41
Search AIT Title
magazine number
page number
5 Byte data
12 Byte title
search in AIT
magazine number:
bit0−3 = magazine number (0#8)
bit4−6 = not used
bit7
= ignore title language
data:
bit0−3 = data
bit6
= hamming error
44
Copy AIT Title
magazine number
page number
destination dram bank
destination dram high
destination dram low
5 Byte data
12 Byte title
search in AIT and copy title into dram
magazine number:
bit0−3 = magazine number (0#8)
bit4−6 = not used
bit7
= ignore title language
data:
bit0−3 = data
bit6
= hamming error
34
Search Next TOP Code
magazine number
page number
code condition
magazine number
page number
code
code flag
search in BTT
magazine number:
bit0−3 = magazine number
bit4−5 = not used
bit6
= backward search
bit7
= include start page
code condition:
low nibble = BTT code
high nibble = search condition
0 = BTT code in low nibble
1 = BTT code # 0
2 = block page
3 = group page
4 = normal page
5 = subtitle page
6 = TV page
7 = block/TV page
8 = group/block/TV page
9 = subpage
a = block/TV subpage
b = group/block/TV subpage
c = title page
d = future page
e = future page
f
= future page
code:
bit0−3 = BTT code
bit6
= hamming error
code flag:
bit0
= subtitle page found
bit1
= TV page found
bit2
= block page found
bit3
= group page found
bit4
= normal page found
bit5
= future page found
bit6
= title page found
bit7
= subpage found
45
Search Direct Choice
direct choice code
number of AIT entries
magazine number
page number
...
search in AIT
Micronas
Write Parameter
73
VCT 38xxA
ADVANCE INFORMATION
Table 3–16: Command language, continued
Code
Function
Write Parameter
Read Parameter
Notes
Miscellaneous Data Commands
36
Read 8/30 Row
15
40 Byte row data
only format 1 and 2 are supported
1st byte of row data is already hamming
decoded
Read VPS
framing code
counter
13 Byte VPS data
= 51H
= incremented every VPS reception
= biphase decoded VPS bytes 3−15
53
Read WSS
framing code
counter
13 Byte WSS data
= 78H
= incremented every WSS reception
= 102 WSS elements from group 1 on
54
Read CAPTION 1
counter
6 Byte CAPTION data
= incremented every reception in field 1
= 3x oversampling
55
Read CAPTION 2
counter
6 Byte CAPTION data
= incremented every reception in field 2
= 3x oversampling
19
Read Rolling Header
24 Byte rolling header
every row 0 in cycle
31
Read Rolling Time
8 Byte rolling time
using time pointer
16
Read Quality
text lines
hamming errors
parity errors
soft errors
updated every VBI
18
Read Reset Source
reset source
reset source:
bit0 = clock supervision
bit1 = voltage supervision
bit2 = watchdog
all bits in reset source are reset after
read
46
Read Hamming
hamming (8,4) Byte
data
hamming Byte:
bit0−3 = data
bit6
= hamming error
47
Read Hamming 2
hamming (24,18) 1st Byte
hamming (24,18) 2nd Byte
hamming (24,18) 3rd Byte
address
mode
data
address:
bit0−5
bit7
mode:
bit0−4
data:
bit0−6
33
Copy Data
designation code
= address
= hamming error
= mode
= data
copy data from DRAM to DRAM
source dram bank
source dram high
source dram low
length
destination dram bank
destination dram high
destination dram low
Display Commands
Read Display Mode
08
Display Mode
display mode
character set
font mapping
(18)
(06)
(00)
display mode:
character set:
font mapping:
09
Display TTX Pointer
dram high
dram low
(20)
(00)
page memory is copied to TTX pointer
10
Display Pointer
dram high
dram low
scroll counter
(20)
(00)
(00)
display starts at pointer using scroll
counter as line offset
11
Display Clear
dram high
dram low
74
display mode
character set
font mapping
display mode:
bit0 = forced boxing
bit1 = reveal
bit2 = box
bit3 = time hold
bit4 = page hold
bit5 = row 24 hold
bit6 = row 25 hold
bit7 = row 26 hold
17
see above
6,38,40,55,70,128
0=latin
1=cyrillic/greek
2=arabic/farsi/hebrew
128=user defined
clear display bank beginning at pointer
(26 rows * 86 Bytes)
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 3–16: Command language, continued
Code
Function
Write Parameter
13
Display Time Pointer
dram high
dram low
26
Display Page Request
magazine number
page number
subpage number high
subpage number low
display delay
(1E)
24
Read Display Page
48
Display Column
49
Display Fill
Read Parameter
(20)
(20)
Notes
8 Byte time string from packet x/00 is
copied to time pointer
magazine number:
bit0−3 = magazine number
bit4
= change display delay
bit5
= display clear (on update)
bit6−7 = not used
subpage number:
F0xx for rolling subpages
display delay:
delay after row 0 reception in steps
of 3.24ms (255 = no update)
only used if bit4 = 1
magazine number
page number
subpage number high
subpage number low
current page in display
dram high
dram low
length
Byte list
...
write to dram with increment of 86 Bytes
dram high
dram low
length
character
repeated write of 1 character to dram
font mode:
bit0 = 0 = reset OSD font 2 pointer
bit0 = 1 = load OSD font 2 pointer
with following parameters
= number of bytes in list
= number of repeated writes
56
OSD Font Pointer
font mode
(00)
font pointer high
font pointer low
extension font pointer high
extension font pointer low
57
Display Read Column
dram high
dram low
length
58
User Character Set
language 000
language 001
language 010
language 011
language 100
language 101
language 110
language 111
(00)
(01)
(02)
(03)
(04)
(05)
(06)
(07)
If character set 128 is selected via
command 08 “Display Mode”, these 8
languages will be selected by option bits
C14,C13,C12 when ESC code is
inactive.
59
User ESC Character Set
esc language 000
esc language 001
esc language 010
esc language 011
esc language 100
esc language 101
esc language 110
esc language 111
(00)
(00)
(00)
(00)
(00)
(00)
(00)
(00)
If character set 128 is selected via
command 08 “Display Mode”, these 8
languages will be selected by option bits
C14,C13,C12 when ESC code is active.
60
Full Row Attribute
full row attribute
number of rows
start row
set full row attribute of specified rows
without changing level 2 bit
61
User Mapping
32 Byte mapping data
32 Bytes are copied into mapping ram
via I/O page register 0276H
Micronas
Byte list
...
read from dram with increment of
86 Bytes
= number of Bytes to read
75
VCT 38xxA
ADVANCE INFORMATION
3.13.I/O Register
Most of the I/O registers can only be written and will
not return useful data when read by application software. Reset values are written by TPU during initialization.
Most hardware-related functions of the TPU are controlled by memory mapped I/O of the 65C02. The
application software has access to the I/O registers via
I2C bus using the CPU subaddresses SUB1 and SUB2
(see Section 3.14.1.1. on page 82).
Note:
For compatibility reasons, every undefined bit of a
write register should be set to ‘0’. Undefined bits of
a read register should be treated as “don’t care”.
0200 H
R/W
CONTROL REGISTER
Bit
Reset
Write Function
all
00 H
During reset the control register is loaded with the contents of the address FFF9H, but it can be read and
written via software.
7
0
1 = CPU disable
0 = CPU enable
6
0
1 = program RAM disable
0 = program RAM enable
5
0
1 = program ROM disable
0 = program ROM enable
4
0
1 = character ROM disable
0 = character ROM enable
3
0
1 = DMA interface disable
0 = DMA interface enable
2
0
1 = I/O page disable
0 = I/O page enable
1
0
1 = test mode on
0 = test mode off
0
0
1 = burnin test mode (only if test pin high)
0 = normal test mode
0202 H
Write
STANDBY
Bit
Reset
Function
2
0
1 = digital circuitry power off(CPU still active with slow clock)
0 = digital circuitry power on
1
0
1 = analog front-end power off
0 = analog front-end power on
0213 H
Write
INTERFACE MODE
Read Function
1 = burnin test mode
0 = normal test mode
Bit
Reset
Function
1
0
1 = standby enable
0 = standby disable
0251 H
Write
BLANKING STOP
Bit
Reset
Function
all
07 H
horizontal stop of blanking pulse in character increments
correct blanking pulse cannot be guaranteed if blanking start = blanking stop
76
(if bit 2 of register 0202H = 1)
Micronas
VCT 38xxA
ADVANCE INFORMATION
0252 H
Write
BLANKING START
Bit
Reset
Function
all
00 H
horizontal start of blanking pulse or self-timed HSYNC in character increments
correct blanking pulse cannot be guaranteed if blanking start = blanking stop
0254 H
Write
DISPLAY MODE 1
Bit
Reset
Function
7
0
1 = OSD layer always uses FONT 1
0 = OSD layer changes from FONT 1 to FONT 2 if ASCII≥ 20H
6
1
1 = enable OSD layer
0 = disable OSD layer
5
1
1 = active flash phase of OSD layer
0 = inactive flash phase of OSD layer
4
0
1 = 13 scanlines/character
0 = 8 scanlines/character
3 to 0
0
With this scan line the OSD layer starts display of the first text line. By slow incrementing of this value soft
scroll begins.
0255 H
Write
DISPLAY MODE 2
Bit
Reset
Function
7
0
1 = OSD layer control code defines character set
0 = OSD layer control code defines color
3
1
1 = 10.125MHz display clock
0 = 20.25MHz display clock
2
1
1 = font pointer offset 10 scanlines/character
0 = font pointer offset 8 or 16 scanlines/character (depending on bit 1)
1
0
1 = font pointer offset 16 scanlines/character
0 = font pointer offset 8 scanlines/character
0
1
1 = 10 scanlines/character
0 = 8 or 13 scanlines/character (depending on bit 4 in register 0254 H)
025A H
Write
PRIO MODE
Bit
Reset
Function
5 to 3
110
prio code for shadow pixel
2 to 0
101
prio code for normal pixel
025B H
R/W
FB Mode
Bit
Reset
Write Function
all
00 H
7
0
color bit 4(color output of OSD layer)
6
0
color bit 3(color output of OSD layer)
4
0
1 = inverted color output
0 = normal color output
Micronas
Read Function
every read resets status
77
VCT 38xxA
ADVANCE INFORMATION
0260 H
Write
OSD LAYER VERTICAL START
Bit
Reset
Function
all
00 H
60 H
9-bit value defining vertical position (in scanline)
1st write:
bit 0 = MSB
2nd write:
bit 7 to 0 = 8 LSBs
0261 H
Write
OSD LAYER VERTICAL STOP
Bit
Reset
Function
all
01 H
28 H
9-bit value defining vertical position (in scanline)
1st write:
bit 0 = MSB
2nd write:
bit 7 to 0 = 8 LSBs
0262 H
Write
OSD LAYER HORIZONTAL START
Bit
Reset
Function
all
16 H
8-bit value defining horizontal start position (in character)
0264 H
Write
OSD LAYER TEXTPOINTER
Bit
Reset
Function
all
−
16-bit value defining memory address of text
1st write:
bit 7 to 0 = 8 MSBs
2nd write:
bit 7 to 0 = 8 LSBs
0265 H
Write
OSD LAYER 2nd COLOR START
Bit
Reset
Function
all
01 H
38 H
9-bit value defining vertical start for 2nd color (in scanline)
1st write:
bit 0 = MSB
2nd write:
bit 7 to 0 = 8 LSBs
0266 H
Write
OSD LAYER 2nd COLOR
Bit
Reset
Function
6 to 0
0C H
7-bit value defining 2nd color
2nd color is used during 1 text row (8, 10 or 13 scanlines) after 2nd color start
0267 H
Write
WST LAYER VERTICAL START
Bit
Reset
Function
all
00 H
24 H
9-bit value defining vertical position (in scanline)
1st write:
bit 0 = MSB
2nd write:
bit 7 to 0 = 8 LSBs
0268 H
Write
WST LAYER HORIZONTAL START
Bit
Reset
Function
all
0F H
8-bit value defining horizontal start position (in character)
78
Micronas
VCT 38xxA
ADVANCE INFORMATION
026A H
Write
WST LAYER VERTICAL STOP
Bit
Reset
Function
all
01 H
28 H
9-bit value defining vertical position (in scanline)
1st write:
bit 0 = MSB
2nd write:
bit 7 to 0 = 8 LSBs
026B H
Write
WST LAYER LAST ROW
Bit
Reset
Function
all
01 H
1E H
9-bit value defining last scanline of the last row to display level 1 double height
after this scanline the level 1 double height attribute will not be decoded anymore
1st write:
bit 0 = MSB
2nd write:
bit 7 to 0 = 8 LSBs
026C H
Write
RGB MODE
Bit
Reset
Function
5
0
1 = WST layer mixed mode
0 = WST layer normal mode
4 to 3
0
11 = WST layer top
10 = WST layer opaque bottom
01 = WST layer transparent bottom
00 = WST layer disable
2
0
1 = OSD layer mixed mode
0 = OSD layer normal mode
1 to 0
0
11 = OSD layer top
10 = OSD layer opaque bottom
01 = OSD layer transparent bottom
00 = OSD layer disable
026D H
Write
SYNC MODE
Bit
Reset
Function
5
0
1 = double scan enable
0 = double scan disable
4
0
1 = blanking disable
0 = blanking enable
026F H
Write
DISPLAY MODE 3
Bit
Reset
Function
7
1
1 = 10 pixel/character
0 = 8 pixel/character
6
0
1 = double dot size in vertical direction(OSD layer only)
0 = normal dot size in vertical direction
5
0
1 = double dot size in horizontal direction(OSD layer only)
0 = normal dot size in horizontal direction
4
0
1 = black colors replaced by transparent & shadow(OSD layer only)
0 = black colors displayed black
3 to 0
FH
4-bit value defining delay of horizontal start for both layers (in pixel)
delay = mod16 (character_width − 2 − value)(leftmost position should not be used!)
Micronas
79
VCT 38xxA
ADVANCE INFORMATION
0270 H
Write
DISPLAY MODE 4
Bit
Reset
Function
4
0
1 = new mosaic mode (single switch to character set 1)
0 = old mosaic mode (static switch to character set 1)
3
0
1 = level 1 display mode (read 40 Byte from display bank)
0 = level 2 display mode (read 86 Byte from display bank)
2
0
1 = boxing enable
0 = boxing disable
1
0
1 = reveal enable
0 = reveal disable
0
0
This bit is taken as flash clock for the WST layer, the frequency should be around 6 Hz.
0273 H
Write
DISPLAY MODE 5
Bit
Reset
Function
4
0
WST layer scan line counter preset (LSB for zoom mode)
3 to 0
0
WST layer scan line counter preset
028E H
Write
DRAM MODE
Bit
Reset
Function
4
0
1 = next CPU write without WEQ but with address increment
0 = normal CPU write mode
3
0
1 = reset address pointer and switch off refresh during standbyt
0 = keep address pointer and refresh during standby
2
1
1 = display channel enable
0 = display channel disable
1
1
1 = slicer channel enable
0 = slicer channel disable
029C H
Read
ACQ SOFT ERROR COUNTER
Bit
Reset
Function
5 to 0
−
6-bit soft error counter
counts number of soft error corrected bytes
counter stops at 63
reset after read
029E H
Read
ACQ SYNC STATUS
Bit
Reset
Function
7
−
1 = field 1
0 = field 2
set at line 624 (PAL) or line 524 (NTSC)
reset at line 313 (PAL) or line 263 (NTSC)
6
−
1 = vertical retrace
0 = vertical window
set at line 628 (PAL) or line 528 (NTSC)
reset at line 624 (PAL) or line 524 (NTSC)
80
Micronas
VCT 38xxA
ADVANCE INFORMATION
029F H
Write
ACQ STANDARD
Bit
Reset
Function
7
0
1 = CAPTION enable in field 2
0 = CAPTION disable in field 2
6
0
1 = CAPTION enable in field 1
0 = CAPTION disable in field 1
5
0
1 = VPS enable
0 = VPS disable
7 to 5
0
VPS and CAPTION cannot be used at the same time, therefore these combinations are used to enable
WSS reception on a PAL+ signal
0=
1 = VPS
2 = CAPTION field 1
3 = WSS & VPS
4 = CAPTION field 2
5 = WSS & VPS
6 = CAPTION field 1&2
7 = WSS
4
1
1 = acquisition enable
0 = acquisition disable
1 to 0
0
00 = PAL mode
10 = NTSC mode
11 = Caption full field mode
02A3 H
Write
ACQ VIDEO INPUT
Bit
Reset
Function
1 to 0
0
00 = VIN1
01 = VIN2
10 = VIN3
11 = VIN4
02A4 H
Read
ACQ HSYNC COUNTER
Bit
Reset
Function
7 to 0
0
number of detected horizontal sync pulses per frame divided by 4
sync pulse is detected if within horizontal window of HPLL
counter is latched with vertical sync, the register can be read at any time
Micronas
81
VCT 38xxA
ADVANCE INFORMATION
3.14.I2C-Bus Slave Interface
Communication between the TPU and the TV controller is done via I2C bus. For detailed information on the
I2C bus please refer to the Philips manual ‘I2C bus
Specification’.
The TPU acts as a slave transmitter/receiver and uses
clock synchronization to slow down the data transfer if
necessary. General call address will not be acknowledged.
Different memories and functions of TPU can be
accessed by subaddressing. The byte following the
slave address byte is defined as the subaddress byte.
Maximum length of an I2C telegram is 256 Bytes following slave address and subaddress byte. The interface supports data transfer with autoincrement.
The I2C bus interface is interrupt-driven and uses an
internal 48-Byte buffer to collect I2C data in real-time
without disturbing internal processes. This is done to
avoid clock synchronization as far as possible. When
the TPU has to process the I2C buffer and the I2C telegram has not yet been stopped, the I2C clock line will
be held down.
The time required to process the I2C buffer depends
on other processes running inside the TPU firmware.
Thus the following I2C telegram addressing the TPU
can be held after the slave address byte until the old
telegram is completely processed.
3.14.1.Subaddressing
Access to all memory locations and to the command
interface is achieved by subaddressing. Both the external DRAM and the internal CPU memory can be
addressed completely. The TPU acknowledges 6 different subaddresses following the slave address (see
Table 3–17 on page 82).
The following symbols are used to describe the I2C
example telegrams:
<
>
ab
ah
al
cc
dd
ss
..
start condition
stop condition
address bank byte
address high byte
address low byte
command byte
data byte
status byte
0 − n continuation bytes
Table 3–17: I2C bus subaddresses
Name
Binary Value
Hex Value
Mode
Function
TPU
0010 001x
22, 23
W, R
TPU slave address
Sub 1
0111 1000
78
W
subaddressing CPU (static)
Sub 2
0111 1001
79
W
subaddressing CPU (autoincrement)
Sub 3
0111 1010
7A
W
subaddressing DRAM (autoincrement)
Sub 4
0111 1011
7B
W
subaddressing command language
Data
0111 1100
7C
R/W
subaddressing data register
Status
0111 1101
7D
R
status register
bit 7 = command wait
bit 6 = command invalid
bit 5 = command found no data
bit 4 = not used
bit 3 = not used
bit 2 = not used
bit 1 = 0
bit 0 = 0
3.14.1.1. CPU Subaddressing
There are 2 CPU subaddresses to access CPU memory: either with static memory address or with autoincrementing memory address. The main purpose of
CPU subaddressing is to write text into the OSD buffer
and to access the I/O page (see Section 3.13. on
82
page 76). The static CPU subaddress can be used to
write more than 1 Byte into the same I/O page register.
The CPU subaddress has to be followed by 2 address
bytes defining the CPU memory address. The following data byte is written into this address. In the case of
autoincrement the continuation bytes are written into
incrementing memory addresses.
Micronas
VCT 38xxA
ADVANCE INFORMATION
The CPU telegram can be stopped after the 2 memory
address bytes. The following I2C telegram subaddressing the data register will continue data transfer to or
from the CPU memory. The data transfer will always
start at the CPU memory address (autoincrement is
not saved).
< 22 78 ah al dd .. >
< 22 79 ah al dd .. >
< 22 79 ah al > < 22 7C dd .. >
Data is directly written into CPU memory without using
the I2C buffer of TPU and without waiting for a stop
condition.
3.14.1.2. DRAM Subaddressing
DRAM access is necessary to generate level 2 displays. The external DRAM can be addressed on byte
level. The maximum DRAM size of 16 Mbit requires a
21-bit memory address pointer. The format of the
DRAM address pointer is shown in Fig. 3–20.
5-bit Bank
8-bit High
8-bit Low
Fig. 3–20: DRAM address pointer
The DRAM subaddress has to be followed by
3 address bytes defining the DRAM address pointer.
The following data byte is written into this address.
DRAM subaddressing always uses autoincrement.
Separate read and write DRAM address pointers are
saved for autoincrement.
The DRAM telegram can be stopped after the 3 address pointer bytes. The following I2C telegram subaddressing the data register will continue data transfer to
or from the DRAM.
3.14.1.3. Command Subaddressing
TPU supports a command language, allowing the host
controller to start complex processing inside the TPU
with simple commands (see Section 3.12. on
page 68). Commands have to be sent to the command
subaddress.
The command subaddress has to be followed by the
command code. The following data bytes are taken as
command parameters.
The execution time for commands depends on other
processes running inside the TPU firmware, therefore
the host controller has to read the status register to get
information about the running command before reading command parameter or starting other commands.
The status register returns information about the command interface. The ‘command wait’ bit is set during
execution of a command and is reset when a command is executed completely and read parameters are
available. If a non-existing command is sent to the
TPU, the ‘command invalid’ bit is set. If a command
could not be executed successfully, the ‘command
found no data’ bit is set. In this case the read parameters of this command are not valid.
Reading status from TPU is done by subaddressing
the status register followed by repeated start condition
and slave read address (see Fig. 3–21).
< 22 7B cc dd .. >
< 22 7D < 23 ss .. >
< 22 7C < 23 dd .. >
Telegrams subaddressing the command interface are
buffered and processed after receiving the stop condition. Therefore the command code and all necessary
command parameters have to be included in a single
telegram.
When reading the DRAM, the first data byte the TPU
returns is a dummy byte, which has to be ignored.
3.14.1.4. Data Subaddressing
< 22 7A ab ah al dd .. >
< 22 7A ab ah al > < 22 7C dd .. >
< 22 7A ab ah al > < 22 7C < 23 dd ..>
Writing data to TPU memory is possible by subaddressing the data register directly. The data is then
written into memory addressed by the foregoing telegram.
Data written to the DRAM subaddress is collected first
in the I2C buffer of TPU and is copied to DRAM when
the buffer is full (48 Bytes) or after stop condition. During the time the buffer is copied to DRAM the TPU will
hold the I2C clock line down.
Reading data from the DRAM subaddress is also buffered internally. Reading the first byte will only empty the
I2C buffer. Every time the buffer is empty, the TPU will
copy 48 Bytes from DRAM into the I2C buffer. During
this time the TPU will hold the I2C clock line down.
Micronas
< 22 7C dd .. >
Reading data from TPU is done by subaddressing the
data register followed by a repeated start condition and
slave read address (see Fig. 3–21). The returned data
depend on the subaddress selected in the preceding
TPU telegram.
< 22 7C <
23 dd .. >
83
VCT 38xxA
ADVANCE INFORMATION
S
0010001
W Ack
0111 1000
Ack
n Byte Sub 1
Ack
P
S
0010001
W Ack
0111 1001
Ack
n Byte Sub 2
Ack
P
S
0010001
W Ack
0111 1010
Ack
n Byte Sub 3
Ack
P
S
0010001
W Ack
0111 1011
Ack
n Byte Sub 4
Ack
P
S
0010001
W Ack
0111 1100
Ack
n Byte Data
Ack
P
S
0010001
W Ack
0111 1100
Ack
R
Ack
S
0010001
W Ack
0111 1101
Ack
S
0010001
S
0010001
1
0
SDA
S
P
SCL
R
n−1 Byte Data
Ack
last Byte Data
Nak P
Ack
W
R
Ack
Nak
S
P
=
=
=
=
=
=
=
=
Status
Ack
Status
Nak P
0
1
0
1
Start
Stop
Interrupt
Data from TPU
Fig. 3–21: I2C bus protocol
3.14.1.5. Hardware Identification
A separate I2C bus slave register is reserved to read
out the hardware version of VCT 38xxA. This register
is active in standby mode.
I2C Sub
address
Number
of bits
h’9F
16
84
Mode
r
Function
Hardware version number
bit[7:0]
hardware id (A3=h’13, B1=h’21 a.s.o.)
bit[15:8]
product code VCT38xy (VCT3832=h’32)
Default
Name
read HWID
only TC
PROD
Micronas
VCT 38xxA
ADVANCE INFORMATION
4. Audio Processing
4.1. Introduction
4.2. Input Select
The audio processing allows input selection and volume control for mono audio sources either from tuner
or from SCART input.
Both audio output channels can be switched to any of
the three audio input channels. Only the audio output
channel AOUT1 can be volume controlled.
AIN1
4.3. Volume Control
AIN2
AOUT1
AIN3
AOUT2
Fig. 4–1: Audio processing
The analog volume control covers a range from
+18 dB and −75 dB. The lowest step is the mute position. Step size is split into a 3-dB and a 1.5-dB range.
−75 dB...−54 dB :
3 dB step size
−54 dB...+18 dB : 1.5 dB step size
4.4. I2C-Bus Slave Interface
The input selection and analog volume is controlled via
the audio control register ACON. This I2C register is
activated by the chip address of the video back-end
processing (see Table 2–2 on page 32).
Table 4–1: Audio control register
I2C Sub
address
Number
of bits
h’34
16
Micronas
Mode
w
Function
Audio Control
bit [5:0]
volume control
000000
mute
000001
−75db
...
−57.0dB
000111
−54.0dB
001000
...
101011
−1.5dB
101100
0.0dB
101101
+1.5dB
...
110110
+15.0dB
110111
+16.5dB
111000
+18.0dB
bit [7:6]
reserved
bit [9:8]
audio input select 1
00
mute
01
AIN1
10
AIN2
11
AIN3
bit [11:10] audio input select 2
00
mute
01
AIN1
10
AIN2
11
AIN3
bit[12]
low power mode
0
disable low power mode
1
enable low power mode
bit[15:13] reserved
Default
Name
0 ACON
AVOL
ASEL1
ASEL2
ALPM
85
VCT 38xxA
ADVANCE INFORMATION
5. TV Controller
5.1. Introduction
5.2.1. CPU Slow Mode
The TV controller basically consists of the CPU, RAM,
ROM, and a number of peripheral modules.
To reduce power consumption considerably, the user
can reduce the internal CPU clock frequency to 1/256
of the normal fCPU value. In this CPU Slow mode, program execution is reduced to 1/256 of the normal
speed, but clocking of most other modules remains
unaffected. The modules that are affected by CPU
Slow mode are:
For instance:
– a memory banking module is included to allow
access to more than 64 kB memory.
– a bootloader software is included to allow in-systemdownloading of external code to Flash memory via
the I2C interface.
1. CPU and Interrupt Controller with all internal and
external interrupts
2. RAM, ROM and DMA
The TV controller runs the complete software necessary to control a TV set. The software includes control
of the audio, video, OSD, and text processors on chip,
as well, as control of external devices like tuner or stereo decoder.
Communication between the TV controller and external devices is done either via I2C bus interface or via
programmable port pins.
The TV Controller is clocked with fOSC = fXTAL/2.
5.2. CPU
The CPU is fully compatible to WDC’s W65C02 microprocessor. The processor has 8-bit registers/accumulator, an 8-bit data bus, and a 16-bit address bus. For
further information about the CPU core, please refer to
the WDC W65C02 data sheet.
fast mode
3. Watchdog
Some modules must not be operated during CPU Slow
mode. Refer to module sections for details.
After reset the CPU is in Fast mode (fCPU = fOSC).
CPU Slow mode is enabled by clearing flag CPUFST
in standby register SR1. The CPU clock frequency
reduction to fOSC/256 will take effect after a maximum
delay of 256 fOSC periods.
Returning CPU to Fast mode is done by setting flag
CPUFST to High. The CPU clock frequency will immediately change to its normal fOSC value.
Fig. 5–1 shows the memory access signals during
CPU fast and slow mode.
slow mode
fOSC
PH2
CCUPH2
RW
WE
OE
Fig. 5–1: Memory access signals
86
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.3. RAM and ROM
Table 5–2: Internal Memory Locations
On-chip RAM is composed of static RAM cells. The
RAM will hold all information during reset, as long as
the specified operating voltages are available.
The 64PSDIP Multi Chip Module contains a 128-KByte
Flash EEPROM of the ST M29W010B type. These
devices exhibit electrical Byte program and block erase
functions. Refer to the ST M29W010B data sheet for
details.
Addresses
Internal Memory
000000 − 000FFF
4k Program RAM
001E00 − 001FFF
I/O Register
002000 − 0023FF
1k Bootloader ROM
002400 − 019FFF
95k Program ROM
0A0000 − 0A3FFF
16k Text RAM
5.3.1. Address Map
The following ROM addresses are reserved and cannot be used to store program code.
Table 5–1: Reserved (physical) addresses
Addresses
Usage
00FFC6 − 00FFD5
Manufacturer ROM ID
00FFD6 − 00FFD7
reserved for bootloader
00FFD8 − 00FFF7
Interrupt Vectors
00FFF8
reserved
00FFF9
Control Word (during reset)
00FFFA − 00FFFB
NMI Vector (expanded by
Interrupt Controller)
00FFFC − 00FFFD
Reset Vector
0xFFFE − 0xFFFF
IRQ/BRK Vector
A 16-Byte address space is reserved as “Manufacturer
ROM ID”. This area contains a unique ROM ID number
which has to be agreed between Micronas and the
customer. Especially the first 6 digits identify customer
and version. As an example a Micronas demo software
is identified like “MI1108 240700 TV”.
Table 5–2 shows the internal memory segmentation.
Internal program RAM and ROM can be disabled via
the Control Register (chapter 5.4. on page 87). The
internal text RAM can be disabled via Standby Register 0 (see page 89).
All memory locations not available internally will be
addressed as external memory. It is possible to operate with internal and external memory in parallel, but
overlapping memory segments will always be
addressed internally.
5.3.2. Bootloader
A segment of the internal ROM is reserved for bootloader code. Via this bootloader code it is possible to
download additional code into the internal RAM and
execute this code. The downloaded code can be used
to program the external Flash EEPROM.
After reset the bootloader checks the I2C bus pins SDA
and SCL for a special identification sequence. If no
identification sequence is detected, the bootloader
starts the application program code.
The bootloader checks the address FFD6/FFD7 of the
external memory if there is a predefined pattern
(A55Ah). If so, it starts the external application software else it starts the internal application software.
5.4. Control Register
The Control Register CR serves to configure the ways,
by which certain system resources are accessed during operation. The main purpose is to obtain a variable
system configuration during IC test.
Upon each High transition on the RESQ pin internal
hardware reads data from address location 00FFF9h
and stores it to the CR. The state of the TEST pin at
this timepoint specifies which program storage source
is accessed for this read:
– With the TEST pin Low, the control byte is read from
internal program storage (mask ROM). With location
00FFF9h set to FFh, this is the setting for standalone operation.
– With the TEST pin High, the control byte is read
from external memory via the test bus (for test purposes only).The system will thus start up according
to the configuration defined in address location
00FFF9h and automatically copied to register CR.
During internal memory access, the pins DB0-DB7,
WExQ and OExQ are tristate. For emulation and test
purposes it is possible to change this behavior via the
Micronas
87
VCT 38xxA
1:
1F01
bit
r/w
7
2:
6
CR
3:
5
RESLNG TSTTOG DISEXT
reset
RESLNG
r/w1:
r/w0:
ADVANCE INFORMATION
Control Register
4
3
2
1
0
MFM
TSTROM
IROM
IRAM
ICPU
Value of 00FFF9h
Reset Pulse Length
Pulse length is 4095/fOSC.
Pulse length is 16/fOSC.
This bit specifies the length of the reset pulse which is
output at pin RESQ following an internal reset. If pin
TEST is 1 the first reset after power on is short. The
following resets are as programmed by RESLNG. If pin
TEST is 0 all resets are long.
TSTTOG
r/w1:
r/w0:
TEST Pin Toggle
Pin TEST can toggle the Multi Function
pins.
Pin TEST can’t toggle the Multi Function
pins.
Table 5–5: Some commonly used settings for address
location 00FFF9h.
Code
TEST
Pin
Operation Mode
FFh
0
Stand-alone with internal ROM
or Flash
DFh
0
Emulator mode (CPGA257
package)
ABh
1
External program storage connected to Multi Function pins in
Bus mode
Table 5–3: TSTROM and IROM usage in mask ROM
parts
TSTROM
IROM
selected program storage
This bit is used for test purposes only. If TSTTOG is
true in IC active mode, pin TEST can toggle the Multi
Function pins between Bus mode and normal mode.
1
1
internal CPU ROM
0
1
internal Test ROM
DISEXT
r/w1:
x
0
external on Multi Function
pins in Bus mode
r/w0:
Disable External Memory Access
DB0−DB7, WExQ and OExQ output pins
are tristate during internal memory
access (see Fig. 5–2 on page 89).
DB0−DB7, WExQ and OExQ output pins
are active during internal memory access.
MFM
r/w1:
r/w0:
Multi Function pin Mode
Enable normal mode.
Enable Test Bus mode.
TSTROM
r/w1:
r/w0:
Test ROM (mask ROM parts only)
Disable internal Test ROM.
Enable internal Test ROM (@ IROM=1).
IROM
r/w1:
r/w0:
Internal ROM
Enable internal CPU ROM.
Disable internal CPU ROM.
IRAM
r/w1:
r/w0:
Internal RAM
Enable internal CPU RAM.
Disable internal CPU RAM.
ICPU
r/w1:
r/w0:
Internal CPU
Enable internal CPU.
Disable internal CPU.
88
Table 5–4: TSTTOG and MFM usage
TSTTOG
MFM
TEST pin
Multi
Function
Pins
x
1
x
normal mode
1
0
1
normal mode
1
0
0
Bus mode
0
0
x
Bus mode
Micronas
VCT 38xxA
ADVANCE INFORMATION
PH2
internal signal
RW
internal signal
ADB
extern
extern
intern
intern
DB
Controlword
DISEXT= 1
OE
WE
DB
Controlword
DISEXT= 0
OE
WE
Fig. 5–2: Internal/external memory access
5.5. Standby Registers
The Standby registers allow the user to switch on/off
power or clock supply of single modules. With these
flags it is possible to greatly influence power consumption and its related electromagnetic interference.
For details about enabling and disabling procedures
and the standby state refer to the specific module
descriptions.
CCC
r/w1:
r/w0:
Capture Compare Counter
Module active.
Module off.
TVPWM
r/w1:
r/w0:
Tuning Voltage Pulse Width Modulator
Module active.
Module off.
The minimum IC current consumption is obtained with
all standby registers set to 00h.
7:
1F09
bit
7
r/w
4:
1F08
bit
7
r/w
reset
0
5:
SR0
6:
6
5
PWM1
PWM0
0
0
4
0
3
0
2
1
0
TRAM
CCC
TVPWM
0
0
0
PWM1
r/w1:
r/w0:
Pulse Width Modulator 1
Module active.
Module off.
PWM0
r/w1:
r/w0:
Pulse Width Modulator 0
Module active.
Module off.
TRAM
r/w1:
r/w0:
Text RAM
Module active
Module off
Micronas
reset
Standby Register 0
8:
SR1
6
9:
5
4
CPUFST
0
1
Standby Register 1
3
2
ADC
0
0
0
0
CPUFST
r/w1:
r/w0:
CPU Fast Mode
Fast mode: fCPU = fXTAL / 2
Slow mode: fCPU = fXTAL / 512
ADC
r/w1:
r/w0:
ADC Module
Module active.
Module off.
TIM1
r/w1:
r/w0:
Timer 1
Module active.
Module off.
TIM0
r/w1:
r/w0:
Timer 0
Module active.
Module off.
1
0
TIM1
TIM0
0
0
89
VCT 38xxA
10:
1F0A
bit
7
r/w
reset
0
PWM3
r/w1:
r/w0:
11:
ADVANCE INFORMATION
SR2
12:
6
5
PWM3
PWM2
4
0
0
Standby Register 2
3
2
1
I2C
0
0
0
0
22:
0
bit
MB
w
0
reset
Pulse Width Modulator 3
Module active.
Module off.
PWM2
r/w1:
r/w0:
Pulse Width Modulator 2
Module active.
Module off.
I2C
r/w1:
r/w0:
I2C-Bus Master Interface
Module active.
Module off.
MB
r/w1:
r/w0:
Memory Banking
Module active.
Module off.
25:
bit
7
TST1
6
5
16:
0
0
1FFF
bit
7
0
17:
TST2
6
5
4
4
3
2
1
0
0
0
1FFB
7
26:
0
0
5
4
TST5
6
0
0
0
0
27:
Test Register 5
3
2
1
0
0
0
0
For testing purposes only
0
0
0
0
0
5.7.1. Alarm Function
Test Register 1
3
0
18:
w
2
1
0
0
0
0
Test Register 2
3
2
1
0
0
0
0
The interrupt source output of this module is routed to
the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller.
Check section “Interrupt Controller” for the actually
selectable sources and how to select them.
The intended use of this function is made, when a system uses a 3.3V regulator with an unregulated input. In
this case, the unregulated input, scaled down by a
resistive divider, is fed to the RESQ pin. With falling
regulator input voltage this alarm interrupt is triggered
first. Then the reset threshold is reached and
VCT 38xxA is reset before the regulator drops out.
The time interval between the occurrence of the alarm
interrupt and the reset may be used to save process
data to nonvolatile memory. In addition, power saving
steps like turning off other devices may be taken to
increase the time interval until reset. The alarm interrupt is a level triggered interrupt. The interrupt is active
as long as the voltage on pin RESQ remains between
the two thresholds of alarm and reset (see Fig. 5–3 on
page 92).
For testing purposes only
reset
19:
0
5
Test Register 4
5.7. Reset Logic
For testing purposes only
reset
0
0
1FFD
bit
7
0
20:
6
reset
0
TST3
0
21:
5
w
90
4
6
24:
An alarm comparator on the pin RESQ allows the
detection of a threshold higher than the reset threshold. An alarm interrupt can be triggered with the output
of this comparator.
15:
w
TST4
For testing purposes only
reset
In all applications where a hardware reset may not
occur over long times, it is good practice to force a
software reset on these registers within appropriate
intervals.
14:
23:
r
Test registers are for manufacturing test only. They
must not be written by the user with values other than
their reset values (00h). They are valid independent of
the TEST input state.
1FFE
7
bit
5.6. Test Registers
13:
1FFC
4
Test Register 3
3
2
1
0
0
0
0
For testing purposes only
0
0
0
0
0
5.7.2. Software Reset
The TV controller software can generate a reset via
the Reset Control Register (see page 94). To prevent
the TV controller from carrying out a reset in this case,
the internal CPU reset can be disconnected from the
RESQ pin.
Micronas
ADVANCE INFORMATION
VCT 38xxA
5.7.2.1. From Standby into Normal Mode
To switch the whole TV application from standby operation into normal mode the controller has to perform
the following sequence:
– RC.RESDIS = 1, RC.DCOCLP = 1
– RC.RESOUT =1
– switch on power supply
– wait for stable power supply
– RC.SELCLK = 1, RC.I2CEN = 1
– RC.DCOCLP = 0, RC.RESOUT = 0
– wait for RC.ALI = 0 (ext. capacitor!)
– RC.RESDIS = 0
– init DMA interface
– init TPU, VDP and Audio
– init external devices
5.7.2.2. From Normal into Standby Mode
To switch the whole TV application from normal mode
into standby operation the controller has to perform the
following sequence:
– RC.DCOCLP = 1, RC.I2CEN = 0
– wait 1ms for stable 20.25MHz DCO
– RC.SELCLK = 0
– turn off power supply
– set TPU into standby mode
– SR0 = 2, SR1 = 8, SR2 = 0
5.7.3. Internal Reset Sources
The VCT 38xxA contains three internal circuits that are
able to generate a system reset: watchdog, supply
supervision, and clock supervision.
All internal resets are directed to the open drain output
of pin RESQ. Thus a “wired or” combination with external reset sources is possible. The RESQ pin is current
limited and therefore large external capacitances may
be connected.
All internal reset sources initially set a reset request
flag. This flag activates the pull-down transistor on the
RESQ pin. An internal reset prolongation counter
starts, as soon as no internal reset source is active any
more. It counts 4096 fCPU periods (for alternative settings refer to register CR) and then resets the reset
request flag, thus releasing the RESQ pin.
Micronas
91
VCT 38xxA
RESET
Interrupt
Source
>1
RC.VSI
Voltage
Supervision
RC.TPUI
TPU
Watchdog
RC.ALI
internal Reset to DMA, TPU, VDP
CPU Reset
>1
RC.RESDIS
VSUPD
VREFA
+
VREFA
VREFR
VREFPOR
+
Bandgap
ADVANCE INFORMATION
VREFR
RESQ
RC.RESOUT
Watchdog
>1
VREFPOR
VSUPS
S Q
>1
R
+
-
>1
&
RC
Clock
Supervision
Reset
Control
CSW0.CSA
&
Reset extension
16 or 4096
oscillator pulses
>1
reset
Fig. 5–3: Block diagram of reset logic
5.7.3.1. Supply Supervision
An internal bandgap reference voltage is compared to
VSUPS. A VSUPS level below the Supply Supervision
threshold VREFPOR will permanently pull the pin
RESQ low and thus hold the VCT 38xxA in reset state
(see Fig. 5–3 on page 92). This reset source is active
after reset and can be enabled/disabled by flag CSA in
register CSW0.
5.7.3.2. Clock Supervision
The Clock Supervision monitors the CPU clock frequency fCPU. A frequency level below the clock supervision threshold of approx. 200 kHz will permanently
pull the pin RESQ low and thus hold the IC in reset
(see Fig. 5–3 on page 92). This reset source is active
after reset and can be enabled/disabled by flag CSA in
register CSW0.
A frequency exceeding the specified clock frequency is
not detected.
92
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.7.3.3. Watchdog
The Watchdog module serves to monitor undisturbed
program execution. A failure of the program to retrigger
the Watchdog within a preselectable time will pull the
RESQ pin low and thus reset the VCT 38xxA (see Fig.
5–3 and Fig. 5–4). The Watchdog reset source is only
enabled after the first write access to register CSW1
(see Section 5.7.3.2. on page 92).
CSW1
2.write
& even
Trigger Reg1
3.write
& odd
Once the Watchdog is enabled, it cannot be disabled anymore, neither by software nor by pulling
down the external RESQ pin. Only after power up
the watchdog is disabled.
CSW1
CSW1
1. write
Trigger Reg2
8
Timer Register
8
8
clk = fCPU/8192
1. write
=
&
≥1
load
8-Bit-Counter
zero
&
2.write & even
3.write & odd
D Q
C
S
≥1
reset in
1. write
power on
write CSW1
S Q
R
≥1
reset out
&
S Q
R
CSW1.WDRES
Fig. 5–4: Block diagram of watchdog
The Watchdog contains a down-counter that generates a reset when it wraps from zero to FFh. It is
reloaded with the content of the watchdog timer register, when, on a write access to register CSW1, watchdog trigger registers 1 and 2 contain bit complemented
values. Resetting the VCT 38xxA initializes the watchdog timer register to FFh, thus forcing the Watchdog to
create a maximum reset interval.
The resolution of the Watchdog is 8192/fCPU. In CPU
Slow mode (see Section 5.2.1. on page 86), the watchdog is clocked with the reduced CPU clock.
The Watchdog is controlled by register CSW1. The
first write access to it loads the timer register value setting the Watchdog’s unretriggered reset interval. The
desired interval can be programmed by setting the
CSW1 value to:
In all future, the CPU has to write alternatingly to register CSW1 value and bit complement value, thus retriggering the up-counter. Failure to retrigger will result in
an overflow of the up-counter generating a Watchdog
reset.
Interval × f CPU
-–1
Value = ----------------------------------8192
The second and all following even numbered write
accesses load watchdog trigger register 1, the third
and all following odd numbered write accesses load
watchdog trigger register 2.
It is not allowed to change a chosen value. Writing a
wrong value to CSW1 immediately sets the flag
CSW1.WDRES and prohibits further retriggering of the
watchdog counter.
CSW1.WDRES is true after a Watchdog reset. Only a
Supply Supervision reset or a write access to register
CSW1 clears it.
Micronas
93
VCT 38xxA
ADVANCE INFORMATION
5.7.4. External Reset Sources
As long as the reset input comparator on the pin
RESQ detects the Low level, the VCT 38xxA is in reset
state. On this pin, external reset sources may be wireored with the internal reset sources, leading to a system-wide reset signal combining all system reset
sources.
5.7.5. Summary of Module Reset States
After reset, the controller modules are set to the following reset states:
Table 5–6: Status after reset
Module
Status
CPU
CPU Fast mode.
Interrupt
Controller
Interrupts are disabled. Priority registers, request flip-flops and stack
are cleared.
Ports
Normal mode. Output is tristate.
Watchdog
Switched off. SW activation is possible.
If the source of one of these interrupts is still active,
resetting the interrupt flag will not work and no further
interrupt will be generated.
I2CEN
r/w1:
r/w0:
I2C Enable
Enable I2C output from FE/BE.
Disable I2C output.
DCOCLP
r/w1:
r/w0:
DCO clamping
DCO input clamped to 0.
DCO input controlled by front-end.
SELCLK
r/w1:
r/w0:
Select clock source
From PLL.
From DCO.
RESDIS
r/w1:
r/w0:
Reset Disable
Disable internal CPU reset.
Enable internal CPU reset.
RESOUT
w1:
w0:
RESQ Output
RESQ output active.
RESQ output inactive.
31:
Clock
monitor
EMU IC: Active. SW may toggle.
normal IC: Permanently active.
1F00
32:
CSW0
33:
Clock, Supply & Watchdog Register 0
bit
7
6
5
4
3
2
1
0
w
x
x
x
x
x
x
x
CSA
reset
x
x
x
x
x
x
x
1
This register controls the Supply and Clock Supervision modules.
5.7.6. Reset Registers
28:
1F07
29:
RC
30:
4
Reset Control Register
bit
7
6
5
w
ALI
VSI
TPUI
I2CEN DCOCLP SELCLK RESDIS RESOUT
r
ALI
VSI
TPUI
I2CEN DCOCLP SELCLK RESDIS
reset
0
0
0
0
3
1
2
0
1
0
0
CSA
w1:
w0:
Clock and Supply Supervision Active
Both Enabled.
Both Disabled.
0
0
This register controls the reset logic and clock generation.
34:
1F60
35:
Alarm Interrupt
Alarm was interrupt source
no pending alarm interrupt
reset alarm interrupt
VSI
r1:
r0:
w1:
VSUPD Voltage Supervision Interrupt
VSUPD supervision was interrupt source
no pending VSUPD supervision interrupt
reset VSUPD supervision interrupt
TPUI
r1:
r0:
w1:
TPU Watchdog Interrupt
TPU watchdog was interrupt source
no pending TPU watchdog interrupt
reset TPU interrupt flag
94
36:
Clock, Supply & Watchdog Register 1
bit
7
6
5
4
3
2
1
0
r
x
x
x
x
x
x
x
WDRES
1
1
1
1
w
ALI
r1:
r0:
w1:
CSW1
reset
Watchdog Time and Trigger Value
1
1
1
1
This register controls the Watchdog module. Only values between 1 and 255 are allowed.
WDRES
r1:
w:
Watchdog Reset Source
Watchdog was reset source.
Any write access to CSW1 resets this
flag.
First write the desired watchdog time value to this register. On further writes, to retrigger the Watchdog,
alternatingly write a value (not necessarily the former
time value) and its bit complemented value. Never
change the latter value.
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.8. Memory Banking
*D0 ... D7
Banking
Register
A15 ... A19
Interrupt
Controller,
DMA
Logic
65C02
A15 ... A19
Address
Decoder,
Memory,
I/O
*A15
A0 ... A14
*A0 ... A14
A0 ... A14
*Processor internal Bus
Fig. 5–5: Block diagram of Memory Banking
The 8-bit processor W65C02 only allows access to
64 kByte of memory space. To allow access to the
expanded memory range above 64 kByte, a specific
banking hardware is implemented. The physical
address range above 32 kBytes (A15 = 1) is separated
into several banks of which only one at a time is
enabled and selected by the Banking register (BR),
which is programmable as any other standard peripheral register by writing the desired value into its specific address. The content of the BR is also readable,
so the software may check the current bank at any
time. The applied software is responsible to program
the BR with the correct bank number at the right time.
Since the upper 32 kBytes range is switched immediately after programming the BR, correct function is not
guaranteed if it is changed by a program sequence
running in a switched bank. BR settings need to be
done in the lower 32 kBytes (A15 = 0), which is the
non-switchable master bank (bank 0).
5.8.1. Banking Register
37:
1F0F
bit
7
38:
6
BR
39:
5
4
Banking Register
3
r/w
reset
BN
r/w:
2
1
0
0
1
BN
0
0
0
0
0
0
Bank Number
number of 32 kByte memory bank
Setting BN = 0 should be avoided because it will mirror
the non-switchable master bank (bank 0) into the
upper 32-kByte area (A15 = 1). RAM, I/O pages and
reserved addresses may be manipulated unintentionally.
RESET initializes BN = 1 to read control byte and reset
vector from bank 1. Also, interrupt vectors have to
reside in bank 1, because the Interrupt Controller generates the appropriate address of bank 1, but it does
not change the contents of the BR. Interrupt functions
have to reside in the non-switchable master bank
(bank 0). Otherwise,they need to be in each used
bank, because after getting the vector the unchanged
contents of the BR determine the current bank which is
valid if A15 is “1”.
Micronas
95
VCT 38xxA
ADVANCE INFORMATION
CPU RAM/ROM
Text RAM
TPU Address Space
≥128k Text RAM
000000H
0F8000H
0A8000H
000FFFH
reserved
0A0000H
088000H
002000H
080000H
DMA
078000H
Page
Table
001000H
001000H
001000H
Scratch
001800H
Page
Memory
Scratch
001800H
16kbyte
004000H
Page
Memory
128kbyte
020000H
256kbyte
040000H
ext. RAM
Page
Memory
003000H
OSD&TTX
Bank
OSD
Bank
512kbyte
int. RAM
Page
Table
003000H
00FFFFH
ext. ROM
Page
Table
TTX
Bank
087FFFH
int. ROM
000000H
002000H
084000H
008000H
16k Text RAM
000000H
Scratch
Bank 1
Bank 0
Bank 2
Bank 3
Bank 4
Bank 5-14
Bank 15
Bank 16
Bank 17-19
Bank 20
Bank 21-30
Bank 31
001E00H
19k Text RAM
000000H
004000H
OSD&TTX
Bank
07FFFFH
I/O-Reg
Fig. 5–6: Memory Banking shown with the maximal size of addressable memory
5.9. DMA Interface
The DMA interface connects the TPU SRAM interface
to the CPU memory bus (see Fig. 5–7). This is done to
avoid extra pins for external TPU page memory.
The DMA interface must not be operated during CPU
Slow mode. The DMA interface can be disabled via
DMAIM.DMAEN.
96
As long as the DMA interface is disabled, the TPU cannot access the CPU address bus and therefore should
not transfer data to/from the internal/external SRAM.
To ensure this, the controller should reset the TPU
before disabling the DMA interface. After reset the
TPU will not access the memory until receiving the I2C
command “DRAM_MODE” (see Section 3.12. on
page 68).
Micronas
VCT 38xxA
ADVANCE INFORMATION
A[18:0]
TPU
SRAM
Interface
PH2
Address
Mapping
D[7:0]
RWQ
DMA Interface
RDY
RWQ
BE
RWQ
DB[7:0]
CPU
ADB[19:0]
Fig. 5–7: Block diagram of DMA interface
In general, all TPU addresses are mapped into bank
16 to 31 of the CPU address space by forcing the MSB
of the address bus to “1” (see Fig. 5–8). Additionally
4 memory segments can be mapped into any address
area by programming a set of DMA registers (see
Fig. 5–9).
A[18:8]
A19 = “1”
Special care should be taken when mapping TPU
addresses into the RAM area of bank 0. Any overlap between TPU memory (e.g. OSD Bank) and
controller memory (e.g. non zero page variables)
must be avoided.
TPU Address Bus
map
4
map
3
match3
map
2
match2
map
1
12
12
match4
match1
12
Mux 1:5
12
12
3
Decoder
12
ADB[19:8]
Fig. 5–8: DMA address mapping
Micronas
97
VCT 38xxA
ADVANCE INFORMATION
If the mapping logic does not find any address match,
the TPU address is directly put on the CPU address
bus with A19 set to “1”. In case of multiple matches,
the priority is map1 > map2 > map3 > map4.
76:
79:
1E0C
1E0D
82:
85:
1E0F
bit
12
CMP n
1E0E
match
=
7
&
≥1
1
0
CA16
reset
1
1
1
1
88:
12
&
97:
1E10
1E11
1E12
1E13
44:
47:
50:
42:
MASK2L
45:
MASK3L
48:
MASK4L
51:
6
5
4
3
2
1
0
MPA14
MPA13
MPA12
MPA11
MPA10
MPA9
MPA8
reset
1
1
1
1
1
1
1
1
1E14
1E15
1E16
1E17
1
0
MA8
reset
1
1
1
1
1
1
1
1
112:
bit
7
60:
6
5
63:
4
2
1
0
Mask 1 High Byte
MAP3E
MAP2E
MAP1E
Mask 2 High Byte
reset
0
0
0
0
0
2
1
0
MA17
MA16
reset
1
1
1
1
MA19 to 8 Mask Address
TPU address is masked with this value.
67:
70:
73:
1E09
1E0A
1E0B
68:
71:
74:
66:
CMP2L
69:
CMP3L
72:
CMP4L
75:
DMAEN
w1:
w0:
DMA Enable
Enable DMA Interface
Disable DMA Interface
MAPxE
w1:
w0:
Mapping Logic x Enable
Enable mapping logic x
Disable mapping logic x
Compare 1 Low Byte
Compare 2 Low Byte
Compare 3 Low Byte
Compare 4 Low Byte
bit
7
6
5
4
3
2
1
0
w
CA15
CA14
CA13
CA12
CA11
CA10
CA9
CA8
reset
1
1
1
1
1
1
1
1
98
4
DMA Interface Mode
3
Mask 4 High Byte
5
114:
MAP4E
Mask 3 High Byte
6
DMAIM
DMAEN
MA18
CMP1L
113:
w
3
65:
1E18
7
MA19
1E08
Map 4 High Byte
3
bit
w
64:
111:
4
MPA19 to 8 Map Address
Matching TPU address is replaced with this value.
Mask 4 Low Byte
MA9
MASK4H
5
Map 3 High Byte
1
2
MASK3H
MAP4H
Map 2 High Byte
1
MA10
62:
108:
1
3
59:
6
105:
MAP3H
1
MA11
1E07
110:
MAP2H
Map 1 High Byte
reset
4
1E06
107:
102:
Mask 2 Low Byte
MA12
61:
104:
MAP1H
0
Mask 3 Low Byte
7
101:
MPA16
5
58:
Map 4 Low Byte
1
MA13
57:
Map 3 Low Byte
MPA17
6
54:
99:
2
MA14
MASK2H
96:
MAP4L
Map 2 Low Byte
MPA18
7
MASK1H
MAP3L
Map 1 Low Byte
MPA19
MA15
56:
93:
w
w
53:
98:
90:
MAP2L
Mask 1 Low Byte
bit
1E05
95:
MAP1L
7
106:
MASK1L
92:
MPA15
109:
41:
89:
w
bit
1E04
4
bit
103:
55:
Compare 4 High Byte
CA17
5.9.1. DMA Registers
52:
87:
2
100:
1E03
5
Compare 3 High Byte
CA18
Fig. 5–9: DMA mapping logic
49:
CMP4H
6
Compare 2 High Byte
3
A[19:8]
n: mapping logic 1 to 4
1E02
84:
CA19 to 8 Compare Address
Masked TPU address is compared with this value.
&
MAP n
46:
81:
CMP3H
CA19
94:
1E01
86:
CMP2H
Compare 1 High Byte
w
91:
43:
83:
78:
12
MASK n
1E00
80:
CMP1H
12
A[19:8]
40:
77:
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.10.Interrupt Controller
The Interrupt Controller has 16 input channels (see
Fig. 5–10 on page 100). Each input has its own interrupt vector pointing to an interrupt service routine
(ISR). One of 15 priority levels can be assigned to
each input or the input can be disabled. The Interrupt
Controller is connected to the NMI input of the CPU.
But despite of the non-maskable interrupt input, it is
possible to disable all interrupt sources in total in the
Interrupt Controller.
operates with the new vector of the interrupt service
routine.
When the Interrupt Controller writes the new vector to
the address bus, the interrupt pending flag of this vector is set, indicating that no interrupt is pending.
The software must pull the top entry from the priority
stack at the end of an interrupt service routine. This
happens with the write access to the interrupt return
register IRRET. Then the next entry (with lower priority) is visible at top of stack and is compared with the
priority latch.
5.10.1.Features
– 16 interrupt inputs.
– 16 interrupt vectors.
The Interrupt Controller and related circuitry is clocked
by the CPU clock and participates in CPU Fast and
Slow mode.
– 15 individual priority levels.
– Global/individual disable of interrupts.
5.10.3.Initialization
– Single interrupt service mode.
After reset, all internal registers are cleared but the
Interrupt Controller is active. When an interrupt
request arrives, it will be stored in the respective pending register IRP/IRRET. But it will not trigger an interrupt as long as its interrupt priority register IRPRIxy is
set to zero.
5.10.2.General
Interrupt requests are served in the order of their programmed priority level. Interrupt requests of the same
priority level are served in descending order of interrupt input number.
Each of the 16 interrupt inputs clears a flag in the interrupt pending register (IRRET and IRP), which can be
read by the user. A pending interrupt enables the output of the corresponding priority register (IRPRI10 to
IRPRIFE) which is connected to a parallel priority
decoder together with the other priority registers. The
decoder outputs the highest priority and its input number to a latch. The latched priority is compared with the
top entry of the priority stack. The top entry of the priority stack contains the priority of the actual served
interrupt. Lower entries contain interrupts with lower
priority whose interrupt service routines were started
but interrupted by the higher priority interrupts above. If
the latched priority is lower or equal than the top of
stack priority, nothing happens. If the latched priority is
higher than the top of stack priority, a NMI is sent to the
CPU and the latched priority is pushed on the stack.
The Interrupt Controller signals an interrupt by NMI
input to the CPU. After the current instruction is finished the CPU starts an interrupt sequence. First it
puts the program bank register, the program counter
High byte, the program counter Low byte and the program status register to the stack. Then the CPU writes
the vector address Low byte (00FFFAh) to the bus.
The Interrupt Controller recognizes this address and
stops the CPU by the RDY signal. Now the Interrupt
Controller writes the vector address Low and High byte
of the corresponding interrupt number to the bus and
releases the CPU by releasing RDY. The CPU now
Micronas
Proper SW configuration of the interrupt sources in
peripheral modules has to be made prior to operation.
Before enabling individual inputs, make sure that no
previously received signal on that input has cleared its
pending flag which may trigger the Interrupt Controller.
Clear all pending interrupts with the flag IRC.CLEAR to
avoid such an effect.
5.10.4.Operation
Activation of an interrupt input is done by writing a priority value ranging from 1h to Fh to the respective
IRPRIxy register. Upon an interrupt request, pending
or fresh, the Interrupt Controller will immediately generate an interrupt.
During operation, changes in the priority register setting may be made to obtain varying interrupt servicing
strategies.
Flags IRC.DAINT,
IRC.DINT and
IRC.A1INT allow some variation in the Interrupt Controller response behavior.
5.10.5.Inactivation
There are two possibilities to disable an interrupt within
the Interrupt Controller. Changing the priority of an
interrupt input to zero disables this interrupt locally.
Interrupts are globally disabled by writing a zero to flag
IRC.DINT of register IRC.
99
Priority
Registers
clke
IRPRI10
Int-Input 1
R
Q
S
Priority
Latch
clke
4
prio
CCUNMI
4
priority
A
VCT 38xxA
100
Pending
Register
CCUNMIDIS
A>B
B
Int-Input 2
R
Q
4
input #
4
4
S
&
push
IRPRI32
Int-Input 3
R
Q
Priority
Stack
15 x 4
4
pull
IRRET write
S
Int-Input 4
R
Q
4
S
Parallel
Priority
Decoder
NMI
clke
DMAE
RDY
Ctrl
00FFFA
IRPRIFE
Int-Input 15
R
Q
A
A=B
B
4
S
R
Q
4
Interrupt
Vector
Table
16
enable
A0...A23
S
16
Clear Request
Micronas
Fig. 5–10: Block diagram of interrupt logic
PATCH
DMAE
Ph2
&
clke
ADVANCE INFORMATION
Int-Input 16
VCT 38xxA
ADVANCE INFORMATION
Within the evaluation period (see Section 5.10.10. on
page 106) it’s not possible to suppress an interrupt by
changing priority.
A zero in the flag IRC.DINT of register IRC prevents
the Interrupt Controller from pulling the signal NMI
Low. However, if this flag is set after the falling edge of
NMI, the corresponding interrupt cannot be cancelled.
5.10.7.Interrupt Registers
115:
1F20
The write access to the IRRET must be performed just
before the RTI command at the end of the interrupt
service routine. After a write access to this location it is
guaranteed that the next command (should be RTI) will
be processed completely before a new interrupt
request is signaled to the CPU. If the RTI command
does not immediately follow the write to IRRET, an
interrupt with the same priority may be detected before
the corresponding RTI is processed. A stack underflow
may occur because this may happen several times.
If an opcode fetch of a disable interrupt instruction (DI)
happens one clock cycle after the falling edge of NMI
(see Section 5.10.10. on page 106), it is possible, that
an interrupt service routine (ISR) is active, though the
corresponding interrupt is disabled. That is why after
disabling an interrupt, and before accessing critical
data, at least one uncritical instruction is necessary.
This guarantees that the ISR is finished before critical
data access and no further ISR can interrupt it.
Because it is now possible that an ISR can lengthen
the time between DI and enable interrupt (EI) indefinitely, it is necessary that an ISR first saves registers
and enables interrupt flags, and then enables interrupts. After interrupt execution, enable flags and registers must be restored. This guarantees, that other
interrupts are not locked out during interrupt execution.
Save Registers
Execute Interrupt
Restore Registers
Write to IRRET
IRC
117:
Interrupt Control Register
7
6
5
4
3
2
1
r
x
x
x
x
DAINT
DINT
x
x
w
x
x
x
RESET
DAINT
DINT
A1INT
CLEAR
x
1
1
x
x
reset
5.10.6.Precautions
116:
bit
RESET
w1:
w0:
0
Reset
No action.
Momentary reset of the Interrupt Controller, all internal registers are cleared.
The reset of the Interrupt Controller happens with writing zero to this flag. It is not necessary to write a one to
finish the reset.
The standard interrupt controller function is performed
by setting all flags to one. A hardware reset of the
Interrupt Controller is performed by setting the RESET
flag to Low and the other flags to High.
DAINT
r1:
r0:
w1:
w0:
Disable after interrupt
Don’t disable after interrupt.
Disable Interrupt Controller after interrupt.
Cancel this feature.
Disable Interrupt Controller after interrupt.
This is the enable flag for the flag A1INT function.
DINT
r1:
r0:
w1:
w0:
Disable interrupt
Interrupts are enabled.
All interrupts are disabled.
Enable interrupts according to priority setting.
Disable all interrupts.
A1INT
w1:
w0:
Allow one interrupt
No action.
Serve one interrupt.
This is a momentary signal. With DAINT = 0, only one
interrupt (with the highest priority) will be served.
The Flags DAINT and A1INT must be considered in
common. They provide the possibility to serve interrupts one by one, only when the main program has
enough time.
CLEAR
w1:
w0:
Clear all requests
No action.
Momentarily clears all interrupt requests.
RTI
Fig. 5–11: Interrupt service routine
Micronas
101
VCT 38xxA
ADVANCE INFORMATION
Table 5–7: Single interrupt service
133:
DAINT
A1INT
Resulting Function
0
1
Disable after current interrupt.
0
0
Serve one interrupt request.
1
x
Normal interrupt mode.
1F26
bit
134:
7
IRPRI98
6
r/w
0
1F27
bit
118:
r
w
1F21
119:
IRRET
120:
Interrupt Return Register
6
5
4
3
2
1
0
IPF7
IPF6
IPF5
IPF4
IPF3
IPF2
IPF1
IPF0
A write access signals the Interrupt Controller that the current request has
been served.
reset
0
IPF0 to 7
r1:
r0:
w:
0
0
0
0
0
0
0
Interrupt Pending Flag of Input 0 to 7
No interrupt is pending.
Interrupt is pending.
Current request is finished.
For interrupt pending flags 8 to 15 refer to description
of register IRP.
A write access to this memory location signals to the
Interrupt Controller that the current request has been
served.
139:
bit
1F22
7
122:
IRPRI10
6
r/w
reset
124:
bit
0
127:
bit
0
1F23
0
125:
130:
bit
7
6
0
0
102
3
2
0
0
126:
0
0
1F24
7
128:
5
4
3
2
0
0
0
0
1F28
bit
140:
7
129:
5
1F25
7
0
131:
4
3
2
IRPRI76
5
0
132:
0
0
0
0
0
1F29
bit
143:
Interrupt Priority Register, Input
10 and 11
4
0
141:
5
3
2
7
reset
0
0
3
2
0
144:
5
0
0
0
PRIOn
r:
0
0
1
0
0
0
Interrupt Priority Register, Input
14 and 15
4
3
2
PRIO15
0
0
Interrupt Priority Register, Input
12 and 13
4
0
6
1
PRIO12
IRPRIFE
r/w
0
PRIO10
IRPRIDC
0
0
1
0
0
0
PRIO14
0
0
0
0
Priority of interrupt input n
Priority of the corresponding interrupt
input.
Priority of the corresponding interrupt
input.
Priority zero prevents the Interrupt Controller from
being triggered but the pending register is not affected.
All incoming requests are stored in the pending registers. With two inputs having the same PRIO setting,
the higher numbered input has priority.
1
0
0
0
Table 5–8: PRIOn usage
PRIOn
Resulting Function
0h
Interrupt input is disabled
1h
Interrupt input is enabled with lowest priority
1
0
:
:
0
0
Fh
Interrupt input is enabled with highest priority
Interrupt Priority Register, Input 6
and 7
4
3
2
PRIO7
0
0
0
PRIO13
reset
0
PRIO4
0
6
0
Interrupt Priority Register, Input 4
and 5
PRIO5
0
0
138:
0
6
1
PRIO2
IRPRI54
6
1
2
Interrupt Priority Register, Input 2
and 3
PRIO3
r/w
reset
4
PRIO0
IRPRI32
r/w
reset
5
0
5
0
Interrupt Priority Register, Input 0
and 1
PRIO1
r/w
reset
123:
3
PRIO11
w:
121:
0
6
r/w
142:
4
PRIO8
IRPRIBA
137:
7
reset
7
5
0
r/w
bit
Interrupt Priority Register, Input 8
and 9
PRIO9
reset
136:
135:
1
0
0
0
PRIO6
0
0
0
0
Micronas
VCT 38xxA
ADVANCE INFORMATION
145:
1F2A
146:
IRP
147:
Interrupt Pending Register
bit
7
6
5
4
3
2
1
0
r
IPF15
IPF14
IPF13
IPF12
IPF11
IPF10
IPF9
IPF8
reset
0
0
0
0
0
0
0
0
The source can be any of the 15 special input ports
(see Section 5.18.1. on page 126). The multiplexers
are configured by registers IRPMUX0 and IRPMUX1.
IPF8 to 15 Interrupt Pending Flag of Input 8 to 15
r1:
No interrupt is pending.
r0:
Interrupt is pending.
For interrupt pending flags 0 to 7 refer to description of
register IRRET.
5.10.8.Interrupt Assignment
While most interrupt assignments are hard-wired,
some can be configured by software (see Fig. 5–12 on
page 104).
Table 5–9: Interrupt assignment
Interrupt
Input
Interrupt
Vector Address
Interrupt
Source
0
00FFF6−F7
I2C
1
00FFF4−F5
T0
2
00FFF2−F3
T1
3
00FFF0−F1
CCCOFL
4
00FFEE−EF
CC0OR
5
00FFEC−ED
CC0COMP
6
00FFEA−EB
CC1OR
7
00FFE8−E9
CC1COMP
8
00FFE6−E7
TVPWM
9
00FFE4−E5
VSYNC
10
00FFE2−E3
RESET
11
00FFE0−E1
CMPO
12
00FFDE−DF
PINT0
13
00FFDC−DD
PINT1
14
00FFDA−DB
PINT2
15
00FFD8−D9
PINT3
5.10.8.1. Interrupt Multiplexer
Interrupt inputs 0−11 are directly connected to the
respective module’s interrupt output. Four interrupt
inputs 12 to 15 allow source selection via multiplexers.
Micronas
103
VCT 38xxA
ADVANCE INFORMATION
Interrupt sources
of peripheral
modules
12
IRPP.P0INT4
IRPM0
0
PINT0
Interrupt
1/4
1
Mux 0
Controller
IRPP.P1INT32
0
Trigger
Mode
PINT1
Special
Input
Ports
15
Mux 1
1/32
1
PINT2
Mux 2
PINT3
Mux 3
Fig. 5–12: Interrupt assignment and multiplexer
5.10.9.Port Interrupt Module
Table 5–10: PITn usage
Port interrupts are the interface of the Interrupt Controller to the external world. Four port pins are connected to the module via their special input lines. Port
interrupt 0 and 1 can scale down the interrupt load by
prescalers. Port interrupt 2 and 3 are directly connected to the special input multiplexer.
The user can define the trigger mode for each port
interrupt by the interrupt port mode register. The Port
interrupt prescaler can be switched by the interrupt
port prescaler register. The pulse duty factor of the
prescaler output is 50 %.
PITn
Trigger Mode
0h
Interrupt source is disabled
1h
Rising edge
2h
Falling edge
3h
Rising and falling edges
151:
The Trigger mode defines on which edge of the interrupt source signal the Interrupt Controller is triggered.
The triggering of the Interrupt Controller is shown in
Fig. 5–13 and Fig. 5–14 for port prescaler active
(P1INT32 or P0INT4 = 1).
148:
1F2B
bit
7
w
reset
PITn
149:
6
IRPM0
5
PIT3
0
150:
4
0
3
2
1
PIT1
0
152:
IRPP
153:
Interrupt Port Prescaler
7
6
5
4
3
2
w
x
x
x
x
x
x
1
0
P1INT32 P0INT4
reset
0
P1INT32
w1:
w0:
Port 1 interrupt prescaler
Indirect mode, 1:32 prescaler
Direct mode, bypass prescaler
P0INT4
w1:
w0:
Port 0 interrupt prescaler
Indirect mode, 1:4 prescaler
Direct mode, bypass prescaler
0
Interrupt Port Mode
PIT2
0
1F2C
bit
0
0
PIT0
0
0
0
Port interrupt trigger n
This field defines the trigger behavior of the associated
port interrupt.
104
Micronas
VCT 38xxA
ADVANCE INFORMATION
154:
bit
1E71
7
155:
IRPMUX0
6
w
reset
5
156:
Interrupt Port Multiplex 0
4
3
2
PISIP1
0
0
1
157:
0
bit
PISIP0
0
0
0
0
1E72
158:
7
IRPMUX1
6
w
0
0
reset
159:
5
Interrupt Port Multiplex 1
4
3
2
PISIP3
0
0
PISIPn
1
0
0
0
PISIP2
0
0
0
0
Port interrupt special input port n
This field defines the special input port connected to
the associated port interrupt (see Table on page 126).
Port Px.y
1
2
3
4
1
2
3
4
1
2
3
4
1/4 prescaler output
Independent
of trigger mode
Interrupt
(low active)
Falling edge
Interrupt
(low active)
Rising edge
Interrupt
(low active)
Falling and rising
edge trigger mode
Fig. 5–13: Interrupt timing (1/4 Prescaler On)
Port Px.y
32
1
2
15
16
17
18
31
32
1/32
prescaler output
Independent
of trigger mode
Interrupt
(low active)
Falling edge trigger
Interrupt
(low active)
Rising edge trigger
Interrupt
(low active)
Falling and rising
edge trigger mode
Fig. 5–14: Interrupt timing (1/32 Prescaler On)
Micronas
105
VCT 38xxA
ADVANCE INFORMATION
5.10.10.Interrupt Timing
Evaluation needs one clock cycle until the Interrupt
Controller pulls the signal NMI Low.
The interrupt response time is calculated from the
interrupt event up to the first interrupt vector on the
address bus (see Fig. 5–15 on page 106).
After the falling edge of NMI the CPU finishes the
actual command. If the falling edge of NMI happens
one clock cycle before an opcode fetch, the following
command will be finished too. Then PC and status will
be saved on stack before the Low byte of the interrupt
vector is written to the address bus.
After an interrupt event, the Interrupt Controller starts
evaluation with the first falling edge of PH2.
Interrupt
Finish actual command and save status.
(Save status = 5 clocks).
PH2
Interrupt
Request
NMI
A0...23
00FFFA
DMA
Vector 1st Byte Vector 2nd Byte Opcode ISR
RDY
Clear
Request
Interrupts
enabled
DMAE
Fig. 5–15: Interrupt timing diagram
106
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.11.Memory Patch Module
The Memory Patch Module allows the user to modify
up to ten hard-wired ROM locations by external
means. This function is useful if faulty parts of software
or data are detected after the ROM code has been
cast into mask ROM.
Software loads addresses and the corrected code e.g.
from external non-volatile memory into respective
registers of the module. The module then will replace
faulty code upon address match.
Single ROM locations are directly replaced. Longer
faulty sequences may be repaired by introducing a
jump to a new subroutine in RAM (e.g. opcode JSR
requires 3 consecutive bytes to be patched). The RAM
subroutine then may consist of any number of instructions, ending with a return to the next correct instruction in ROM. In such a way it is possible to include also
complex software modules.
5.11.1.Features
– patching of read data from up to 10 different ROM
locations (24 bit physical address)
– automatic insertion of 1 CPU wait state for each
patched access
ADB[23:0]
DB[7:0]
Write/Compare
Enable
PA[7:0]
Patch Address Register
PA[15:8]
Patch Data Register
PA[23:16]
Output Enable
PATOE
≡
DBP[7:0]
PH2
PSEL9...0
Patch Enable Register
PMEN
Patch Cell 0
≥1
Sequencer
&
RDY
ROMEN
Patch Cells 1...9
RWQ
ROMACC
Fig. 5–16: Block diagram of patch module
5.11.2.General
5.11.3.Initialization
The logic contains ten patch cells (see Fig. 5–16 on
page 107), each consisting of a 24-bit compare register (Patch Address register, PARn), a 24-bit address
comparator, a Patch Enable register (PERn) bit and an
8-bit Patch Data register (PDR).
After reset, as bit PER0.PMEN is reset to 0, all patch
cell registers are in Write mode and patch operation is
disabled.
The current address information for a ROM access is
fed to a bank of ten patch cells. In case of a match in
one patch cell, and provided that the corresponding
Patch Enable register bit is set, a wait cycle for CPU is
included by pulling down the RDY input of CPU for one
cycle (see Fig. on page 108). In the meantime the
module’s logic disables the ROM data bus drivers and
instead places the data information from the corresponding Patch Data register on the data bus.
Micronas
To initialize a patch cell, first set the corresponding
PSEL bit in register PER0 or PER1 as a pointer. Then
enter the 24bit address to registers PAR2 (High byte),
PAR1 (middle byte) and PAR0 (Low byte) and the
desired patch code to register PDR.
If desired, repeat the above sequence for other patch
cells. Only set one PSEL pointer bit in registers PER0
and PER1 at a time.
107
VCT 38xxA
ADVANCE INFORMATION
5.11.5.Patch Registers
5.11.4.Patch Operation
To activate a number of properly initialized patch cells
for ROM code patching, set all the corresponding
PSEL bits in registers PER1, then PER0, setting bit
PER0.PMEN to 1.
The Memory Patch Module will immediately start comparing the current address to the setting of the enabled
patch cells. In case of a match, the ROM data will be
replaced by the corresponding patch cell data register
setting.
To reconfigure the Memory Patch Module, first set
PER0.PMEN to 0. The module will immediately terminate patch operation.
160:
DB[7:0]
A2
D1
A2
D2
A3
A3
PD1
D3
PATOE
Patch Address Register 0
5
4
3
2
1
0
w
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
reset
1
1
1
1
1
1
1
1
163:
1E65
PAR1
164:
165:
Patch Address Register 1
bit
7
6
5
4
3
2
1
0
w
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
reset
1
1
1
1
1
1
1
1
1E66
PAR2
167:
168:
Patch Address Register 2
bit
7
6
5
4
3
2
1
0
w
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
reset
1
1
1
1
1
1
1
1
PD2
169:
RDY
162:
6
166:
ADB[23:0] A1
PAR0
161:
7
.
PH2
1E64
bit
1E67
170:
PDR
171:
Patch Data Register
bit
7
6
5
4
3
2
1
0
w
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
reset
0
0
0
0
0
0
0
0
ROMEN
172:
Fig. 5–17: Patch timing
1E68
173:
PER0
174:
Patch Enable Register 0
bit
7
6
5
4
3
2
1
0
w
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
PSEL0
PMEN
reset
0
0
0
0
0
0
0
0
175:
1E69
176:
PER1
177:
Patch Enable Register 1
bit
7
6
5
4
3
2
1
0
w
x
x
x
x
x
PSEL9
PSEL8
PSEL7
reset
x
x
x
x
x
0
0
0
PA23 to 0 Patch Address
Upon occurrence of this address the patch cell
replaces ROM data with data from PDR.
PD7 to 0
Patch Data
Data to replace false ROM data at certain address.
PSEL0 to 9 Select Patch Cell
w1:
select cell for write or enable for patch
w0:
disable patch cell
Before writing compare address or replace data of a
patch cell, only one cell must be selected. In compare
mode one or more patch cells can be selected.
PMEN
w1:
w0:
108
Patch Mode Enable
enable patch mode of all cells
enable write mode of all cells
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.12.I2C-Bus Master Interface
The I2C bus interface is a pure Master system, Multimaster busses are not realizable. The clock and data
terminal pins have open-drain outputs.
The I2C bus master interface can operate on two terminals. Terminal 1 is connected to the pins SDA/SCL,
terminal 2 can be connected either to the pins
P36/P37 or to the pins P22/P23. Please refer to chapter 5.18. on page 126 how to set up the corresponding
port pins.
The I2C bus master interface is not affected by CPU
Slow mode.
The bit rate is programmable using a clock prescaler.
A complete telegram is assembled by the software out
of individual sections. Each section contains an 8-bit
data. This data is written into one of the six possible
Write registers. Depending on the chosen address, a
certain part of an I2C bus cycle is generated. By
means of corresponding calling sequences it is therefore possible to join even very long telegrams (e.g.
long data files for auto increment addressing of I2C
slaves).
The software interface contains a 5 word deep WriteFIFO for the control data registers, as well, as a 3 word
deep Read FIFO for the received data. Thus most of
the I2C telegrams can be transmitted to the hardware
without the software having to wait for empty space in
the FIFO.
If telegrams longer than 3 bytes (1 address, 2 data
bytes) are received, the software must check the filling
condition of the Write-FIFO and, if necessary, fill it up
(or read out the Read-FIFO). A variety of status flags is
available for this purpose:
– The ‘half full’ flag I2CRS.WFH is set if the WriteFIFO is filled with three bytes.
– The ‘empty’ flag I2CRS.RFE is set if there is no
more data available in the Read-FIFO.
– The ‘busy’ flag I2CRS.BUSY is activated by writing
any byte to any one of the Write registers. It stays
active until the I2C bus activities are stopped after
the stop condition generation.
Moreover, the ACK-bit is recorded separately on the
bus lines for the address and the data fields. However,
the interface itself can set the address ACK=0. In any
case the two ACK flags show the actual bus condition.
These flags remain until the next I2C start condition is
generated.
For example, the software has to work off the following
sequence (ACK=1) to read a 16-bit word from an I2C
device address 10H (on condition that the bus is not
active):
– write 021H to
I2CWS0
– write 0FFH to
I2CWD0
– write 0FFH to
I2CWP0
– read RFE bit from
I2CRS
– read dev. address from I2CRD
An interrupt is generated on two conditions:
– read RFE bit from
– The Write-FIFO was filled and reaches the ‘half full’
state.
– read 1st data byte from I2CRD
– The Write-FIFO is empty and stop condition is completed.
– read 2nddata byte from I2CRD
All address and data fields appearing on the bus are
constantly monitored and written into the Read-FIFO.
The software can then check these data in comparison
with the scheduled data. If a read instruction is handled, the interface must set the data word FFH, so that
the responding slave can insert its data. In this case
the Read-FIFO contains the read-in data.
– read RFE bit from
I2CRS
I2CRS
The value 21H in the first step results from the device
address in the 7 MSBs and the R/W-bit (read=1) in the
LSB. If the telegrams are longer, the software has to
ensure that neither the Write-FIFO nor the Read-FIFO
can overflow.
– To write data to this device:
– write 20H to
I2CWS0
– write 1st databyte to
I2CWD0
– write 2nd databyte to
I2CWP0
The bus activity starts immediately after the first write
to the Write-FIFO. The transmission can be synchronized by an artificial extension of the Low phase of the
clock line. Transmission is not continued until the state
of the clock line is High once again. Thus, an I2C slave
device can adjust the transmission rate to its own abilities.
Micronas
109
VCT 38xxA
ADVANCE INFORMATION
WR_Data (subaddress=control info)
Address
Decoder
D0 to D7
WR
0
Clock Prescaler
Write
FIFO
5 x 11
half full
1
clk = fOSC
SR2.I2C
empty
Terminal 1
SDA/SCL
control
2
in
out
SR
Write Logic
2
busy
Terminal 2
P22/P23
P36/P37
Read Logic
Read
FIFO
3x8
Start Condition
resets ACK flags
empty
Q
Q
ADR_ACK
RD_Data
S R
DAT_ACK
D0 to D7
S R
Status Register
I2C
Interrupt
Source
D0 to D7
RD_Status
Fig. 5–18: Block diagram of I2C bus master interface
110
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.12.1.I2C Bus Master Interface Registers
1T
178:
SDA
1FD0
bit
7
179:
I2CWS0
6
5
w
1/2T
1/4T
1T
3
2
1
0
0
0
0
0
0
0
0
0
Writing this register moves I2C start condition, I2C
Address and ACK=1 into the Write FIFO.
Fig. 5–19: Start condition I2C bus
181:
1FD1
bit
7
182:
I2CWS1
6
5
w
183:
I2C Write Start Register 1
4
3
2
1
0
0
0
0
I2C Address
reset
1T
I2C Write Start Register 0
I2C Address
reset
SCL
180:
4
0
0
0
0
0
Writing this register moves I2C start condition, I2C
Address and ACK=0 into the Write FIFO.
SDA
repeated
8 times
SCL
184:
1FD2
bit
1/4T
1/2T
1/4T
Fig. 5–20: Single bit on I2C bus
7
I2CWD0
6
5
w
reset
I2C Write Data Register 0
3
2
1
0
0
0
0
0
0
0
0
0
Writing this register moves I2C Data and ACK=1 into
the Write FIFO.
187:
1FD3
7
188:
I2CWD1
6
5
w
189:
4
I2C Write Data Register 1
3
2
1
0
0
0
0
I2C Data
reset
SCL
186:
4
I2C Data
bit
SDA
185:
0
0
0
0
0
Writing this register moves I2C Data and ACK=0 into
the Write FIFO.
1/4T
3/4T
190:
2
Fig. 5–21: Stop condition I C bus
1FD4
bit
7
191:
I2CWP0
6
5
w
192:
4
I2C Write Stop Register 0
3
2
1
0
0
0
0
I2C Data
reset
0
0
0
0
0
Writing this register moves I2C Data, ACK=1 and I2C
stop condition into the Write FIFO.
193:
1FD5
bit
7
194:
I2CWP1
6
5
w
reset
195:
4
I2C Write Stop Register 1
3
2
1
0
0
0
0
I2C Data
0
0
0
0
0
Writing this register moves I2C Data, ACK=0 and I2C
stop condition into the Write FIFO.
Micronas
111
VCT 38xxA
ADVANCE INFORMATION
Table 5–11: I2C Bit Rates
196:
1FD6
bit
7
197:
I2CRD
6
5
r
198:
I2C Read Data Register
4
3
2
1
0
SPEED
Bit Rate
0
0
0
0
0
19.776 Kbit/s
1
2.531 Mbit/s
2
1.266 Mbit/s
3
844 Kbit/s
4
633 Kbit/s
...
...
127
19.931 Kbit/s
I2C Data
reset
0
0
0
0
Reading this register returns the content of the Read
FIFO.
199:
1FD7
200:
I2CRS
201:
I2C Read Status Register
bit
7
6
5
4
3
2
1
r
x
OACK
AACK
DACK
BUSY
WFH
RFE
x
reset
0
0
0
0
0
0
0
0
OACK
r:
“OR”ed Acknowledge
AACK || DACK
AACK
r:
Address Acknowledge
Acknowledge state of address field
DACK
r:
Data Acknowledge
Acknowledge state of data field
BUSY
r1:
r0:
Busy
I2C Master Interface is busy
I2C Master Interface is not busy
WFH
r1:
r0:
Write-FIFO Half Full
Write-FIFO is filled with 3 Bytes
Write-FIFO is not half full
RFE
r1:
r0:
Read-FIFO Empty
Read-FIFO is empty
Read-FIFO is not empty
202:
1FDB
bit
7
w
TERM
reset
1
203:
6
I2CM
5
204:
4
3
2
1
0
0
0
0
0
0
1
0
SPEED
w:
Speed Select
I2C Bit Rate = fOSC / (4 * SPEED)
1E73
7
206:
6
I2CPS
5
207:
4
I2C Port Select Register
3
2
1
w
reset
112
Special Input Port Select
use port pair P36, P37 for terminal 2
use port pair P22, P23 for terminal 2
SPEED
Terminal Select
Terminal 1
Terminal 2
205:
SIPS
w1:
w0:
I2C Mode Register
TERM
w1:
w0:
bit
0
0
SIPS
0
0
0
0
0
0
0
0
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.13.Timer T0 and T1
5.13.1.Features
Timer T0 and T1 are 16-bit auto reload down counters.
They serve to deliver a timing reference signal, to output a frequency signal or to produce time stamps.
– 16-bit auto reload counter
– Time value readable
– Interrupt source output
– Frequency output
TIM x
w
fOSC/21
Reload-reg.
0
3:1
MUX
fOSC/29
clk
17
fOSC/2
TIMxM.CSF
r
2
16
1
16 bit Auto-reload
Down counter
TIM x
Tx
Interrupt
Source
zero
SR1.TIMx
1/2
Tx-OUT
Fig. 5–22: Block diagram of timer T0 and T1
5.13.2.Operation
The timer’s 16-bit down-counter is clocked by the input
clock and counts down to zero. Reaching zero, it generates an output pulse, reloads with the content of the
TIMx reload register and restarts its travel.
T0 and T1 are not affected by CPU Slow mode.
The clock input frequency can be selected from three
possible values by programming the timer mode register TIMxM.CSF. After reset, both timers are in standby
mode (inactive).
Prior to entering active mode, proper SW initialization
of the Ports assigned to function as Tx-OUT outputs
has to be made. The ports have to be configured Special Out (see Section 5.18. on page 126).
The interrupt source output of this module is routed to
the Interrupt Controller logic (see Section 5.10. on
page 99).
The state of the down-counter is readable by reading
the 16-bit register TIMx, Low byte first. Upon reading
the Low byte, the High byte is saved to a temporary
latch, which is then accessed during the subsequent
High byte read.
Thus, for time stamp applications, read consistency
between Low and High byte is guaranteed.
Returning a timer to standby mode by resetting the
corresponding Enable bit will halt its counter and will
set its output to Low. The register TIMx remains
unchanged.
To initialize a timer, Reload register TIMx has to set to
the desired time value, still in standby mode. For entering active mode, set the corresponding enable bit in
the Standby register. The timer will immediately start
counting down from the time value present in register
TIMx.
During active mode, a new time value is loaded by writing to the 16-bit register TIMx, High byte first. Upon
writing the Low byte, the reload register is set to the
new 16-bit value, the counter is reset, and immediately
starts down-counting with the new value.
On reaching zero, the counter generates a reload signal, which can be used to trigger an interrupt. The
same signal is connected to a divide by two scaler to
generate the output signal Tx-OUT with a pulse duty
factor of 50 %.
Micronas
113
VCT 38xxA
ADVANCE INFORMATION
5.13.3.Timer Registers
1F4E
208:
211:
209:
1F4C
bit
212:
7
r
6
TIM0L
210:
TIM1L
5
213:
4
Timer 0 Low Byte
Timer 1 Low Byte
3
2
1
0
Read Low Byte of down-counter and latch High Byte.
w
Write Low Byte of reload value and reload down-counter.
reset
1
1F4F
214:
217:
1
215:
1F4D
bit
218:
7
6
r
1
1
TIM0H
216:
TIM1H
5
1
219:
4
1
1
1
Timer 0 High Byte
Timer 1 High Byte
3
2
1
0
1
1
Read latched High Byte of down-counter.
w
Write High Byte of reload value.
reset
1
1
1
1
1
1
TIMx have to be read Low byte first and written High
byte first.
220:
223:
1F11
221:
1F13
bit
224:
7
6
TIM0M
222:
TIM1M
5
225:
4
3
Timer 0 Mode
Timer 1 Mode
2
1
r/w
reset
CSF
r/w:
0
CSF
0
0
0
0
0
0
0
0
Clock Selection Field
Source of timer clock (see Table 5–12)
Table 5–12: CSF usage
CSF
Clock
Divider
Timer
Clock
Timer
Increment
Timer
Period
00
fOSC/21
5.0625 MHz
197.53 ns
12.945 ms
01
fOSC/29
19.775 KHz
50.568 µs
3.3140 s
77.248 Hz
12.945 ms
848.39 s
1x
114
17
fOSC/2
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.14.Capture Compare Module (CAPCOM)
5.14.1.Features
The Capture Compare Module (CAPCOM) is a complex relative timer. It comprises a free running 16-bit
Capture Compare Counter (CCC) and 2 Capture Compare Subunits (SU). The CCC provides an interrupt on
overflow and the timervalue can be read by software.
– 16-bit free running counter with read out.
A SU is able to capture the relative time of an external
event input and to generate an output signal when the
CCC passes a predefined timer value. Three types of
interrupts enable interaction with SW. Special functionality provides an interface to the asynchronous external world.
– Output action: toggle, Low or High level.
CCCS.CSF
– 16-bit capture register.
– 16-bit compare register.
– Input trigger on rising, falling or both edges.
– Three different interrupt sources: overflow, input,
compare
– Designed for interfacing to asynchronous external
events
2
fOSC/20
fOSC/24
fOSC/28
fOSC/212
0
4:1
Mux
clk
CCCOFL
Interrupt
Source
CCC
1
Timer Value
SR0.CCC
ofl
16
2
2
CC0I
1
CC0-IN
CC0-OUT
7
0 0
0 1
1 0
1 1
Input Action Logic
3
CC0M
CAP CMP OFL LAC RCR
0
6
5
4
X
3
X
2
X
1
MSK MSK MSK FOL
0
7
6
5
4
OAM
3
IAM
2
1
0
&
&
CC0OR
Interrupt
Source
&
2
Low
0 0
TOGGLE 0 1
1 0
1 1
Output Action Logic
>1
>1
16
A
reset
load
Subunit 0
16-Bit Capture-Register
r
16-Bit Compare-Register
w
CC0
16
Subunit 1
CC1-OUT
B
CC0COMP
Interrupt
Source
16
Timer Value
CC1-IN
=
ofl
CC1OR
Interrupt
Source
CC1COMP
Interrupt
Source
Fig. 5–23: Block diagram of CAPCOM module
Micronas
115
VCT 38xxA
ADVANCE INFORMATION
5.14.2.Initialization
5.14.3.1. Operation of Subunit
After system reset the CCC and all SUs are in standby
mode (inactive).
For a proper setup the SW has to program the following SU control bits in registers CCxI and CCxM: Interrupt Mask (MSK), Force Output Logic (FOL, 0 recommended), Output Action mode (OAM), Input Action
mode (IAM), Reset Capture register (RCR, 0 recommended), and Lock After Capture (LAC). Refer to section 5.14.5. for details.
In standby mode, the CCC is reset to value 0000h.
Capture and compare registers CCx are reset. No
information processing will take place, e.g. update of
interrupt flags. However, the values of registers CCxI
and CCxM are only reset by system reset, not by
standby mode. Thus, it is possible to program all mode
bits in standby mode and a predetermined start-up out
of standby mode is guaranteed.
Prior to entering active mode, proper SW configuration
of the Ports assigned to function as Input Capture
inputs and Output Action outputs has to be made. The
Output Action ports have to be configured as Special
Out and the Input Capture ports as special in (see
Section 5.18. on page 126).
Please note, that the compare register CCx is reset in
standby mode. It can only be programmed in active
mode.
5.14.3.Operation of CCC
Each SU is able to capture the CCC value at a point of
time given by an external input event processed by an
Input Action Logic.
A SU can also change an output line level via an Output Action Logic at a point of time given by the CCC
value.
Thus, a SU contains a 16-bit capture register CCx to
store the input event CCC value, a 16-bit compare register CCx to program the Output Action CCC value, an
8-bit interrupt register CCxI and an 8-bit mode register
CCxM. Two types of interrupts per SU enable interaction with SW.
For limitations on operating the CAPCOM module in
CPU Slow mode, see section 5.14.3.1.15. on
page 117.
For entering active mode of the entire CAPCOM module set, the enable bit in the standby register.
The CCC will immediately start up-counting with the
selected clock frequency and will deliver this 16-bit
value to the SUs.
The state of the counter is readable by reading the 16bit register CCC, Low byte first. Upon reading the Low
byte, the High byte is saved to a temporary latch,
which is then accessed during the subsequent High
byte read. Thus, for time stamp applications, read consistency between Low and High byte is guaranteed.
The CCC is free running and will overflow from time to
time. This will cause generation of an overflow interrupt event. The interrupt (CCCOFL) is directly fed to
the Interrupt Controller and also to all SUs where further processing takes place.
116
5.14.3.1.13. Compare and Output Action
To activate a SUs compare logic the respective 16-bit
compare register CCx has to be programmed, Low
byte first. The compare action will be locked until the
High byte write is completed. As soon as CCx setting
and CCC value match, the following actions are triggered:
– The flag CMP in the CCxI register is set.
– The CCxCOMP interrupt source is triggered.
– The CCxOR interrupt source is triggered when activated.
– The Output Action logic is triggered.
Four different reactions are selectable for the Output
Action signal: according to field CCxM.OAM (Table
5–17) the equal state will lead to a High or Low
level, or toggling or inactivity on this output.
Another means to control the Output Action is bit
CCxM.FOL. E.g. rise-mode and force will set the
output pin to High level, fall-mode and force to Low
level. This forcing is static, i.e. it will be permanently
active and may override compare events. Thus, it is
recommended to set and reset shortly after that, i.e.
to pulse the bit with SW. Toggle mode of the Output
Action logic and forcing leads to a burst with clockfrequency and is not recommended.
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.14.3.1.14. Capture and Input Action
The Input Action logic operates independently of the
Output Action logic and is triggered by an external
input in a way defined by field CCxM.IAM. Following
Table 5–18 it can completely ignore events, trigger on
rising or falling edge or on both edges. When triggered, the following actions take place:
– Flag CCxI.CAP is set.
– The CCxOR interrupt source is triggered when activated.
– The 16-bit capture register CCx stores the current
CCC value, i.e. the “time” of the external event.
Read CCx Low byte first. Further compare action
will be locked until the subsequent High byte read is
completed. Thus a coherent result is ensured, no
matter how much time has elapsed between the two
reads.
Some applications suffer from fast input bursts and a
lot of capture events and interrupts in consequence. If
the SW cannot handle such a rate of interrupts, this
could evoke stack overflow and system crash. To prevent such fatal situations the Lock After Capture (LAC)
mode is implemented. If bit CCxI.LAC is set, only one
capture event will pass. After this event has triggered a
capture, the Input Action logic will lock until it is
unlocked again by writing an arbitrary value to register
CCxM. Make sure that this write only restores the
desired setting of this register.
Programming the Input Action logic while an input transition occurs may result in an unexpected triggering.
This may overwrite the capture register, lock the Input
Action logic if in LAC mode and generate an interrupt.
Make sure that SW is prepared to handle such a situation.
parator equal state (maskable ored and non-maskable
direct).
All interrupt sources act independently, parallel interrupts are possible. The interrupt flags enable SW to
determine the interrupt source and to take the appropriate action. Before returning from the interrupt routine the corresponding interrupt flag should thus be
cleared by writing a 1 to the corresponding bit location
in register CCxI.
The interrupts generated by internal logic (CCC Overflow and Comparator equal) will trigger in a predetermined and known way. But as explained in 5.14.3.1.14.
erroneous input signals may cause some difficulties
concerning the Input Capture input, as well, as interrupt handling. To overcome possible problems the
Input Capture Interrupt flag CCxI.CAP is double buffered. If a second or even more input capture interrupt
events occur before the interrupt flag is cleared (i.e.
SW was not able to keep track), the flag goes to a third
state. Two consecutive writes to this bit in register CCxI
are then necessary to clear the flag. This enables SW
to detect such a multiple interrupt situation and eventually to discard the capture register value which always
relates to the latest input capture event and interrupt.
The internal CAPCOM module control logic always
runs on the oscillator frequency, regardless of CPU
Slow mode. Avoid write accesses to the CCxI register
in CPU Slow mode, since the logic would interpret one
CPU access as many consecutive accesses. This may
yield unexpected results concerning the functionality of
the interrupt flags. The following procedure should be
followed to handle the capture interrupt flag CAP:
1. SW responds to a CAPCOM interrupt, switching to
CPU Fast mode if necessary and determining that
the source is a capture interrupt (CAP flag =1).
For testing purposes, a permanent reset (FFFFh) may
be forced on capture register CCx by setting bit
CCxI.RCR. Make sure that the reset is only temporary.
2. The interrupt service routine is processed.
5.14.3.1.15. Interrupts
4. The service routine reads CAP again. If it is reset,
the routine can return to main program as usual. If it
is still set an external capture event overrun has
happened. Appropriate actions may be taken (i.e.
discarding the capture register value etc.).
Each SU supplies two internal interrupt events:
1. Input Capture event and
2. Comparator equal state.
3. Just before returning to main program, the service
routine acknowledges the interrupt by writing a 1 to
flag CAP.
5. go to 3.
As previously explained, interrupt events will set the
corresponding flags in register CCxI. In addition to the
above mentioned two, the CCC Overflow interrupt
event sets flag CCxI.OFL in each SU. Thus, three
interrupt events are available in each SU. The corresponding flags are masked with their mask bits in register CCxM and passed to a logical or. The result
(CCxOR) is fed to the Interrupt Controller as a first
interrupt source. In addition, the Comparator equal
(CCxCOMP) interrupt is directly passed to the Interrupt Controller as second interrupt source. Thus a SU
offers four types of interrupts: CCC overflow (maskable
ored), input capture event (maskable ored) and com-
Micronas
5.14.4.Inactivation
The CAPCOM module is inactivated and returned to
standby mode (power down mode) by setting the
Enable bit to 0. Section 5.14.2. applies. CCxI and
CCxM are only reset by system reset, not by standby
mode.
117
VCT 38xxA
ADVANCE INFORMATION
5.14.5.CAPCOM Registers
226:
1F7C
bit
227:
7
CCCL
6
5
r
228:
CAPCOM Counter Low Byte
4
3
2
1
0
0
0
This flag is static. As long as FOL is true neither comparator can trigger nor SW can force, by writing
another “one”, the Output Action logic. After forcing it is
recommended to clear FOL unless Output Action logic
should not be locked.
Read Low Byte and lock CCC.
reset
229:
0
0
1F7D
bit
230:
7
0
CCCH
6
5
r
0
231:
0
0
CAPCOM Counter High Byte
4
3
2
1
0
0
0
0
0
0
0
0
0
The CAPCOM module counter has to be read Low
byte first to avoid inconsistencies.
232:
1F14
bit
233:
7
CCCS
6
5
234:
4
2
IAM
r/w:
Input Action Mode
Defines behavior of Input Action logic.
OAM
Output Action Logic Modes
00
Disabled, ignore trigger, output Low level.
01
Toggle output.
0
10
Output Low level.
0
11
Output High level.
CAPCOM Clock Select
3
Output Action Mode
Defines behavior of Output Action logic.
Table 5–17: OAM usage
Read High Byte and unlock CCC.
reset
OAM
r/w:
1
w
CSF
reset
0
0
0
0
0
0
0
CSF
Clock Selection Field
w:
Source of CCC clock (see Table 5–16)
Table 5–16: CSF usage
Table 5–18: IAM usage
IAM
Input Action Logic Modes
Clock
Divider
Timer
Clock
Timer
Increment
Timer
Period
00
Disabled, don’t trigger.
00
fOSC/20
10.125 MHz
98.765 ns
6.4727 ms
01
Trigger on rising edge.
01
fOSC/24
632.81 KHz
1.5802 µs
103.56 ms
10
Trigger on falling edge.
10
fOSC/28
39.551 KHz
25.284 µs
1.6570 s
11
Trigger on rising and falling edge.
2.4719 KHz
404.54 µs
26.512 s
CSF
12
11
235:
fOSC/2
1F6C
238:
1F70
236:
239:
CC0M
237:
CC1M
240:
bit
7
6
5
4
r
MSK
MSK
MSK
FOL
reset
0
0
0
0
MSK
w1:
w0:
CAPCOM 0 Mode Register
CAPCOM 1 Mode Register
3
2
1
OAM
0
0
IAM
0
0
0
Mask Flag
Enable.
Disable.
These mask flags refer to the corresponding event
flags in CAPCOM interrupt register.
FOL
r/w1:
r/w0:
118
Force Output Action Logic
Force Output Action logic.
Release Output Action logic.
Micronas
VCT 38xxA
ADVANCE INFORMATION
241:
1F6D
242:
1F71
244:
245:
CC0I
243:
CC1I
246:
CAPCOM 0 Interrupt Register
CAPCOM 1 Interrupt Register
bit
7
6
5
4
3
2
1
0
r/w
CAP
CMP
OFL
LAC
RCR
x
x
x
reset
0
0
0
0
0
0
0
0
CAP
r1:
r0:
w1:
Capture Event
Event.
No Event.
Clear flag.
CMP
r1:
r0:
w1:
Compare Event
Event.
No Event.
Clear flag.
OVL
r1:
r0:
w1:
Overflow Event
Event.
No Event.
Clear flag.
LAC
r/w1:
r/w0:
Lock After Capture
Enable.
Disable.
RCR
r/w1:
r/w0:
Reset Capture Register
Reset capture register to FFFFh.
Release capture register.
247:
1F6E
250:
bit
248:
1F72
7
251:
CC0L
CC1L
6
r
249:
252:
CAPCOM 0 Capture/Compare Low
Byte
CAPCOM 1 Capture/Compare Low
Byte
5
4
3
2
1
0
Read Low Byte of capture register and lock it.
w
Write Low Byte of compare register and lock it.
reset
253:
256:
bit
1
1
1F6F
254:
1F73
7
r
1
257:
CC0H
CC1H
6
1
255:
258:
1
1
1
1
CAPCOM 0 Capture/Compare High
Byte
CAPCOM 1 Capture/Compare High
Byte
5
4
3
2
1
0
Read High Byte of capture register and unlock it.
w
Write High Byte of compare register and unlock it.
reset
259:
bit
1
1E70
7
1
260:
CCIMUX
6
w
reset
1
5
1
261:
1
1
CCSIPn
0
1
CAPCOM Input Multiplex Register
4
3
2
CCSIP1
0
1
1
0
0
0
CCSIP0
0
0
0
0
CAPCOM Special Input Port n
This field defines the special input port connected to
the associated SU (see Table on page 126).
Micronas
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VCT 38xxA
ADVANCE INFORMATION
5.15.Pulse Width Modulator
5.15.1.Features
Each of the 4 available PWMs is an 8-bit reload downcounter with fixed reload interval. It serves to generate
a frequency signal with variable pulse width or, with an
external low-pass filter, as a digital to analog converter.
– 8-bit resolution
– standby mode
PWMx
w
0
fOSC/29
fOSC/21
Pulse Width Register
load
1
0
x: PWM number 0 to 3
y: Standby Register 0 or 2
8
clk
1
1
S
zero
8 bit down counter
Q
PWMx
R
0
SRy.PWMx
Fig. 5–1: Block diagram of 8-bit PWM
5.15.2.General
A PWM’s 8-bit down-counter is clocked by its input
clock and counts down to zero. Reaching zero, it stops
and sets the output to Low. A load pulse reloads the
counter with the content of the PWM register, restarts
it and sets the output to High. The repetition rate is
19.775 KHz, the reload period is 50.57 µs.
Returning a PWM to standby mode by resetting its
respective enable flag will immediately set its output
Low.
The state of the down-counters is not readable.
5.15.5.PWM Registers
The PWMs are not affected by CPU Slow mode. It is
recommended that the CPU should not write the PWM
registers during Slow mode.
262:
265:
268:
5.15.3.Initialization
Prior to entering active mode, proper SW initialization
of the Ports assigned to function as PWMx outputs has
to be made. The ports have to be configured Special
Out (see Section 5.18. on page 126).
5.15.4.Operation
After reset, all PWMs are in standby mode (inactive)
and the output signal PWMx is Low.
For entering active mode, the enable bit in the corresponding standby register has to be set (see Section
5.5. on page 89). The desired pulse width value is then
written into register PWMx. Each PWM will start producing its output signal immediately after the next subsequent load pulse.
During active mode, a new pulse width value is set by
simply writing to the register PWMx. Upon the next
subsequent load pulse the PWM will start producing
an output signal with the new pulse width value, starting with a High level.
120
271:
1F50
1F51
1F52
1F53
bit
7
263:
266:
269:
272:
PWM0
264:
PWM1
267:
PWM2
270:
PWM3
6
273:
5
4
w
reset
PWM 0 Register
PWM 1 Register
PWM 2 Register
PWM 3 Register
3
2
1
0
0
0
0
Pulse width value
0
0
0
0
0
Table 5–19: Pulse Width Programming
Pulse width value
Pulse duty factor
00h
0% (Output is static Low)
01h
1/256
02h
2/256
:
:
FEh
254/256
FFh
100% (Output is static High) 1)
1
) Pulse duty factor 255/256 is not selectable.
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.16.Tuning Voltage Pulse Width Modulator
The Tuning Voltage Pulse Width Modulator (TVPWM),
in combination with an external low pass filter, serves
as a digital to analog converter to control voltage synthesis tuning. It can also be operated as a normal 8-bit
PWM.
0
1
fOSC/2
clk
1
8 bit PWM Counter
5.16.1.Features
– 14bit resolution
– standby mode
load
6 bit Frame Counter
8
SR0.TVPWM
6
Comparator
Extension Logic
8
w
TVPWMH Register
TVPWM
Interrupt
Source
6
TVPWML Register
pulse
pwm
≥1
TVPWM
Fig. 5–2: Block Diagram of 14bit Tuning Voltage PWM
5.16.2.General
The TVPWM is based on an 8-bit PWM built by a
counter and a programmable comparator (see Fig. 5–
2). The overflow of the counter reloads the comparator
with the content of the TVPWMH register and sets the
TVPWM output to High. Matching the counter value,
the comparator sets the TVPWM output to Low. The
counter is continually running, producing PWM cycles
with a length of 256 T.
An interrupt is generated after completion of a frame of
64 reload cycles. The interrupt source output of this
module is routed to the Interrupt Controller logic (see
Section 5.10. on page 99).
The TVPWM is not affected by CPU Slow mode. It is
recommended that the CPU should not write the
TVPWM registers during Slow mode.
Depending on the content of the TVPWML register, the
6-bit pulse extension logic will add additional single
clock pulses distributed over a frame of 64 reload
cycles (see Fig. 5–3). This gives 14-bit resolution
when integrating over a complete frame. The frame
rate is 309 Hz, the frame period is 3.24 ms.
1T
cycle n
256 T
cycle n+1
256 T
Fig. 5–3: TVPWM Timing
Micronas
121
VCT 38xxA
ADVANCE INFORMATION
5.16.3.Initialization
Prior to entering active mode, proper SW initialization
of the Ports assigned to function as TVPWM output
has to be made. The ports have to be configured Special Out (see Section 5.18. on page 126).
5.16.4.Operation
After reset, the TVPWM is in standby mode (inactive)
and the output signal TVPWM is Low.
For entering active mode, the enable bit in the corresponding standby register has to be set (see Section
5.5. on page 89). The desired pulse width value is then
written into the registers TVPWML and TVPWMH. The
TVPWM will start producing its output signal immediately after the next subsequent load pulse.
During active mode, a new pulse width value is set by
simply writing to the register TVPWML and TVPWMH.
Writing TVPWMH will update the comparator and the
extension logic with the new register values. Upon the
next subsequent load pulse the TVPWM will start producing an output signal with the new pulse width value,
starting with a High level.
Returning the TVPWM to standby mode by resetting
its respective enable flag will not reset its output signal.
The state of the counters and the extension logic is not
readable.
5.16.5.TVPWM Registers
274:
1F4A
bit
275:
7
TVPWML
6
5
276:
4
w
3
2
1
0
0
0
Pulse width value Low
reset
277:
TV PWM Low Byte
0
1F4B
bit
7
278:
TVPWMH
6
5
w
reset
0
0
279:
4
0
TV PWM High Byte
3
2
1
0
0
0
0
Pulse width value High
0
0
0
0
0
TVPWM has to be written Low byte first.
122
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.17.A/D Converter (ADC)
5.17.1.Features
This 10-bit analog to digital converter allows the conversion of an analog voltage in the range of 0 to URef
into a digital value. A multiplexer connects the ADC to
one of 15 analog input ports. A sample-and-hold circuit
holds the analog voltage during conversion. The duration of the sampling time is programmable. The A/D
conversion is done by a charge balance A/D converter
using successive approximation.
– A/D converter with 10-bit resolution.
– Successive approximation, charge balance type.
– Input multiplexer with 15 analog channels.
– Sample and hold circuit.
– 4/8/16/32 µs conversion selectable for optimum
throughput/accuracy balance.
– Zero standby current, 300 µA active current.
SR1.ADC
0
VSUPS
1
4
GNDS
P10-17
P20-26
A
15
MUX
S&H
10
D
2
AD1
AD0
TSAMP
CHANNEL
x
r
7
6
9
5
8
4
7
3
6
2
5
1
4
0
3
7
2
EOC
CMPO
6
x
5
x
4
w
x
3
r
2
1
0
1
0
CMPO
Interrupt
Source
Fig. 5–4: Block Diagram of the ADC
5.17.2.Operation
After reset, the module is off (zero standby current).
The module is enabled by the flag SR1.ADC. The user
must ensure that the flag End of Conversion (EOC) in
register AD0 is true, before he starts to operate the
module.
A write access to register AD0 indicating sample time
and channel number starts the conversion. The flag
EOC signalizes the end of conversion. The 10-bit
result is stored in the registers AD1 (8 MSB) and AD0.
The conversion rate depends on the software, the
oscillator frequency and the programmed sample time.
The ADC module is not affected by CPU Slow mode.
Micronas
123
VCT 38xxA
ADVANCE INFORMATION
5.17.3.Measurement Errors
The result of the conversion mirrors the voltage potential of the sampling capacitance (typically 15 pF) at the
end of the sampling time. This capacitance has to be
charged by the source through the source impedance
within the sampling time period. To avoid measurement errors, system design has to make sure that at
the end of the sampling period, the potential error on
the sampling capacitance is less than ±0.1 LSB.
Measurement errors may occur, when the voltage of
high-impedance sources has to be measured:
– To reduce these errors, the sampling time may be
increased by programming the field TSAMP in register AD1.
– In cases where high-impedance sources are only
rarely sampled, a 100-nF capacitor from the input to
GNDS is a sufficient measure to ensure that the
potential on the sampling capacitance reaches the
full source potential, even with the shortest sampling
time.
– In some high-impedance applications a charge
pumping effect may influence the measurement
result when two sources are measured alternatingly.
5.17.4.Comparator
In addition to the A/D converter the module contains a
comparator. The level at the A/D converter input is
compared to VSUPS/2. The state of the comparator
output can be read at flag CMPO in register AD0.
The interrupt source output of this module is routed to
the Interrupt Controller logic. The CMPO interrupt
source is gated with an internal clock. This is the reason why interrupts are generated as long as the level
at the comparator is lower than the internal reference.
124
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.17.5.ADC Registers
Table 5–21: ADC input multiplexer
A write access to register AD0 starts the A/D conversion of the written channel number and sampling duration. The flag EOC signals the end of conversion. The
result is stored in register AD1 (bit 9 to 2) and in register AD0 (bit 1 and 0).
280:
1FA8
281:
AD0
282:
CHANNEL
Port Pin
0
none
1
P10
2
P11
ADC Register 0
bit
7
6
5
4
3
2
1
0
3
P12
r
EOC
CMPO
x
x
x
x
AN1
AN0
4
P13
0
5
P14
6
P15
7
P16
8
P17
9
P20
10
P21
11
P22
12
P23
13
P24
14
P25
15
P26
w
TSAMP
reset
283:
0
CHANNEL
0
1FA9
0
284:
0
AD1
0
285:
0
0
ADC Register 1
bit
7
6
5
4
3
2
1
0
r
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
reset
EOC
r1:
r0:
End of Conversion
End of conversion
Busy
EOC is reset by a write access to the register AD0.
EOC must be true before starting the first conversion
after enabling the module by setting SR1.ADC.
CMPO
r1:
r0:
Comparator Output
Input is lower than reference voltage.
Input is higher than reference voltage.
TSAMP
Sampling Time
AN 9 to 0
TSAMP adjusts the sample time and the conversion
time. The total conversion time is 20 clock cycles
longer than the sample time. Sampling starts one clock
cycle after completion of the write access to AD0.
Analog Value Bit 9 to 0
The 10 bit analog value is in the range of 0 to 1023.
The 8 MSB can be read from register AD1. The two
LSB can be read from register AD0. The result is available until a new conversion is started.
Table 5–20: Sampling time adjustment
TSAMP
tSample
tConversion
0H
20 TOSC
40 TOSC
1H
60 TOSC
80 TOSC
2H
140 TOSC
160 TOSC
3H
300 TOSC
320 TOSC
CHANNEL Channel of Input Multiplexer
CHANNEL selects from which port pin the conversion
is done. The MSB of CHANNEL is bit 3. No port pin is
connected to the ADC if the channel 0 is selected. In
this case the input of the A/D converter is connected to
ground. After reset, CHANNEL is set to zero.
Micronas
125
VCT 38xxA
ADVANCE INFORMATION
5.18.Ports
Table 5–23: Port pin configuration
There exist different kinds of ports. The universal
ports, P1 to P3, serve as digital I/O and have additional special input and output functions. A subset of
the universal ports (P10-P17, P20-P26) serves as
input for the analog-to-digital converter. The I2C ports
SDA, SCL can alternatively be used as digital I/O
ports. The analog audio ports AIN1−3, AOUT1−2 can
alternatively be used as digital input ports. The
20.25 MHz system clock output CLK20 can alternatively be used as digital output port.
5.18.1.Port Assignment
Table 5–23 shows the assignment of port pins to Special Input and Output functions.
Every Special Output function is connected to 2 port
pins in parallel and can be activated via the MOD flag
in the corresponding port register.
The ADC input multiplexer can be connected to 1 of 15
port pins. The output driver of the selected port pin is
then forced to open-drain mode. Additionally it can be
disabled using the EN flag in the corresponding port
register.
Every special input function can be connected to 1 of
15 input ports (see Table 5–22). If port number 0 is
selected the special input function is connected to
ground. Changing the input port may produce temporary glitch signals. Therefore, the corresponding special input function should be disabled before the input
port is changed.
Table 5–22: Special input configuration
Special
Input
Number
Special
Input
Function
Special
Input
Port
1
CC0−IN
0−15
2
CC1−IN
0−15
3
PINT0
0−15
4
PINT1
0−15
5
PINT2
0−15
6
PINT3
0−15
126
Port
Name
ADC
Input
Special
Output
Special
Input Port
P10
1
Timer 0
1
P11
2
Timer 1
2
P12
3
CC0−OUT
3
P13
4
CC1−OUT
4
P14
5
TVPWM
5
P15
6
PWM 0
6
P16
7
PWM 1
7
P17
8
PWM 2
8
P20
9
PWM 3
9
P21
10
CLK20
10
P22
11
SDA 2
11
P23
12
SCL 2
12
P24
13
Timer 0
P25
14
Timer 1
P26
15
CC0−OUT
P27
CC1−OUT
P30
TVPWM
P31
PWM 0
P32
PWM 1
P33
PWM 2
P34
PWM 3
P35
CLK20
P36
SDA 2
P37
SCL 2
P40
SDA
P41
SCL
P42
AOUT1
P43
AOUT2
P44
AIN1
P45
AIN2
14
P46
AIN3
15
13
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.18.2.1. Features
5.18.2.Universal Ports P1 to P3
– digital I/O port
There are 24 universal port pins. The universal ports
P1 to P3 are each 8 bits wide. In the 64-pin PSDIP
package only 12 universal port pins are available
(P10−P17, P20−P23).
– special input and output function
– analog input function
– Schmitt trigger input buffer
– tristate output
– push-pull or open-drain output
– 10-mA output current
– output supply either 3.3 V or 5.0 V
ADC In x.y
VDD
PxD read
DBy
VSS
Special In x.y
PxVDD
1
Special Out x.y
Px.y
0
Q
D
PxD write
PxVSS
Q
D
PxM
Q
D
PxE
Q
D
x: Port number 1 to 3
y: Port pin number 0 to 7
PxO
Fig. 5–5: Universal port circuit
Universal ports can be operated in different modes:
Table 5–24: Universal ports operating modes
Modes
Port Mode
Function
Normal Input
The SW uses the ports as digital input.
Special Input
The port input is additionally connected to specific hardware modules.
Normal Output
The SW uses the ports as latched digital tristate output.
Special Output
The port output is directly driven by specific hardware modules.
After reset, all Universal Ports are in normal mode, tristate condition.
Micronas
127
VCT 38xxA
ADVANCE INFORMATION
5.18.2.2. Universal Port Mode
286:
Each port bit can be individually configured to several
port modes. The output driver of each pin has to be
enabled by setting the EN flag. Using the OUT flag the
output stage can be configured to either open drain or
push pull output. The MOD flag selects the source of
the output value.
Table 5–25: Port mode register settings
Mode
MOD
EN
D
Function
Normal
Input
x
0
x
READ of register
PxD returns port
pin input levels to
data bus.
Normal
Output
0
1
Data
WRITE to register
PxD changes level
of port pin output
drivers.
READ of register
PxD returns the
PxD register setting to the data
bus.
Special
Input
x
x
x
289:
292:
1
1
x
READ of register
PxD returns port
pin input levels to
data bus.
The Special Input mode is always active. This allows
manipulating the input signal to the special hardware
through Normal Output operations by software.
128
291:
P3D
293:
294:
Port 2 Data Register
Port 3 Data Register
7
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
reset
0
0
0
0
0
0
0
0
D0−7
r:
w:
Universal Port Data Input/Output
Read pin level resp. data latch.
Write data to data latch.
To use a port pin as software output, the appropriate
driver must be activated by setting the EN flag and the
MOD flag must be programmed to Normal mode.
295:
298:
301:
1F91
P1O
296:
1F95
P2O
299:
1F99
297:
300:
P3O
302:
303:
Port 1 Output Register
Port 2 Output Register
Port 3 Output Register
bit
7
6
5
4
3
2
1
0
w
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
reset
0
0
0
0
0
0
0
0
OUT0−7
w1:
w0:
307:
310:
Output Flag
Output driver is open drain
Output driver is push pull
1F92
305:
1F96
308:
1F9A
311:
P1M
306:
P2M
309:
P3M
312:
Port 1 Mode Register
Port 2 Mode Register
Port 3 Mode Register
bit
7
6
5
4
3
2
1
0
w
MOD7
MOD6
MOD5
MOD4
MOD3
MOD2
MOD1
MOD0
reset
0
0
0
0
0
0
0
0
MOD0−7
w1:
w0:
Normal/Special Mode Flag
Special Output Mode
Normal Output Mode
The MOD flag defines from which source the pin is
driven if the EN flag is true.
313:
316:
Universal Port Data registers PxD contain input/output
data of the corresponding port. The “x” in PxD means
the number of the port. Thus PxD stands for P1D to
P3D.
P2D
290:
1F98
Port 1 Data Register
D7
As the Special Output mode allows reading the pin levels, the output state of the special hardware may be
read by the CPU.
5.18.3.Universal Port Registers
1F94
288:
bit
Port pin input level
is presented to
special hardware.
Special hardware
drives port pin.
P1D
287:
r/w
304:
Special
Output
1F90
319:
1F93
314:
1F97
317:
1F9B
320:
P1E
315:
P2E
318:
P3E
321:
Port 1 Enable Register
Port 2 Enable Register
Port 3 Enable Register
bit
7
6
5
4
3
2
1
0
w
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
reset
0
0
0
0
0
0
0
0
EN0−7
w1:
w0:
Enable Flag
Output driver is enabled
Output driver is disabled
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.18.4.I2C Ports P40 and P41
5.18.4.1. Features
The I2C ports SDA and SCL can alternatively be used
as digital I/O ports. To activate the I2C function of the
port pin the corresponding MOD flag has to be set to
special mode. In normal mode the port pin serves as
digital I/O. The output stage is open-drain only. After
reset, the I2C ports are in special mode.
– digital I/O port
– I2C input and output function
– Schmitt trigger input buffer
– open-drain output
– connected to standby supply
VDD
P4D read
DB0/DB1
VSS
1
SDA/SCL In
VDD
0
1
SDA/SCL Out
P40
P41
Q
0
D
P4D write
VSS
Q
D
P4M
Q
D
P4E
Fig. 5–6: I2C port circuit
322:
1F9C
bit
7
r
323:
.
P4D
324:
6
5
AIN3D
AIN2D
0
0
4
Port 4 Data Register
3
2
AIN1D AOUT2D AOUT1D
w
reset
0
0
325:
1
0
bit
SCLD
SDAD
SCLD
SDAD
0
0
0
SCLD
r:
w:
SCL Data Input/Output
Read pin level resp. data latch.
Write data to data latch.
SDAD
r:
w:
SDA Data Input/Output
Read pin level resp. data latch.
Write data to data latch.
Micronas
7
326:
P4M
327:
6
5
w
AIN3M
AIN2M
reset
1
1
4
Port 4 Mode Register
3
2
AIN1M AOUT2M AOUT1M
1
0
0
1
0
SCLM
SDAM
1
1
SCLM
w1:
w0:
SCL Normal/Special Mode Flag
Special I2C Output Mode
Normal Output Mode
SDAM
w1:
w0:
SDA Normal/Special Mode Flag
Special I2C Output Mode
Normal Output Mode
328:
To use the I2C ports as software output, the appropriate drivers must be activated by setting the SCLEN
and SDAEN flag and resetting the SCLM and SDAM
flags.
1F9E
1F9F
bit
7
329:
6
P4E
330:
5
4
Port 4 Enable Register
1
0
w
3
SCLEN
SDAEN
reset
1
1
SCLEN
w1:
w0:
SCL Enable Flag
Output driver is enabled
Output driver is disabled
SDAEN
w1:
w0:
SDA Enable Flag
Output driver is enabled
Output driver is disabled
2
129
VCT 38xxA
ADVANCE INFORMATION
5.18.5.Audio Ports P42 to P46
5.18.5.1. Features
The analog audio ports AIN1−3, AOUT1−2 can alternatively be used as digital input ports. To activate the
audio function of the port pin, the corresponding MOD
flag has to be set to Special mode. In Normal mode the
port pin serves as digital input. After reset the audio
ports are in Normal mode.
– analog audio input or output
– digital input port
– Schmitt trigger input buffer
– special input function
VDD
P4D read
DBy
VSS
Special In 4.y
1
Audio
P4.y
0
Q
y: Port pin number 2 to 6
D
P4M
Fig. 5–7: Audio port circuit
AINxD
r:
AINx Data Input
Read pin level resp. data latch.
AOUTxD
r:
AOUTx Data Input
Read pin level resp. data latch.
To use the Audio ports as software input, the corresponding flags must be programmed to Normal Input
mode.
AINxM
w1:
w0:
AINx Normal/Special Mode Flag
Special Audio Input Mode
Normal Input Mode
AOUTxM
w1:
w0:
AOUTx Normal/Special Mode Flag
Special Audio Output Mode
Normal Input Mode
130
Micronas
VCT 38xxA
ADVANCE INFORMATION
5.18.6.CLK20 Output Port
5.18.6.1. Features
The CLK20 pin delivers the internal 20.25-MHz clock.
The output stage is push-pull with programmable
driver strength (C20M.DSTR). The CLK20 pin can
alternatively be used as digital output port. It is possible to force the CLK20 output either to High or Low
(C20M.FSO) or to switch it into tristate mode
(C20M.DOD). After reset, the CLK20 port is enabled.
– programmable driver strength
– tristate mode
– digital output port
VDD
CLK20
CLK20
VSS
6
DB
C20M
Fig. 5–8: CLK20 Port Circuit
331:
1F9D
bit
7
332:
6
C20M
w
reset
333:
5
4
FSO
0
0
CLK20 Mode Register
3
2
DOD
0
0
1
0
DSTR
w000:
w111:
Driver Strength
Output driver strong
Output driver weak
DOD
w1:
w0:
Disable Output Driver
Output driver is high-impedance
Output driver is enabled
FSO
w10:
w11:
Force Static Output
Output driver is forced to 1
Output driver is forced to 0
Micronas
0
DSTR
0
0
131
VCT 38xxA
ADVANCE INFORMATION
5.19.I/O Register Cross Reference
Table 5–26: I/O Register Map
Addr.
Mnemonic
Name
Mode
Reset
1E00
MASK1L
Mask 1 Low Byte
w
FF
1E01
MASK2L
Mask 2 Low Byte
w
FF
1E02
MASK3L
Mask 3 Low Byte
w
FF
1E03
MASK4L
Mask 4 Low Byte
w
FF
1E04
MASK1H
Mask 1 High Byte
w
FF
1E05
MASK2H
Mask 2 High Byte
w
FF
1E06
MASK3H
Mask 3 High Byte
w
FF
1E07
MASK4H
Mask 4 High Byte
w
FF
1E08
CMP1L
Compare 1 Low Byte
w
FF
1E09
CMP2L
Compare 2 Low Byte
w
FF
1E0A
CMP3L
Compare 3 Low Byte
w
FF
1E0B
CMP4L
Compare 4 Low Byte
w
FF
1E0C
CMP1H
Compare 1 High Byte
w
FF
1E0D
CMP2H
Compare 2 High Byte
w
FF
1E0E
CMP3H
Compare 3 High Byte
w
FF
1E0F
CMP4H
Compare 4 High Byte
w
FF
1E10
MAP1L
Map 1 Low Byte
w
FF
1E11
MAP2L
Map 2 Low Byte
w
FF
1E12
MAP3L
Map 3 Low Byte
w
FF
1E13
MAP4L
Map 4 Low Byte
w
FF
1E14
MAP1H
Map 1 High Byte
w
FF
1E15
MAP2H
Map 2 High Byte
w
FF
1E16
MAP3H
Map 3 High Byte
w
FF
1E17
MAP4H
Map 4 High Byte
w
FF
1E18
DMAIM
DMA Interface Mode
w
00
1E64
PAR0
Patch Address Register 0
w
FF
1E65
PAR1
Patch Address Register 1
w
FF
1E66
PAR2
Patch Address Register 2
w
FF
1E67
PDR
Patch Data Register
w
00
1E68
PER0
Patch Enable Register 0
w
00
1E69
PER1
Patch Enable Register 1
w
00
132
Section
DMA Interface (chapter
5.9. on page 96)
Memory Patch Module
(chapter 5.11. on
page 107)
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 5–26: I/O Register Map
Addr.
Mnemonic
Name
Mode
Reset
1F01
CR
1F0F
Control Register
r/w
−
Control Register (chapter 5.4. on page 87)
BR
Banking Register
r/w
01
Memory Banking (chapter 5.8. on page 95)
1F00
CSW0
Clock, Supply & Watchdog Register 0
w
01
1F60
CSW1
Clock, Supply & Watchdog Register 1
r/w
FF
Reset Logic (chapter
5.7. on page 90)
1F07
RC
Reset Control Register
r/w
00
1F08
SR0
Standby Register 0
r/w
00
1F09
SR1
Standby Register 1
r/w
40
1F0A
SR2
Standby Register 2
r/w
00
1FD0
I2CWS0
I2C Write Start Register 0
w
00
1FD1
I2CWS1
I2C Write Start Register 1
w
00
1FD2
I2CWD0
I2C Write Data Register 0
w
00
1FD3
I2CWD1
I2C Write Data Register 1
w
00
1FD4
I2CWP0
I2C Write Stop Register 0
w
00
1FD5
I2CWP1
I2C Write Stop Register 1
w
00
1FD6
I2CRD
I2C Read Data Register
r
00
1FD7
I2CRS
I2C Read Status Register
r
00
1FDB
I2CM
I2C Mode Register
w
02
1E73
I2CPS
I2C Port Select Register
w
00
Micronas
Section
Standby Registers
(chapter 5.5. on
page 89)
I2C-Bus Master Interface (chapter 5.12. on
page 109)
133
VCT 38xxA
ADVANCE INFORMATION
Table 5–26: I/O Register Map
Addr.
Mnemonic
Name
Mode
Reset
1F20
IRC
Interrupt Control Register
r/w
0C
1F21
IRRET
Interrupt Return Register
r/w
00
1F22
IRPRI10
Interrupt Priority Register, Input 0 and 1
r/w
00
1F23
IRPRI32
Interrupt Priority Register, Input 2 and 3
r/w
00
1F24
IRPRI54
Interrupt Priority Register, Input 4 and 5
r/w
00
1F25
IRPRI76
Interrupt Priority Register, Input 6 and 7
r/w
00
1F26
IRPRI98
Interrupt Priority Register, Input 8 and 9
r/w
00
1F27
IRPRIBA
Interrupt Priority Register, Input 10 and 11
r/w
00
1F28
IRPRIDC
Interrupt Priority Register, Input 12 and 13
r/w
00
1F29
IRPRIFE
Interrupt Priority Register, Input 14 and 15
r/w
00
1F2A
IRP
Interrupt Pending Register
r
00
1F2B
IRPM0
Interrupt Port Mode
w
00
1F2C
IRPP
Interrupt Port Prescaler
w
00
1E71
IRPMUX0
Interrupt Port Multiplex 0
w
00
1E72
IRPMUX1
Interrupt Port Multiplex 1
w
00
1FA8
AD0
ADC Register 0
r/w
00
1FA9
AD1
ADC Register 1
r
00
1F4E
TIM0L
Timer 0 Low Byte
r/w
FF
1F4F
TIM0H
Timer 0 High Byte
r/w
FF
1F11
TIM0M
Timer 0 Mode
w
00
1F4C
TIM1L
Timer 1 Low Byte
r/w
FF
1F4D
TIM1H
Timer 1 High Byte
r/w
FF
1F13
TIM1M
Timer 1 Mode
w
00
1F4A
TVPWML
TV PWM Low Byte
w
00
1F4B
TVPWMH
TV PWM High Byte
w
00
1F50
PWM0
PWM 0 Register
w
00
1F51
PWM1
PWM 1 Register
w
00
1F52
PWM2
PWM 2 Register
w
00
1F53
PWM3
PWM 3 Register
w
00
134
Section
Interrupt Controller
(chapter 5.10. on
page 99)
A/D Converter (ADC)
(chapter 5.17. on
page 123)
Timer T0 and T1 (chapter 5.13. on page 113)
Pulse Width Modulator
(chapter 5.15. on
page 120)
Micronas
VCT 38xxA
ADVANCE INFORMATION
Table 5–26: I/O Register Map
Addr.
Mnemonic
Name
Mode
Reset
1F6C
CC0M
CAPCOM 0 Mode Register
r/w
00
1F6D
CC0I
CAPCOM 0 Interrupt Register
r/w
00
1F6E
CC0L
CAPCOM 0 Capture/Compare Low Byte
r/w
FF
1F6F
CC0H
CAPCOM 0 Capture/Compare High Byte
r/w
FF
1F70
CC1M
CAPCOM 1 Mode Register
r/w
00
1F71
CC1I
CAPCOM 1 Interrupt Register
r/w
00
1F72
CC1L
CAPCOM 1 Capture/Compare Low Byte
r/w
FF
1F73
CC1H
CAPCOM 1 Capture/Compare High Byte
r/w
FF
1F7C
CCCL
CAPCOM Counter Low Byte
r
00
1F7D
CCCH
CAPCOM Counter High Byte
r
00
1F14
CCCS
CAPCOM Clock Select
w
00
1E70
CCIMUX
CAPCOM Input Multiplex Register
w
00
1F90
P1D
Port 1 Data Register
r/w
00
1F91
P1O
Port 1 Output Register
w
00
1F92
P1M
Port 1 Mode Register
w
00
1F93
P1E
Port 1 Enable Register
w
00
1F94
P2D
Port 2 Data Register
r/w
00
1F95
P2O
Port 2 Output Register
w
00
1F96
P2M
Port 2 Mode Register
w
00
1F97
P2E
Port 2 Enable Register
w
00
1F98
P3D
Port 3 Data Register
r/w
00
1F99
P3O
Port 3 Output Register
w
00
1F9A
P3M
Port 3 Mode Register
w
00
1F9B
P3E
Port 3 Enable Register
w
00
1F9C
P4D
Port 4 Data Register
r/w
00
1F9E
P4M
Port 4 Mode Register
w
73
1F9F
P4E
Port 4 Enable Register
w
03
1F9D
C20M
CLK20 Mode Register
w
00
1FFB
TST5
Test Register 5
r
00
1FFC
TST4
Test Register 4
w
00
1FFD
TST3
Test Register 3
w
00
1FFE
TST1
Test Register 1
w
00
1FFF
TST2
Test Register 2
w
00
Micronas
Section
Capture Compare Module (CAPCOM) (chapter
5.14. on page 115)
Ports (chapter 5.18. on
page 126)
Test Registers (chapter
5.6. on page 90)
135
VCT 38xxA
ADVANCE INFORMATION
6. Specifications
6.1. Outline Dimensions
SPGS703000-1(P64)/1E
33
1
32
0.8 ±0.2
3.8 ±0.1
64
57.7 ±0.1
19.3 ±0.1
18 ±0.05
1.778
0.48 ±0.06
3.2 ±0.2
0.28 ±0.06
1 ±0.05
20.3 ±0.5
31 x 1.778 = 55.1 ±0.1
Fig. 6–1: 64-Pin Plastic Shrink Dual-Inline Package
(PSDIP64)
Weight approximately 9.0 g
Dimensions in mm
31 x 0.8 = 24.8 ± 0.1
0.17 ± 0.06
96
0.8
65
64
128
33
31 x 0.8 = 24.8 ± 0.1
28 ± 0.1
31.2 ± 0.1
0.34 ± 0.05
0.8
97
32
1
31.2 ± 0.1
3.4 ± 0.2
3.775 ± 0.325
0.1
28 ± 0.1
SPGS706000-5(P128)/1E
Fig. 6–2: 128-Pin Plastic Metric Quad Flat Package
(PMQFP128)
Weight approximately 5.4 g
Dimensions in mm
136
Micronas
0.4 ± 0.1
0.2
1 ± 0.1
2.1 ± 0.20
Micronas
4.80 ± 0.20
0.2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1
2
3
4
5
2.540 ± 0.15
6
7
8
9
EXTRA PIN
10 11 12 13 14 15 16 17 18 19 20
2.540 x 19 = 48.26 ± 0.2
2.540 x 19 = 48.26 ± 0.2
2.540 ± 0.15
D0029/1E
ADVANCE INFORMATION
VCT 38xxA
Fig. 6–3: 257-Pin Ceramic Pin Grid Array
(CPGA257)
Weight approximately 32 g
Dimensions in mm
137
1 ± 0.1
0.46 ± 0.05
0.8
VCT 38xxA
ADVANCE INFORMATION
6.2. Pin Connections and Short Descriptions
NC = not connected
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
Pin No.
Pin Name
Type
IN = Input
OUT = Output
SUPPLY = Supply Pin
Connection
Short Description
(If not used)
PSDIP
64-pin
PMQFP
128-pin
CPGA
257-pin
1
33
A-1
P17
IN/OUT
LV
Port 1, Bit 7
2
34
C-2
P16
IN/OUT
LV
Port 1, Bit 6
3
37
C-1
VSUPP1
SUPPLY
X
Supply Voltage, Port 1
4
38
E-2
GNDP1
SUPPLY
X
Ground, Port 1
5
35
B-1
P15
IN/OUT
LV
Port 1, Bit 5
6
36
D-2
P14
IN/OUT
LV
Port 1, Bit 4
7
39
D-1
P13
IN/OUT
LV
Port 1, Bit 3
8
40
F-2
P12
IN/OUT
LV
Port 1, Bit 2
9
41
E-1
P11
IN/OUT
LV
Port 1, Bit 1
10
42
G-2
P10
IN/OUT
LV
Port 1, Bit 0
11
43
F-1
VOUT
OUT
LV
Analog Video Output
12
44
H-2
VRT
IN
X
Reference Voltage Top, Video ADC
13
45
G-1
SGND
IN
GNDAF
Signal Ground for Analog Input
14
46
H-1
GNDAF
SUPPLY
X
Ground, Analog Front-end
15
47
J-1
VSUPAF
SUPPLY
X
Supply Voltage, Analog Front-end
16
48
K-1
CBIN
IN
VRT
Analog Component Cb Input
17
49
L-1
CIN1
IN
VRT
Analog Chroma 1 Input
18
50
M-1
CIN2/ CRIN
IN
VRT
Analog Chroma 2 Input /
Analog Component Cr Input
19
51
N-1
VIN1
IN
VRT
Analog Video 1 Input
20
52
N-2
VIN2
IN
VRT
Analog Video 2 Input
21
53
P-1
VIN3
IN
VRT
Analog Video 3 Input
22
54
P-2
VIN4
IN
VRT
Analog Video 4 Input
23
89
Y-16
TEST
IN
GNDS
Test Pin, reserved for Test
24
76
W-8
HOUT
OUT
X
Horizontal Drive Output
25
77
Y-7
VSUPD
SUPPLY
X
Supply Voltage, Digital Circuitry
26
78
Y-8
GNDD
SUPPLY
X
Ground, Digital Circuitry
27
90
W-16
FBLIN
IN
GNDAB
Fast Blank Input
28
91
Y-17
RIN
IN
GNDAB
Analog Red Input
29
92
W-17
GIN
IN
GNDAB
Analog Green Input
30
93
Y-18
BIN
IN
GNDAB
Analog Blue Input
138
Micronas
VCT 38xxA
ADVANCE INFORMATION
Pin No.
Pin Name
Type
Connection
Short Description
(If not used)
PSDIP
64-pin
PMQFP
128-pin
CPGA
257-pin
31
94
W-18
VPROT
IN
GNDD
Vertical Protection Input
32
95
Y-19
SAFETY
IN
GNDD
Safety Input
33
96
W-19
HFLB
IN
HOUT
Horizontal Flyback Input
34
97
Y-20
VERTQ /
OUT
LV
Differential Vertical Sawtooth Output
INTLC
Interlace Control Output
35
98
V-19
VERT
OUT
LV
Differential Vertical Sawtooth Output
36
99
W-20
EW
OUT
LV
Vertical Parabola Output
37
100
U-19
SENSE
IN
GNDAB
Sense ADC Input
38
101
V-20
GNDM
SUPPLY
X
Ground, MADC Input
39
102
T-19
RSW1
OUT
LV
Range Switch1 for Measurement ADC
40
103
U-20
RSW2
OUT
LV
Range Switch2 for Measurement ADC
41
104
R-19
SVMOUT
OUT
VSUPAB
Scan Velocity Modulation Output
42
105
T-20
ROUT
OUT
VSUPAB
Analog Red Output
43
106
P-19
GOUT
OUT
VSUPAB
Analog Green Output
44
107
R-20
BOUT
OUT
VSUPAB
Analog Blue Output
45
108
N-19
VSUPAB
SUPPLY
X
Supply Voltage, Analog Back-end
46
109
P-20
GNDAB
SUPPLY
X
Ground, Analog Back-end
47
110
N-20
VRD
IN
X
DAC Reference
48
111
M-20
XREF
IN
X
Reference Input for RGB DACs
49
112
L-20
AIN3
IN
GNDS
Analog Audio 3Input
50
113
K-20
AIN2
IN
GNDS
Analog Audio 2Input
51
114
J-20
AIN1
IN
GNDS
Analog Audio 1 Input
52
115
H-20
AOUT2
OUT
LV
Analog Audio 2 Output
53
116
H-19
AOUT1
OUT
LV
Analog Audio 1 Output
54
122
E-19
VSUPS
SUPPLY
X
Supply Voltage, Standby
55
123
D-20
GNDS
SUPPLY
X
Ground, Standby
56
120
F-19
XTAL1
IN
X
Analog Crystal Input
57
121
E-20
XTAL2
OUT
X
Analog Crystal Output
58
117
G-20
RESQ
IN/OUT
X
Reset Input/Output, Active Low
59
118
G-19
SCL
IN/OUT
X
I2C Bus Clock
60
119
F-20
SDA
IN/OUT
X
I2C Bus Data
61
62
V-2
P23
IN/OUT
LV
Port 2, Bit 3
62
63
W-1
P22
IN/OUT
LV
Port 2, Bit 2
63
64
W-2
P21
IN/OUT
LV
Port 2, Bit 1
Micronas
139
VCT 38xxA
Pin No.
ADVANCE INFORMATION
Pin Name
Type
Connection
Short Description
(If not used)
PSDIP
64-pin
PMQFP
128-pin
CPGA
257-pin
64
65
Y-1
P20
IN/OUT
LV
Port 2, Bit 0
1
A-20
ADB17
OUT
LV
Address Bus 17
2
B-18
VSUPADB
SUPPLY
X
Supply Voltage, Address Bus
3
A-19
GNDADB
SUPPLY
X
Ground, Address Bus
4
B-17
ADB16
OUT
LV
Address Bus 16
5
A-18
ADB15
OUT
LV
Address Bus 15
6
B-16
ADB14
OUT
LV
Address Bus 14
7
A-17
ADB13
OUT
LV
Address Bus 13
8
B-15
ADB12
OUT
LV
Address Bus 12
9
A-16
ADB11
OUT
LV
Address Bus 11
10
B-14
ADB10
OUT
LV
Address Bus 10
11
A-15
ADB9
OUT
LV
Address Bus 9
12
B-13
ADB8
OUT
LV
Address Bus 8
13
A-14
ADB7
OUT
LV
Address Bus 7
14
A-13
ADB6
OUT
LV
Address Bus 6
15
A-12
ADB5
OUT
LV
Address Bus 5
16
A-11
VSUPADB
SUPPLY
X
Supply Voltage, Address Bus
17
A-10
GNDADB
SUPPLY
X
Ground, Address Bus
18
A-9
ADB4
OUT
LV
Address Bus 4
19
A-8
ADB3
OUT
LV
Address Bus 3
20
B-8
ADB2
OUT
LV
Address Bus 2
21
A-7
ADB1
OUT
LV
Address Bus 1
22
B-7
ADB0
OUT
LV
Address Bus 0
23
A-6
DB0
IN/OUT
LV
Data Bus 0
24
B-6
DB1
IN/OUT
LV
Data Bus 1
25
A-5
DB2
IN/OUT
LV
Data Bus 2
26
B-5
DB3
IN/OUT
LV
Data Bus 3
27
A-4
VSUPDB
SUPPLY
X
Supply Voltage, Data Bus
28
B-4
GNDDB
SUPPLY
X
Ground, Data Bus
29
A-3
DB4
IN/OUT
LV
Data Bus 4
30
B-3
DB5
IN/OUT
LV
Data Bus 5
31
A-2
DB6
IN/OUT
LV
Data Bus 6
32
B-2
DB7
IN/OUT
LV
Data Bus 7
55
R-1
DISINTROM
IN
X
Disable Internal ROM
140
Micronas
VCT 38xxA
ADVANCE INFORMATION
Pin No.
PSDIP
64-pin
Micronas
Pin Name
Type
Connection
Short Description
(If not used)
PMQFP
128-pin
CPGA
257-pin
56
R-2
P27
IN/OUT
LV
Port 2, Bit 7
57
T-1
P26
IN/OUT
LV
Port 2, Bit 6
58
T-2
P25
IN/OUT
LV
Port 2, Bit 5
59
U-1
P24
IN/OUT
LV
Port 2, Bit 4
60
U-2
VSUPP2
SUPPLY
X
Supply Voltage, Port 2
61
V-1
GNDP2
SUPPLY
X
Ground, Port 2
66
W-3
VBCLK
IN
GNDD
Video Bus Clock
67
Y-2
VB7
IN
GNDD
Video Bus 7
68
W-4
VB6
IN
GNDD
Video Bus 6
69
Y-3
VB5
IN
GNDD
Video Bus 5
70
W-5
VB4
IN
GNDD
Video Bus 4 / Bond 0=16k Text RAM
71
Y-4
VB3
IN
GNDD
Video Bus 3 / Bond 1=CTI
72
W-6
VB2
IN
GNDD
Video Bus 2 / Bond 2=Scaler
73
Y-5
VB1
IN
GNDD
Video Bus 1 / Bond 3=Comb Filter
74
W-7
VB0
IN
GNDD
Video Bus 0 / Bond 4=VDP Full/Lite
75
Y-6
CLK20
OUT
LV
20 MHz System Clock Output
79
Y-9
P37
IN/OUT
LV
Port 3, Bit 7
80
Y-10
P36
IN/OUT
LV
Port 3, Bit 6
81
Y-11
P35
IN/OUT
LV
Port 3, Bit 5
82
Y-12
P34
IN/OUT
LV
Port 3, Bit 4
83
Y-13
VSUPP3
SUPPLY
X
Supply Voltage, Port 3
84
W-13
GNDP3
SUPPLY
X
Ground, Port 3
85
Y-14
P33
IN/OUT
LV
Port 3, Bit 3
86
W-14
P32
IN/OUT
LV
Port 3, Bit 2
87
Y-15
P31
IN/OUT
LV
Port 3, Bit 1
88
W-15
P30
IN/OUT
LV
Port 3, Bit 0
124
D-19
WE1Q
OUT
LV
Write Enable Output 1
125
C-20
WE2Q
OUT
LV
Write Enable Output 2
126
C-19
OE1Q
OUT
LV
Output Enable Output 1
127
B-20
OE2Q
OUT
LV
Output Enable Output 2
128
B-19
ADB18
OUT
LV
Address Bus 18
141
VCT 38xxA
6.3. Pin Descriptions for PSDIP64 package
Pin 1,2,5-10, P10−P17 − I/O Port (Fig. 6–28)
These pins provide CPU controlled I/O ports.
Pin 3, VSUPP1* − Supply Voltage, Port 1 Driver
This pin is used as supply for the I/O port 1 driver.
Pin 4, GNDP1* − Ground, Port 1 Driver
This is the ground reference for the I/O port 1 driver.
Pin 11, VOUT− Analog Video Output (Fig. 6–13)
The analog video signal that is selected for the main
(luma, CVBS) adc is output at this pin. An emitter follower is required at this pin.
Pin 12, VRT − Reference Voltage Top (Fig. 6–14)
Via this pin, the reference voltage for the A/D converters
is decoupled. The pin is connected with 10 µF/47 nF to
the Signal Ground Pin.
Pin 13, SGND − Signal GND for Analog Input
This is the high quality ground reference for the video
input signals.
Pin 14, GNDAF* − Ground, Analog Front-end
This pin has to be connected to the analog ground. No
supply current for the digital stages should flow
through this line.
Pin 15, VSUPAF* − Supply Voltage, Analog Front-end
This pin has to be connected to the analog supply voltage. No supply current for the digital stages should
flow through this line.
Pin 16,18, CBIN,CRIN − Analog Chroma Component
Input (Fig. 6–11)
These pins are used as the chroma component (CB,
CR) inputs required for the analog YUV Interface. The
input signal must be AC-coupled. The CRIN pin can
alternatively be used as the second SVHS chroma
input (CIN2).
Pin 17,18, CIN1,CIN2 − Analog Chroma Input (Fig. 6–
11)
These are the analog chroma inputs. A S-VHS chroma
signal is converted using the chroma (Video 2) AD
converter. A resistive divider is used to bias the input
signal to the middle of the converter input range. The
input signal must be AC-coupled. The CIN2 pin can
alternatively be used as the chroma component (CR)
input required for the analog YUV Interface.
Pins 19−22, VIN1–4 − Analog Video Input (Fig. 6–10)
These are the analog video inputs. A CVBS or S-VHS
luma signal is converted using the luma (Video 1) AD
converter. The input signal must be AC-coupled.
ADVANCE INFORMATION
Pin 24, HOUT − Horizontal Drive Output (Fig. 6–17)
This open drain output supplies the drive pulse for the
horizontal output stage. The polarity and gating with
the flyback pulse are selectable by software.
Pin 25, VSUPD* − Supply Voltage, Digital Circuitry
Pin 26, GNDD* − Ground, Digital Circuitry
This is the ground reference for the digital circuitry.
Pin 27, FBLIN − Fast Blank Input (Fig. 6–19)
These pins are used to switch the RGB outputs to the
external analog RGB inputs. The active level (low or
high) can be selected by software.
Pin 28,29,30, RIN, GIN, BIN − Analog RGB Input (Fig.
6–15)
These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector which can by
switched to the analog RGB outputs with the fast blank
signal. The analog back-end provides separate brightness and contrast settings for the external analog RGB
signals.
Pin 31, VPROT − Vertical Protection Input (Fig. 6–18)
The vertical protection circuitry prevents the picture
tube from burn-in in the event of a malfunction of the
vertical deflection stage. During vertical blanking, a
signal level of 2.5V is sensed. If a negative edge cannot be detected, the RGB output signals are blanked.
Pin 32, SAFETY − Safety Input (Fig. 6–18)
This is a three-level input. Low level means normal
function. At the medium level RGB output signals are
blanked. At high level RGB output signals are blanked
and horizontal drive is shut off.
Pin 33, HFLB − Horizontal Flyback Input (Fig. 6–18)
Via this pin the horizontal flyback pulse is supplied to
the VCT 38xxA.
Pin 34, VERTQ, INTLC − Inverted Vertical Sawtooth
Output (Fig. 6–21) / Interlace Output (Fig. 6–20)
This pin supplies the inverted signal of VERT. Together
with the VERT pin it can be used to drive symmetrical
deflection amplifiers. The drive signal is generated with
15-bit precision. The analog voltage is generated by a
4 bit current-DAC with external resistor and uses digital
noise shaping. Alternatively this pin supplies the interlace information, the polarity is programmable.
Pin 35, VERT − Vertical Sawtooth Output (Fig. 6–21)
This pin supplies the drive signal for the vertical output
stage. The drive signal is generated with 15-bit precision. The analog voltage is generated by a 4 bit current-DAC with external resistor and uses digital noise
shaping.
Pin 23, TEST − Test Input (Fig. 6–6)
This pin enables factory test modes. For normal operation, it must be connected to ground.
142
Micronas
ADVANCE INFORMATION
VCT 38xxA
Pin 36, EW − East-West Parabola Output (Fig. 6–22)
This pin supplies the parabola signal for the East-West
correction. The drive signal is generated with 15 bit
precision. The analog voltage is generated by a 4 bit
current-DAC with external resistor and uses digital
noise shaping.
Pin 49, 50, 51, AIN1−3 − Analog Audio Input (Fig. 6–
26)
The analog input signal from TUNER or SCART is fed
to this pin. The input signal must be AC-coupled. Alternatively these pins can be used as digital I/O ports
(Fig. 6–29).
Pin 37, SENSE − Measurement ADC Input (Fig. 6–24)
This is the input of the analog to digital converter for
the picture and tube measurement. Three measurement ranges are selectable with RSW1 and RSW2.
Pin 52,53, AOUT1, AOUT2 − Analog Audio Output
(Fig. 6–27)
These pins are the analog audio outputs. Connections
to these pins must use a 680 ohm series resistor as
closely as possible to these pins. The output signals
are intended to be AC coupled. Alternatively these pins
can be used as digital I/O ports (Fig. 6–29).
Pin 38, GNDM − Measurement ADC Reference Input
This is the ground reference for the measurement A/D
converter. Connect this pin to GNDAB
Pin 39, 40, RSW1, RSW2 − Range Switch for Measuring ADC (Fig. 6–23)
These pins are open drain pulldown outputs. RSW1 is
switched off during cutoff and whitedrive measurement. RSW2 is switched off during cutoff measurement only.
Pin 41, SVMOUT − Scan Velocity Modulation Output
(Fig. 6–16)
This output delivers the analog SVM signal. The D/A
converter is a current sink like the RGB D/A converters. At zero signal the output current is 50% of the
maximum output current.
Pin 42, 43, 44, ROUT, GOUT, BOUT − Analog RGB
Output (Fig. 6–16)
These pins are the analog Red/Green/Blue outputs of
the back-end. The outputs are current sinks.
Pin 45, VSUPAB* − Supply Voltage, Analog Back-end
This pin has to be connected to the analog supply voltage. No supply current for the digital stages should
flow through this line.
Pin 46, GNDAB* − Ground, Analog Back-end
This pin has to be connected to the analog ground. No
supply current for the digital stages should flow
through this line.
Pin 54, VSUPS* − Supply Voltage, Standby
Pin 55, GNDS* − Ground, Standby
This is the ground reference for the standby circuitry.
Pins 56 and 57, XTAL1 Crystal Input and XTAL2 Crystal Output (Fig. 6–8)
These pins are connected to an 20.25 MHz crystal
oscillator which is digitally tuned by integrated shunt
capacitances. The CLK20 clock signal is derived from
this oscillator.
Pin 58, RESQ − Reset Input/Output (Fig. 6–7)
A low level on this pin resets the VCT 38xxA. The internal CPU can pull down this pin to reset external
devices connected to this pin.
Pin 59, SCL − I2C Bus Clock (Fig. 6–7)
This pin connects to the I2C bus clock line. The signal
can be pulled down by external slave ICs to slow down
data transfer.
Pin 60, SDA − I2C Bus Data (Fig. 6–7)
This pin connects to the I2C bus data line.
Pin 61−64, P20−P23 − I/O Port (Fig. 6–28)
These pins provide CPU controlled I/O ports.
Pin 47, VRD − DAC Reference Decoupling (Fig. 6–25)
Via this pin the DAC reference voltage is decoupled by
an external capacitor. The DAC output currents
depend on this voltage, therefore a pulldown transistor
can be used to shut off all beam currents. A decoupling capacitor of 4.7 µF in parallel to 100 nF (low
inductance) is required.
Pin 48, XREF − DAC Current Reference (Fig. 6–25)
External reference resistor for DAC output currents,
typical 10 kΩ to adjust the output current of the D/A
converters. (see recommended operating conditions).
This resistor has to be connected to analog ground as
closely as possible to the pin.
Micronas
143
VCT 38xxA
6.4. Pin Descriptions for PMQFP128 package
Pins 1, 4−15, 18−22, 128, ADB0−ADB18 − Address
Bus Output (Fig. 6–30)
These 19 lines provide the CCU address bus output to
access external memory.
Pin 2, 16, VSUPADB* − Supply Voltage, Address Bus
Driver
This pin is used as supply for the address bus driver.
Pin 3, 17, GNDADB* − Ground, Address Bus Driver
This is the ground reference for the address bus driver.
Pins 23−26, 29−32, DB0−DB7 − Data Bus Input/Output (Fig. 6–31)
These 8 lines provide the bidirectional CCU data bus
to access external memory.
Pin 27, VSUPDB* − Supply Voltage, Data Bus Driver
This pin is used as supply for the CCU data bus driver.
Pin 28, GNDDB* − Ground, Data Bus Driver
This is the ground reference for the CCU data bus
driver.
Pin 55, DISINTROM − Disable Internal ROM Input
(Fig. 6–6)
A high level at this pin disables the internal CCU program memory during reset. In this case the CCU loads
the control word from external address location
h’FFF9.
ADVANCE INFORMATION
Pin 124, WE1Q − Write Enable Output 1 (Fig. 6–30)
This pin controls the direction of data exchange
between the CCU and the external program memory
device.
Pin 125, WE2Q − Write Enable Output 2 (Fig. 6–30)
This pin controls the direction of data exchange
between the CCU and external the teletext page memory device.
Pin 126, OE1Q − Output Enable Output 1 (Fig. 6–30)
This pin is used to enable the output driver of the external program memory device for read access.
Pin 127, OE2Q − Output Enable Output 1 (Fig. 6–30)
This pin is used to enable the output driver of the external teletext page memory device for read access.
* Application Note:
All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected
separately with short and low-resistive lines to the
power supply. Decoupling capacitors from VSUPxx to
GNDxx are recommended as closely as possible to
these pins. Decoupling of VSUPD and GNDD is most
important. We recommend using more than one
capacitor. By choosing different values, the frequency
range of active decoupling can be extended.
Pin 56−59, P27−P24 − I/O Port (Fig. 6–28)
These pins provide CCU controlled I/O ports.
Pin 60, VSUPP2* − Supply Voltage, Port 2 Driver
This pin is used as supply for the I/O port 2 driver.
Pin 61, GNDP2* − Ground, Port 2 Driver
This is the ground reference for the I/O port 2 driver.
Pins 66−74, VBCLK, VB0−VB7 − Digital Video Bus
Input (Fig. 6–32)
In future versions of VCT 38xxA these pins will provide
the ITU−R 656 video interface. As long as the ITU-R
656 video interface is not available, these pins have to
be connected to GNDD.
Pin 75, CLK20 − Main Clock Output (Fig. 6–9)
This is the 20.25 MHz main clock output.
Pin 79−82, 85−88, P37−P30 − I/O Port (Fig. 6–28)
These pins provide CCU controlled I/O ports.
Pin 83, VSUPP3* − Supply Voltage, Port 3Driver
This pin is used as supply for the I/O port 3 driver.
Pin 84, GNDP3* − Ground, Port 3Driver
This is the ground reference for the I/O port 3 driver.
144
Micronas
VCT 38xxA
ADVANCE INFORMATION
6.5. Pin Configuration
1
64
P20
P16
2
63
P21
VSUPP1
3
62
P22
GNDP1
4
61
P23
P15
5
60
SDA
P14
6
59
SCL
P13
7
58
RESQ
P12
8
57
XTAL2
P11
9
56
XTAL1
P10
10
55
GNDS
VOUT
11
54
VSUPS
VRT
12
53
AOUT1
SGND
13
52
AOUT2
GNDAF
14
51
AIN1
VSUPAF
15
50
AIN2
CBIN
16
49
AIN3
CIN1
17
48
XREF
CIN2/CRIN
18
47
VRD
VIN1
19
46
GNDAB
VIN2
20
45
VSUPAB
VIN3
21
44
BOUT
VIN4
22
43
GOUT
TEST
23
42
ROUT
HOUT
24
41
SVMOUT
VSUPD
25
40
RSW2
GNDD
26
39
RSW1
FBLIN
27
38
GNDM
VCT 38xx
P17
RIN
28
37
SENSE
GIN
29
36
EW
BIN
30
35
VERT
VPROT
31
34
VERTQ
SAFETY
32
33
HFLB
Fig. 6–4: 64-pin PSDIP package
Micronas
145
VCT 38xxA
ADVANCE INFORMATION
P35
P34
P36
P37
VSUPP3
GNDP3
P33
GNDD
VSUPD
HOUT
CLK20
VB0
P32
P31
P30
VB1
VB2
TEST
FBLIN
RIN
VB3
VB4
GIN
VB5
VB6
BIN
VPROT
SAFETY
HFLB
VB7
VBCLK
P20
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
97
64
P21
VERT
98
63
P22
EW
99
62
P23
SENSE
100
61
GNDP2
GNDM
101
60
VSUPP2
RSW1
102
59
P24
RSW2
103
58
P25
SVMOUT
104
57
P26
ROUT
105
56
P27
GOUT
106
55
DISINTROM
BOUT
107
54
VIN4
VSUPAB
108
53
VIN3
GNDAB
109
52
VIN2
VRD
110
51
VIN1
XREF
111
50
CIN2/CRIN
AIN3
112
49
CIN1
AIN2
113
48
CBIN
AIN1
114
47
VSUPAF
AOUT2
115
46
GNDAF
AOUT1
116
45
SGND
RESQ
117
44
VRT
SCL
118
43
VOUT
SDA
119
42
P10
XTAL1
120
41
P11
XTAL2
121
40
P12
VSUPS
122
39
P13
GNDS
123
38
GNDP1
WE1Q
124
37
VSUPP1
WE2Q
125
36
P14
OE1Q
126
35
P15
OE2Q
127
34
P16
ADB18
128
1
33
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P17
VERTQ
VCT 38xx
2
3
4
5
6
7
8
9
ADB17
VSUPADB
GNDADB
ADB16
ADB15
ADB14
ADB13
ADB12
ADB11
ADB10
ADB9
ADB8
ADB7
ADB6
ADB5
VSUPADB
146
DB7
DB6
DB5
DB4
GNDDB
VSUPDB
DB3
DB2
DB1
DB0
ADB0
ADB1
ADB2
ADB3
ADB4
GNDADB
Micronas
VCT 38xxA
ADVANCE INFORMATION
Fig. 6–5: 128-pin PMQFP package
VSUPAF
6.6. Pin Circuits
To ADC
VSUPS
GNDAF
GNDS
Fig. 6–10: Input pins VIN1–VIN4
Fig. 6–6: Input pins TEST, DISINTROM
VSUPAF
VSUPS
To ADC
GNDAF
N
Fig. 6–11: Input pins CIN1, CIN2
GNDS
Fig. 6–7: Input/Output pins RESQ, SDA, SCL
VSUPAF
VSUPS
To ADC
P
P
XTAL2
P
GNDAF
fXTAL
0.5M
XTAL1
Fig. 6–12: Input pins CRIN, CBIN
N
N
N
GNDS
VSUPAF
VINx
–
+
P
Fig. 6–8: Input/Output pins XTAL1, XTAL2
N
VREF
GNDAF
VSUPD
Fig. 6–13: Output pin VOUT
P
N
GNDD
–
+
Fig. 6–9: Output pin CLK20
= V
REF
VSUPAF
P
VRT
ADC Reference
SGND
Fig. 6–14: Supply pins VRT, SGND
Micronas
147
VCT 38xxA
ADVANCE INFORMATION
VSUPAB
VSUPAB
P
P
Clamping
P
N
GNDAB
N
GNDAB
Fig. 6–20: Output pin INTLC
Fig. 6–15: Input pins RIN, GIN, BIN
VSUPAB
P
N
P
P
Flyback
VERTQ
N
Bias
GNDAB
VERT
Fig. 6–16: Output pins ROUT, GOUT, BOUT,
SVMOUT
N
GNDAB
Fig. 6–21: Output pins VERT, VERTQ
N
GNDD
VSUPAB
Fig. 6–17: Output pin HOUT
P
VSUPAB
VEWXR
P
N
GNDAB
VREF
GNDAB
Fig. 6–22: Output pin EW
Fig. 6–18: Input pins SAFETY, VPROT, HFLB
N
VSUPAB
VREF
GNDAB
Fig. 6–23: Output pins RSW1, RSW2
GNDAB
Fig. 6–19: Input pin FBLIN
148
Micronas
VCT 38xxA
ADVANCE INFORMATION
VSUPS
P
VSUPAB
P
P
N
N
N
Fig. 6–24: Input pin SENSE
GND AB
Fig. 6–29: Input pins P42-P46
VSUPAB
VRD
+
-
VSUPADB
ref. current
P
int. ref.
voltage
XREF
GNDAB
N
Fig. 6–25: Supply pins XREF, VRD
GNDADB
Fig. 6–30: Output pins ADB0-ADB18, OE1, OE2,
WE1, WE2
40 k
≈ 2.5 V
GNDAB
VSUPDB
VSUPS
P
Fig. 6–26: Input pins AIN1-3
N
80 k
GNDDB
Fig. 6–31: Input/Output pins DB0-DB7
≈ 2.5 V
GNDAB
VSUPD
Fig. 6–27: Output pins AOUT1, AOUT2
GNDD
VSUPPx
VSUPS
P
to ADC
Fig. 6–32: Input pins VB0-VB7, VBCLK
N
GND Px
Fig. 6–28: Input/Output pins P10-P17, P20-P27, P30P37
Micronas
149
VCT 38xxA
ADVANCE INFORMATION
6.7. Electrical Characteristics
6.7.1. Absolute Maximum Ratings
1)
Symbol
Parameter
TA
Pin Name
Min.
Max.
Unit
Ambient Operating Temperature
−
65
°C
TC
Case Temperature (PSDIP64)
−
115
°C
TC
Case Temperature (PMQFP128)
−
115
°C
TS
Storage Temperature
−40
125
°C
PTOT
Total Power Dissipation
−
1400
mW
VSUPx
Supply Voltage
−0.3
6
V
VI
Input Voltage, all Inputs
−0.3
VSUPx+0.31)
V
VO
Output Voltage, all Outputs
−0.3
VSUPx+0.3
1)
V
VIO
Input/Output Voltage, all Open Drain Outputs
−0.3
6
VSUPx
V
Refer to Pin Circuits (chapter 6.6. on page 147)
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
6.7.2. Recommended Operating Conditions
6.7.2.1. General Recommendations
Symbol
Parameter
TA
Ambient Operating Temperature
fXTAL
Clock Frequency
VSUPA
Min.
Typ.
Max.
Unit
0
−
65
°C
XTAL1/2
−
20.25
−
MHz
Analog Supply Voltage
VSUPAF
VSUPAB
4.75
5.0
5.25
V
VSUPD
Digital Supply Voltage
VSUPS
VSUPD
VSUPVDP
VSUPTPU
VSUPCCU
3.15
3.3
3.45
V
VSUPP
Port Supply Voltage
VSUPPx
VSUPDB
VSUPADB
3.15
3.3/5.0
5.25
V
VSUPOFF
Standby Supply Voltage
VSUPAF
VSUPAB
VSUPD
0
−
0.5
V
VSUP∆
Difference between Standby and Emulator
Supply Voltage
VSUPS
VSUPVDP
VSUPTPU
VSUPCCU
0
−
0.3
V
150
Pin Name
Micronas
VCT 38xxA
ADVANCE INFORMATION
6.7.2.2. Analog Input and Output Recommendations
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
CAIN
Input Coupling Capacitor
Audio Inputs
AIN1−3
−
330
−
nF
VAIN
Audio Input Level
−
−
1.0
VRMS
RLAOUT
Audio Output Load Resistance
10
−
−
kΩ
CLAOUT
Audio Output Load Capacitance
−
−
1.0
nF
RSAOUT
Audio Output Serial Resistance
−
680
−
Ω
Audio
AOUT1−2
Video
VVIN
Video Input Level
VIN1−4,
CIN1−2
0.5
1.0
3.5
V
VCIN
Chroma Input Level
CRIN, CBIN
−
700
−
mV
CVIN
Input Coupling Capacitor
Video Inputs
VIN1−4
−
680
−
nF
CCIN
Input Coupling Capacitor
Chroma Inputs
CIN1−2
−
1
−
nF
CCCIN
Input Coupling Capacitor
Component Inputs
CRIN, CBIN
−
220
−
nF
Rxref
RGB−DAC Current defining Resistor
XREF
9.5
10
10.5
kΩ
CRGBIN
RGB Input Coupling Capacitor
RIN
GIN
BIN
−
15
−
nF
Rload
Deflection Load Resistance
−
6.8
−
kΩ
Cload
Deflection Load Capacitance
EW,
VERT,
VERTQ
−
68
−
nF
RGB
Deflection
Micronas
151
VCT 38xxA
ADVANCE INFORMATION
6.7.2.3. Recommended Crystal Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
TA
Operating Ambient Temperature
0
–
65
°C
fP
Parallel Resonance Frequency
with Load Capacitance CL = 13 pF
–
20.250000
–
MHz
∆fP/fP
Accuracy of Adjustment
–
–
±20
ppm
∆fP/fP
Frequency Temperature Drift
–
–
±30
ppm
RR
Series Resistance
–
–
25
Ω
C0
Shunt Capacitance
3
–
7
pF
C1
Motional Capacitance
20
–
30
fF
–
3.3
–
pF
Load Capacitance Recommendation
External Load Capacitance 1) from pins to
Ground
(pin names: Xtal1 Xtal2)
CLext
DCO Characteristics 2,3)
CICLoadmin
Effective Load Capacitance @ min. DCO–
Position, Code 0,
package: 64PSDIP
3
4.3
5.5
pF
CICLoadrng
Effective Load Capacitance Range,
DCO Codes from 0..255
11
12.7
15
pF
1)
Remarks on defining the External Load Capacitance:
External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance of the PCBs to the
required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size should be determined in the application.
The suggested value is a figure based on experience with various PCB layouts.
Tuning condition: Code DVCO Register=–720
2)
Remarks on Pulling Range of DCO:
The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard). The resulting frequency fL with an effective load capacitance of CLeff = CICLoad + CLoadBoard is:
1 + 0.5 * [ C1 / (C0 + CLeff) ]
fL = fP * _______________________
1 + 0.5 * [ C1 / (C0 + CL) ]
3)
Remarks on DCO codes
The DCO hardware register has 8 bits, the fp control register uses a range of –2048...2047
152
Micronas
VCT 38xxA
ADVANCE INFORMATION
6.7.3. Characteristics
If not otherwise designated under test conditions, all characteristics are specified for recommended operating conditions (see Section 6.7.2. on page 150).
6.7.3.1. General Characteristics
Symbol
Parameter
PTOT
Total Power Dissipation
PSTDBY
Standby Power Dissipation
IVSUPS
Pin Name
Min.
Typ.
Max.
Unit
−
850
1350
mW
−
tbd
tbd
mW
Current Consumption Standby
Mode
−
tbd
tbd
mA
IVSUPS
Current Consumption Standby
Supply
−
15
23
mA
IVSUPD
Current Consumption Digital Circuitry
VSUPD
−
55
83
mA
IVSUPP
Current Consumption Port Circuitry
VSUPP
−
−
–
mA
IVSUPAF
Current Consumption Analog
Front-end
VSUPAF
−
48
72
mA
IVSUPAB
Current Consumption Analog
Back-end
VSUPAB
−
50
100
mA
IL
Input and Output Leakage Current
All I/O Pins
−
−
1
µA
VSUPS
Test Conditions
VSUPD = VSUPP =
VSUPAF = VSUPAB =
VSUPDB = VSUPADB = 0V
SR0 = SR1 = SR2 = 0
normal operation
depends on port load
depends on contrast and
brightness settings
6.7.3.2. Test Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
TEST
−
−
0.8
V
VIH
Input High Voltage
2.0
−
−
V
Micronas
Test Conditions
153
VCT 38xxA
ADVANCE INFORMATION
6.7.3.3. Reset Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VBG
Internal Reference Voltage
RESQ
1.125
1.25
1.375
V
tBG
Internal Voltage Reference
Setup Time after Power-Up
−
30
60
us
VREFR
RESET Comparator Reference
Voltage
−
1*VBG
−
V
RVlh−
RVhl
RESET Comparator Hysteresis,
symmetrical to VREFR
0.25
0.313
0.375
V
VREFA
ALARM Comparator Reference
Voltage
−
2*VBG
−
V
AVlh−
AVhl
ALARM Comparator Hysteresis,
symmetrical to VREFA
0.1
0.135
0.15
V
tCDEL
RESET, ALARM Comparator
Delay Time
−
−
100
ns
VREFPOR
Power On Reset Comparator
Reference Voltage
−
V
VSUPS
−
2*VBG
Test Conditions
Overdrive=50mV
6.7.3.4. I2C Bus Interface
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
SDA, SCL
–
–
0.3*
VSUPS
V
VIH
Input High Voltage
0.6*
VSUPS
–
–
V
VOL
Output Low Voltage
–
–
0.4
0.6
V
V
VIH
Input Capacitance
–
–
5
pF
tF
Signal Fall Time
–
–
300
ns
CL = 400 pF
tR
Signal Rise Time
–
–
300
ns
CL = 400 pF
fSCL
Clock Frequency
0
–
400
kHz
tLOW
Low Period of SCL
1.3
–
–
µs
tHIGH
High Period of SCL
0.6
–
–
µs
tSU Data
Data Set Up Time to SCL high
100
–
–
ns
tHD Data
DATA Hold Time to SCL low
0
–
0.9
µs
154
SCL
SDA
Test Conditions
Il = 3 mA
Il = 6 mA
Micronas
VCT 38xxA
ADVANCE INFORMATION
6.7.3.5. 20-MHz Clock Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VOL
Output Low Voltage
CLK20
−
−
0.4
V
IOL = tbd,
strength tbd
VOH
Output High Voltage
VSUPD
− 0.4
−
VSUPD
V
−IOL = tbd,
strength tbd
6.7.3.6. Analog Video Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VOUT
Output Voltage
VOUT
1.7
2.0
2.3
VPP
VVIN = 1 VPP, AGC = 0 dB
AGCVOUT
AGC Step Width, VOUT
dB
DNLAGC
AGC Differential
Non-Linearity
LSB
3 Bit Resolution = 7
Steps
3 MSB’s of main AGC
VOUTDC
DC-Level
V
clamped to back porch
BW
VOUT Bandwidth
THD
VOUT Total Harmonic
Distortion
CLVOUT
Load Capacitance
ILVOUT
Output Current
1.333
±0.5
1
10
−
MHz
Input: −2 dBr of main
ADC range,
CL ≤ 10 pF
−45
−40
dB
Input: −2 dBr of main
ADC range,
CL ≤ 10 pF
1 MHz, 5 Harmonics
−
−
10
pF
−
−
±0.1
mA
Min.
Typ.
Max.
Unit
Test Conditions
10 µF/10 nF, 1 GΩ Probe
6
6.7.3.7. A/D Converter Reference
Symbol
Parameter
Pin Name
VVRT
Reference Voltage Top
VRT
VVRTN
Reference Voltage Top Noise
Micronas
2.5
2.6
2.8
V
−
−
100
mVPP
155
VCT 38xxA
ADVANCE INFORMATION
6.7.3.8. Analog Video Front-End and A/D Converters
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VIN1−4
1
–
–
MΩ
Code Clamp–DAC=0
Luma – Path (Composite)
RVIN
Input Resistance
CVIN
Input Capacitance
–
5
–
pF
VVIN
Full Scale Input Voltage
1.8
2.0
2.2
VPP
min. AGC Gain
VVIN
Full Scale Input Voltage
0.5
0.6
0.7
VPP
max. AGC Gain
AGC
AGC step width
–
0.166
–
dB
DNLAGC
AGC Differential Non-Linearity
–
–
±0.5
LSB
6-Bit Resolution= 64 Steps
fsig=1MHz,
– 2 dBr of max. AGC–Gain
VVINCL
Input Clamping Level, CVBS
–
1.0
–
V
Binary Level = 64 LSB
min. AGC Gain
QCL
Clamping DAC Resolution
–16
−
15
steps
ICL–LSB
Input Clamping Current per step
0.7
1.0
1.3
µA
5 Bit – I–DAC, bipolar
VVIN=1.5 V
DNLICL
Clamping DAC Differential NonLinearity
–
–
±0.5
LSB
1.4
2.0
2.6
kΩ
Chroma – Path (Composite)
RCIN
Input Resistance
SVHS Chroma
VCIN
Full Scale Input Voltage, Chroma
1.08
1.2
1.32
VPP
VCINDC
Input Bias Level,
SVHS Chroma
−
1.5
−
V
Binary Code for Open
Chroma Input
−
128
−
−
1
−
−
MΩ
CIN1
CIN2
Chroma – Path (Component)
RCIN
Input Resistance
CCIN
Input Capacitance
−
−
4.5
pF
VCIN
Full Scale Input Voltage
0.76
0,84
0.92
VPP
minimal Range
VCIN
Full Scale Input Voltage
1.08
1.2
1.32
VPP
extended Range
VCINCL
Input Clamping Level Cr, Cb
−
1.5
−
V
Binary Level = 128 LSB
QCL
Clamping DAC Resolution
–32
−
31
steps
ICL–LSB
Input Clamping Current per step
0.59
0.85
1.11
µA
6 Bit – I–DAC, bipolar
VVIN=1.5 V
DNLICL
Clamping DAC Differential NonLinearity
−
−
±0.5
LSB
156
CRIN
CBIN
Code Clamp–DAC=0
Micronas
VCT 38xxA
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
8
10
–
MHz
–2 dBr input signal level
–
–56
–
dB
1 MHz, –2 dBr signal level
Dynamic Characteristics for all Video-Paths (Luma + Chroma)
VIN1−4
CIN1−2
CBIN
BW
Bandwidth
XTALK
Crosstalk, any Two Video Inputs
THD
Total Harmonic Distortion
–
50
–
dB
1 MHz, 5 harmonics,
–2 dBr signal level
SINAD
Signal-to-Noise and Distortion
Ratio
–
45
–
dB
1 MHz, all outputs,
–2 dBr signal level
INL
Integral Non-Linearity
–
–
±1
LSB
Code Density,
DC-ramp
DNL
Differential Non-Linearity
–
–
±0.8
LSB
DG
Differential Gain
–
–
±3
%
DP
Differential Phase
–
–
1.5
deg
Micronas
–12 dBr, 4.4 MHz signal on
DC-ramp
157
VCT 38xxA
ADVANCE INFORMATION
6.7.3.9. Analog RGB and FB Inputs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
RIN
GIN
BIN
−0.3
−
1.1
V
0.5
0.7
1.0
VPP
SCART Spec: 0.7V ±3dB
−
0.44
−
V
Contrast setting: 511
−
0.7
−
V
Contrast setting: 323
−
1.1
−
V
Contrast setting: 204
RGB Input Characteristics
VRGBIN
External RGB Inputs Voltage
Range
VRGBIN
nominal RGB Input Voltage
peak-to-peak
VRGBIN
RGB Inputs Voltage for Maximum Output Current
tCLP
Clamp Pulse Width
1.6
−
−
µs
CIN
Input Capacitance
−
−
13
pF
IIL
Input Leakage Current
−0.5
−
0.5
µA
VCLIP
RGB Input Voltage for
Clipping Current
−
2
−
V
VCLAMP
Clamp Level at Input
40
60
80
mV
Clamping ON
VINOFF
Offset Level at Input
−10
−
10
mV
Extrapolated from
VIN = 100 and 200 mV
VINOFF
Offset Level Match at Input
−10
−
10
mV
Extrapolated from
VIN = 100 and 200 mV
RCLAMP
Clamping-ON-Resistance
−
140
−
Ω
−
−
0.5
V
0.9
−
−
V
Clamping OFF,
VIN = −0.3...3 V
Fast Blank Input Characteristics
VFBLOFF
FBLIN Low Level
VFBLON
FBLIN High Level
VFBLTRIG
Fast Blanking Trigger
Level typical
−
0.7
−
V
tPID
Delay Fast Blanking to RGB OUT
from midst of FBLIN−transition
to 90% of RGBOUT- transition
−
8
15
ns
Difference of Internal Delay to
External RGBin Delay
−5
−
+5
ns
Switch-Over-Glitch
−
0.5
−
158
FBLIN
pAs
Internal RGB = 3.75 mA Full
Scale
Int. Brightness = 0
External Brightness =
1.5 mA (Full Scale)
RGBin = 0
VFBLOFF = 0.4 V
VFBLON = 1.0 V
Rise and fall time = 2 ns
Switch from 3.75 mA (int) to 1.5
mA (ext)
Micronas
VCT 38xxA
ADVANCE INFORMATION
6.7.3.10. Horizontal Flyback Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VIL
Input Low Voltage
HFLB
–
–
1.8
V
VIH
Input High Voltage
2.6
–
–
V
VIHST
Input Hysteresis
0.1
–
–
V
PSRRHF
Power Supply Rejection Ratio of
Trigger Level
0
−
−
dB
f = 20 MHz
PSRRMF
Power Supply Rejection Ratio of
Trigger Level
−20
−
−
dB
f < 15 kHz
PSRRLF
Power Supply Rejection Ratio of
Trigger Level
−40
−
−
dB
f < 100 Hz
Unit
Test Conditions
6.7.3.11. Horizontal Drive Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
VOL
Output Low Voltage
HOUT
−
−
0.4
V
IOL = 10 mA
VOH
Output High Voltage
(Open Drain Stage)
−
−
5
V
external pull-up resistor
tOF
Output Fall Time
−
8
20
ns
CLOAD = 30pF
IOL
Output Low Current
−
−
10
mA
Max.
Unit
6.7.3.12. Vertical Safety Input
Symbol
Parameter
Pin Name
VILA
Input Low Voltage A
SAFETY
VIHA
Min.
Typ.
−
−
1.8
V
Input High Voltage A
2.6
−
−
V
VILB
Input Low Voltage B
−
−
3.0
V
VIHB
Input High Voltage B
3.8
−
−
V
VIHST
Input Hysteresis A and B
0.1
−
−
V
tPID
Internal Delay
−
−
100
ns
Test Conditions
6.7.3.13. Vertical Protection Input
Symbol
Parameter
Pin Name
VIL
Input Low Voltage
VPROT
VIH
VIHST
Micronas
Min.
Typ.
Max.
Unit
−
−
1.8
V
Input High Voltage
2.6
−
−
V
Input Hysteresis
0.1
−
−
V
Test Conditions
159
VCT 38xxA
ADVANCE INFORMATION
6.7.3.14. Vertical and East/West D/A Converter Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
VOMIN
Minimum Output Voltage
EW
VERT
VERTQ
VOMAX
Unit
Test Conditions
−
0
−
V
Rload = 6.8 kΩ
Rxref = 10 kΩ
Maximum Output Voltage
2.82
3
3.2
V
Rload = 6.8 kΩ
Rxref = 10 kΩ
IDACN
Full scale DAC Output
Current
415
440
465
µA
Rxref = 10 kΩ
PSRR
Power Supply Rejection
Ratio
−
20
−
dB
Min.
Typ.
Max.
6.7.3.15. Interlace Output
Symbol
Parameter
Pin Name
VOL
Output Low Voltage
INTLC
VOH
Output High Voltage
Unit
Test Conditions
−
0.2
0.4
V
IOL = 1.6 mA
VSUPAB
− 0.4
VSUPAB
− 0.2
−
V
−IOL = 1.6mA
Min.
Typ.
Unit
Test Conditions
6.7.3.16. Sense A/D Converter Input
Symbol
Parameter
Pin Name
VI
Input Voltage Range
SENSE
−
0
Max.
VSUPA
V
B
VI255
Input Voltage for code 255
1.4
1.54
1.7
V
Read cutoff blue
register
C0
Digital Output for zero Input
−
−
16
LSB
Offset check,
read cutoff blue
register
RI
Input Impedance
1
−
−
MΩ
6.7.3.17. Range Switch Output
Symbol
Parameter
Pin Name
RON
Output On Resistance
RSW1
RSW2
IMax
Min.
Typ.
Max.
Unit
Test Conditions
IOL = 10 mA
−
−
50
Ω
Maximum Current
−
−
15
mA
ILEAK
Leakage Current
−
−
600
nA
CIN
Input Capacitance
−
−
5
pF
160
RSW High Impedance
Micronas
VCT 38xxA
ADVANCE INFORMATION
6.7.3.18. D/A Converter Reference
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VDACREF
DAC-Ref. Voltage
VRD
2.38
2.50
2.67
V
VDACR
DAC-Ref. Output
resistance
18
25
32
VXREF
DAC-Ref. Voltage
Bias Current Generation
2.38
2.5
2.67
Min.
Typ.
Max.
−
10
−
bit
3.6
3.75
3.9
mA
XREF
Test Conditions
kΩ
V
Rxref = 10 kΩ
6.7.3.19. Analog RGB Outputs, D/A Converters
Symbol
Parameter
Pin Name
Unit
Test Conditions
Internal RGB Signal D/A Converter Characteristics
Resolution
ROUT
GOUT
BOUT
Rref = 10 kΩ
IOUT
Full Scale Output Current
IOUT
Differential Nonlinearity
−
−
0.5
LSB
IOUT
Integral Nonlinearity
−
−
1
LSB
IOUT
Glitch Pulse Charge
−
0.5
−
pAs
Ramp signal, 25 Ω output termination
IOUT
Rise and Fall Time
−
3
−
ns
10% to 90%, 90% to 10%
IOUT
Intermodulation
−
−
−50
dB
2/2.5MHz full scale
IOUT
Signal to Noise
+50
−
−
dB
Signal: 1MHz full scale Bandwidth: 10MHz
IOUT
Matching R-G, R-B, G-B
−2
−
2
%
R/B/G Crosstalk
one channel talks
two channels talk
−
−
−46
dB
−
−
−
−
−
−
−50
−50
−50
dB
dB
dB
−
9
−
bit
39.2
40
40.8
%
RGB Input Crosstalk from external RGB
one channel talks
two channels talk
three channels talk
Passive channel:
IOUT =1.88 mA
Crosstalk-Signal: 1.25 MHz,
3.75 mA PP
Internal RGB Brightness D/A Converter Characteristics
Resolution
ROUT
GOUT
BOUT
IBR
Full Scale Output Current relative
IBR
Full Scale Output Current absolute
−
1.5
−
mA
IBR
Differential Nonlinearity
−
−
1
LSB
IBR
Integral Nonlinearity
−
−
2
LSB
IBR
Match R-G, R-B, G-B
−2
−
2
%
IBR
Match to digital RGB
R-R, G-G, B-B
−2
−
2
%
Micronas
Ref to max. digital RGB
161
VCT 38xxA
Symbol
Parameter
ADVANCE INFORMATION
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
−
9
−
bit
96
100
104
%
Ref. to max. Digital RGB VIN
= 0.7 VPP, contrast = 323
Full Scale Output Current
absolute
−
3.75
−
mA
Same as Digital RGB
Contrast Adjust Range
−
16:511
−
Gain Match R-G, R-B, G-B
−3
−
3
%
Measured at RGB Outputs
VIN = 0.7 V, contrast = 323
Gain Match to RGB-DACs
R-R, G-G, B-B
−3
−
3
%
Measured at RGB Outputs
VIN = 0.7 V, contrast = 323
R/B/G Input Crosstalk
one channel talks
two channels talk
−
−
−46
dB
Passive channel:
VIN = 0.7V, contrast = 323
Crosstalk signal: 1.25 MHz,
3.75 mAPP
RGB Input Crosstalk from
Internal RGB
one channel talks
two channels talk
tree channels talk
−
−
−50
dB
RGB Input Noise and
Distortion
−
−
−50
dB
VIN=0.7 VPP at 1 MHz
contrast = 323
Bandwidth: 10 MHz
15
−
MHz
VIN = 0.7 VPP,
contrast =323
External RGB Voltage/Current Converter Characteristics
Resolution
IEXOUT
CR
Full Scale Output Current relative
ROUT
GOUT
BOUT
RGB Input Bandwidth -3dB
VRGBO
RGB Input THD
−
−
−50
−40
−
−
dB
dB
Input signal 1 MHz
Input signal 6 MHz
VIN = 0.7 VPP
contrast =323
Differential Nonlinearity of
Contrast Adjust
−
−
1
LSB
VIN = 0.44V
Integral Nonlinearity of
Contrast Adjust
−
−
2
LSB
R,G,B Output Voltage
−1.0
−
0.3
V
Referred to VSUPO
−
−
100
Ω
Ref. to VSUPO
−1.5
−1.3
−1.2
V
Ref. to VSUPO Sum of max.
Current of RGB-DACs and
max. Current of Int. Brightness DACs is 2% degraded
R,G,B Output Load Resistance
VOUTC
162
RGB Output Compliance
Micronas
VCT 38xxA
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
−
9
−
bit
39.2
40
40.8
%
Full Scale Output Current absolute
−
1.5
−
mA
Differential Nonlinearity
−
−
1
LSB
Integral Nonlinearity
−
−
2
LSB
Matching R-G, R-B, G-B
−2
−
2
%
Matching to digital RGB R-R, GG, B-B
−2
−
2
%
−
9
−
bit
58.8
60
61.2
%
Full Scale Output Current absolute
−
2.25
−
mA
Differential nonlinearity
−
−
1
LSB
Integral nonlinearity
−
−
2
LSB
Matching to digital RGB R-R, GG, B-B
−2
−
2
%
−
1
−
bit
19.6
20
20.4
%
Full Scale Output Current
absolute
−
0.75
−
mA
Match to digital RGB
R−R, G−G, B −B
−2
−
2
%
Test Conditions
External RGB Brightness D/A Converter Characteristics
Resolution
IEXBR
Full Scale Output Current relative
ROUT
GOUT
BOUT
Ref to max. digital RGB
RGB Output Cutoff D/A Converter Characteristics
Resolution
ICUT
Full Scale Output Current relative
ROUT
GOUT
BOUT
Ref to max. digital RGB
RGB Output Ultrablack D/A Converter Characteristics
Resolution
IUB
Micronas
Full Scale Output Current
relative
ROUT
GOUT
BOUT
Ref to max. digital RGB
163
VCT 38xxA
ADVANCE INFORMATION
6.7.3.20. Scan Velocity Modulation Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Resolution
SVMOUT
−
8
−
bit
1.55
1.875
2.25
mA
Test Conditions
IOUT
Full Scale Output Current
IOUT
Differential Nonlinearity
−
−
0.5
LSB
IOUT
Integral Nonlinearity
−
−
1
LSB
IOUT
Glitch Pulse Charge
−
0.5
−
pAs
Ramp, output line is terminated on both ends with 50 Ω
IOUT
Rise and Fall Time
−
3
−
ns
10% to 90%, 90% to 10%
6.7.3.21. Analog Audio Inputs and Outputs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
RAIN
Audio Input Resistance
AIN1-3
AOUT1-2
25
40
58
kΩ
fsignal = 1 kHz, I = 0.05 mA
dVAOUT
Deviation of DC-Level at Audio
Output from GNDAB Voltage
−20
−
+20
mV
AAudio
Gain from Audio Input to Audio
Output
−1.0
0.0
+0.5
dB
fsignal = 1 kHz
AVOL = 0dB
frAudio
Frequency Response from Audio
Input to Audio Output
bandwidth: 50 Hz to 15000 Hz
−0.5
0.0
+0.5
dB
with resp. to 1 kHz
PSRR
Power Supply Rejection Ratio for
Audio Output
tbd
50
−
dB
1 kHz sine at 100 mVRMS
tbd
20
−
dB
≤ 100 kHz sine at
100 mVRMS
VNOISE
Noise Output Voltage
−
tbd
20
µV
RGEN = 1kΩ,
equally weighted
50 Hz...15 kHz
VMute
Mute Output Voltage
−
tbd
2
µV
AVOL = mute,
equally weighted
50 Hz...15 kHz
THD
Total Harmonic Distortion from
Audio Input to Audio Output
−
−
0.1
%
Input Level = 0.7VRMS,
fsig = 1 kHz,
equally weighted
50 Hz...15 kHz
XTALK
Crosstalk attenuation between
Audio Input and Audio Output
70
−
−
dB
Input Level = 0.7VRMS,
fsig = 1 kHz,
equally weighted
50 Hz...15 kHz,
unused analog inputs
connected to ground by Z <
1 kΩ
164
Micronas
VCT 38xxA
ADVANCE INFORMATION
6.7.3.22. ADC Input Port
Symbol
Parameter
Pin Name
Min.
VREF
ADC Comparator Reference
Voltage
Px.y
−
Vlh−
Vhl
ADC Comparator Hysteresis,
symmetrical to VREF
0.1
tCDEL
ADC Comparator Delay Time
−
LSB
LSB Value
−
R
Conversion Range
GNDS
A
Conversion Result
−
Typ.
Max.
Unit
−
V
0.17
0.24
V
−
100
ns
−
V
VSUPS
V
−
hex
GNDS<Vin<VSUPS
0.5*
VSUPS
VSUPS
/1024
−
INT
(Vin/
LSB)
Test Conditions
Overdrive=50mV
000
−
−
hex
Vin<=GNDS
−
−
3FF
hex
Vin>=VSUPS
tc
Conversion Time
−
4
−
µs
ts
Sample Time
−
2
−
υs
TUE
Total Unadjusted Error
−6
−
6
LSB
DNL
Differential Non-Linearity
−3
−
3
LSB
Ci
Input Capacitance during Sampling Period
−
15
−
pF
Ri
Serial Input Resistance during
Sampling Period
−
5
−
kΩ
6.7.3.23. Universal Port
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Vol
Output Low Voltage
P1x
P2x
P3x
−
−
0.4
1.0
V
Io=3mA
Io=10mA
Voh
Output High Voltage
−
−
V
Io=−3mA
Io=−10mA
VIL
Input Low Voltage
−
−
0.8
V
VIH
Input High Voltage
2.0
−
−
V
Ii
Input Leakage Current
−0.1
−
0.1
µA
Micronas
VSUPP−0.4
VSUPP−1.0
P1x
P2x
P3x
P42−P46
0<Vi<VSUPP
165
VCT 38xxA
ADVANCE INFORMATION
6.7.3.24. Memory Port
Symbol
Parameter
Pin Name
tCYC
PH2 Cycle Time
tADS
Address Setup Time
tADH
Address Hold Time
tDWS
Data Write Setup Time
ADB[18-0]
DB[7:0]
Min.
Typ.
Max.
Unit
Test Conditions
-
98.77
-
ns
-
15
+ 0.5
20
30
19
+ 0.7
26
40
ns
ns/pf
ns
ns
CADB = 0 pF
-
8
10
ns
CADB = 10 pF
-
9
+ 0.5
14
24
14
+ 0.7
21
35
ns
ns/ pF
ns
ns
CDB = 0 pF
CDB = 0 pF
CADB = 10 pF
CADB = 30 pF
CDB = 10 pF
CDB = 30 pF
tDWH
Data Write Hold Time
-
6
8
ns
tDRS
Data Read Setup Time
12
-
-
ns
tDRH
Data Read Hold Time
6
-
-
ns
tENS
Enable Setup Time
-
6
10
ns
COEQ,WEQ = 0 pF
tENH
Enable Hold Time
-
6
9
ns
COEQ,WEQ = 0 pF
OE1Q
OE2Q
WE1Q
WE2Q
tcyc
PH2
tADS
tADH
ADB[18:0]
tACC
tDRH
tDRS
DB[7:0]
READ DATA
tDWH
tDWS
DB[7:0]
WEQ,
OEQ
WRITE DATA
tENS
tENH
Fig. 6–33: Memory port timing
166
Micronas
ADVANCE INFORMATION
VCT 38xxA
7. Application
Fig. 7–1: VCT 38xxA application circuit, part 1/3
Micronas
167
VCT 38xxA
ADVANCE INFORMATION
Fig. 7–2: VCT 38xxA application circuit, part 2/3
168
Micronas
ADVANCE INFORMATION
VCT 38xxA
Fig. 7–3: VCT 38xxA application circuit, part 3/3
Micronas
169
VCT 38xxA
170
ADVANCE INFORMATION
Micronas
VCT 38xxA
ADVANCE INFORMATION
8. Glossary of Abbreviations
AIT
Additional Information Table
BTT
Basic TOP Table
BTTL
Basic TOP Table List
CCU
Central Control Unit
CLUT
Color Look Up Table
CPU
Central Processing Unit
CRI
Clock Running-in
DMA
Direct Memory Access
DRAM
Dynamic Random Access Memory
FLOF
Full Level One Features
FRC
Framing Code
MPT
Multipage Table
MPET
Multipage Extension Table
NMI
Non Maskable Interrupt
OSD
On Screen Display
PDC
Programme Delivery Control
PLT
Page Linking Table
RAM
Random Access Memory
ROM
Read Only Memory
SRAM
Static Random Access Memory
TOP
Table Of Pages
TPU
Teletext Processing Unit
TTX
Teletext
VBI
Vertical Blanking Interval
VPS
Video-Programm-System
WSS
Wide Screen Signalling
WST
World System Teletext
Micronas
9. References
1. Preliminary Data Sheet: “VDP 31xxB”,
Sept. 25, 1998
6251-437-2PD
2. Preliminary Data Sheet: “TPU 3035, TPU 3040,
TPU 3050”,
Feb. 23, 1999
6251-349-6PD
3. Preliminary Data Sheet: “W65C02”,
Oct. 2, 1991
6251-364-1PD
4.“Enhanced Teletext Specification”.
European Telecommunication Standard ETS 300
706. ETSI, May1997.
5. “Television systems; 625-line television Wide
Screen Signalling (WSS)”. European Telecommunication Standard ETS 300 294. ETSI, May1996.
6. “Television systems; Specification of the domestic
video Programme Delivery Control system (PDC)”.
European Telecommunication Standard ETS 300
231. ETSI, August1996.
7. “Electronic Programme Guide (EPG)”. European
Telecommunication Standard ETS 300 707. ETSI,
May1997.
171
VCT 38xxA
ADVANCE INFORMATION
10. Data Sheet History
1. Advance Information: “VCT 38xxA Video/Controller/
Teletext IC Family”, Edition Oct. 17, 2000,
6251-518-1AI. First release of the advance information.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-518-1AI
172
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