MSC23S4641E-8BS16 (98.06.22) Semiconductor MSC23S4641E-8BS16 4,194,304 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK): DESCRIPTION The Oki MSC23S4641E-8BS16 is a fully decoded, 4,194,304 x 64bit synchronous dynamic random access memory composed of sixteen 16Mb DRAMs(2Mx8) in TSOP packages mounted with decoupling capacitors on a 168-pin glass epoxy Dual-in-Line Package supports any application where high density and large capacity of storage memory are required, like for example PCs or servers. FEATURES • • • • • • • • • • 4-Meg Word x 64-Bit (2Bank 8 Byte) organization 168-pin Dual Inline Memory Module All DQ Pins have 10Ω Damping Resister Single 3.3V power supply, ±0.3V tolerance Input :LVTTL compatible Output :LVTTL compatible Refresh : 4,096 cycles/64 ms Programmable data transfer mode • CAS latency(2, 3) • Burst length(1,2,4,8,Full) • Data scramble(sequential,interleave) CBR auto-refresh, Self-refresh capability Serial Presence Detect (SPD) With EEPROM PRODUCT ORGANIZATION Product Name MSC23S4641E-8BS16 Operation Frequency(Max.) 125MHz Access Time(Max.) tAC2 tAC3 10.0ns 6.0ns MSC23S4641E-8BS16 (98.06.22) BLOCK DIAGRAM CKE1 CKE0 /CS0 DQMB0 /CS2 DQMB2 /CS1 DQ0 DQM /CS CKE DQ0 DQ7 DQ7 DQM /CS CKE DQ0 1 10KΩ /CS3 DQ16 DQM /CS CKE DQ0 DQ23 DQ7 DQ7 DQ24 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQ31 DQ7 DQ7 DQ48 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQ55 DQ7 DQ7 DQ56 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQ63 DQ7 DQM /CS CKE DQ0 3 9 DQ7 11 DQMB3 DQMB1 DQ8 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQ15 DQ7 DQ7 DQ32 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQ39 DQ7 2 4 10 DQMB4 12 DQMB6 5 7 13 DQ7 DQMB5 15 DQMB7 DQ40 DQM /CS CKE DQ0 DQ47 DQ7 DQM /CS CKE DQ0 6 14 8 DQ7 16 DQ7 Serial PD SDA WP 17 SCL A0 A1 A2 47KΩ SA0 SA1 SA2 1 9 3 11 2 10 4 12 5 CLK0 13 CLK1 6 3.3pF 1 á 16 3.3pF 3.3pF Vcc 16 Two Decoupling Capacitors per SDRAM Vss 0.1uF 0.33uF Note. The Value of all resistors is 10Ω expect WP and CKE1 MODULE (Front) (Back) 1 85 OUTLINE 10 11 94 95 40 41 124 125 15 CLK3 8 14 3.3pF /RAS,/CAS,/WE A0-A11 7 CLK2 84 168 MSC23S4641E-8BS16 (98.06.22) PIN CONFIGURATION Front side Pin No. Pin name 1 VSS 2 DQ0 3 DQ1 4 DQ2 5 DQ3 6 VCC 7 DQ4 8 DQ5 9 DQ6 10 DQ7 11 DQ8 12 VSS 13 DQ9 14 DQ10 15 DQ11 16 DQ12 17 DQ13 18 VCC 19 DQ14 20 DQ15 21 N.C 22 N.C 23 VSS 24 N.C 25 N.C 26 VCC 27 /WE 28 DQMB0 29 DQMB1 30 /CS0 31 N.C 32 VSS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A10 39 N.C 40 VCC 41 VCC 42 CLK0 Pin Name VCC VSS CLK# /CS# CKE# A0-A10 A11 /RAS /CAS Back side Pin No. Pin name 85 VSS 86 DQ32 87 DQ33 88 DQ34 89 DQ35 90 VCC 91 DQ36 92 DQ37 93 DQ38 94 DQ39 95 DQ40 96 VSS 97 DQ41 98 DQ42 99 DQ43 100 DQ44 101 DQ45 102 VCC 103 DQ46 104 DQ47 105 N.C 106 N.C 107 VSS 108 N.C 109 N.C 110 VCC 111 /CAS 112 DQMB4 113 DQMB5 114 /CS1 115 /RAS 116 VSS 117 A1 118 A3 119 A5 120 A7 121 A9 122 A11(BA0) 123 N.C 124 VCC 125 CLK1 126 N.C Function Power Supply (3.3V) Ground (0V) System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Front side Pin No. Pin name 43 VSS 44 N.C 45 /CS2 46 DQMB2 47 DQMB3 48 N.C 49 VCC 50 N.C 51 N.C 52 N.C 53 N.C 54 VSS 55 DQ16 56 DQ17 57 DQ18 58 DQ19 59 VCC 60 DQ20 61 N.C 62 N.C 63 CKE1 64 VSS 65 DQ21 66 DQ22 67 DQ23 68 VSS 69 DQ24 70 DQ25 71 DQ26 72 DQ27 73 VCC 74 DQ28 75 DQ29 76 DQ30 77 DQ31 78 VSS 79 CLK2 80 N.C 81 WP 82 SDA 83 SCL 84 VCC Pin Name /WE DQMB# DQ# WP SDA SCL SA# N.C Back side Pin No. Pin name 127 VSS 128 CKE0 129 /CS3 130 DQMB6 131 DQMB7 132 N.C 133 VCC 134 N.C 135 N.C 136 N.C 137 N.C 138 VSS 139 DQ48 140 DQ49 141 DQ50 142 DQ51 143 VCC 144 DQ52 145 N.C 146 N.C 147 N.C 148 VSS 149 DQ53 150 DQ54 151 DQ55 152 VSS 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 VCC 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 VSS 163 CLK3 164 N.C 165 SA0 166 SA1 167 SA2 168 VCC Function Write Enable Data Input/Output Mask Data Input/Output Write Protect Data I/O for SPD CLK input for SPD Socket Position Address for SPD No Connection MSC23S4641E-8BS16 (98.06.22) SERIAL PRESENCE DETECT Byte No. SPD Hex Value 0 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 08 04 0B 09 02 40 00 01 80 60 00 80 08 00 01 8F 02 06 01 01 00 06 C0 A0 00 00 14 14 14 30 04 20 10 20 10 00-00 12 2D 41,45,20,20,20,20,20,20 01/06 43,32,33,53,34,36,34,31,45, 2D,38,42,53,31,36,20,20,20 20,20 91,92 00-00 93-125 64 126 F5 127 FF-FF 128-255 73-90 Remark Notes Defines the number of bytes written into SPD memory Total number of bytes of SPD memory Fundamental memory type Number of rows Number of columns Number of module banks Data width of this assembly ... Data width continuation Voltage interface level Cycle time (CL=3) Access time from CLK (CL=3) DIMM configuration type Refresh rate / type Primary SDRAM width Error checking SDRAM width Minimum CLK delay Burst lengths supported Number of banks on each SDRAM /CAS latency /CS latency /WE latency SDRAM module attributes SDRAM device attributes : General Cycle time (CL=2) Access time from CLK (CL=2) Cycle time (CL=1) Access time from CLK (CL=1) Minimum ROW pulse width /RAS to /RAS bank delay /RAS to /CAS delay Minimum /RAS precharge time Density of each bank on module 128 byte Manufacturer’s part number C23S4641E-8BS16 256 byte SDRAM 11 rows 9 columns 2 bank 64 bits 0 LVTTL CL=3 tCC=8ns CL=3 tAC3=6ns Non Parity Normal/ Self/ x8 tCCD: 1 CLK 1,2,4,8,F 2 banks 2,3 0 0 CL=2 tCC2=12ns CL=2 tAC2=10ns Not support Not support tRP=20ns tRRD=20ns tRCD=20ns tRAS=48ns 16MB Command and address signal input setup time 2ns Command and address signal input hold time 1ns Data signal input setup time 2ns Data signal input hold time 1ns R.F.U SPD data revision code 1.2 Checksum for byte 0-62 Manufacturer’s JEDEC ID code Manufacturing location Revision code R.F.U Intel specification frequency Intel specification /CAS latency Unused storage locations 100MHz CLK0-3,CL=3 MSC23S4641E-8BS16 (98.06.22) ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Rating Voltage on any pin relative to Vss Vcc supply voltage Storage temperature Symbol Value Unit VIN, VOUT Vcc,VccQ Tstg -0.5 to VCC+0.5 V -0.5 to 4.6 - 55 to 125 V °C PD* Ios Topr 16 W 50 0 to 70 mA °C Power dissipation Short circuit current Operating temperature *: Ta=25 u Recommended Operating Conditions Parameter Power supply voltage Input high voltage Input low voltage Symbol Vcc,VccQ VIH VIL Min. Typ. 3.0 2.0 -0.3 3.3 - (Voltages referenced to Vss = 0V) Max. Unit 3.6 VCC+0.3 0.8 V V V Capacitance Parameter Input capacitance(A0-A11,/RAS, /CAS,/WE) Input capacitance(/CS0,/CS1,/CS2,/CS3) Input capacitance(DQMB0-DQMB7) Input capacitance(CKE0,CKE1) I/O capacitance(DQ0-DQ63) Input capacitance(CLK0,CLK1,CLK2,CLK3) (Vcc=3.3V ± 0.3V, Ta = 25°C f=1MHz) Symbol Max. Unit CIN1 98 pF CIN2 34 pF CIN3 22 pF CIN4 58 pF CDQ 25 pF CCLK 50 pF MSC23S4641E-8BS16 (98.06.22) DC CHARACTERISTICS Parameter Condition Symbol Input Leakage Current Bank CKE Others Min Max - - - -160 160 uA ILO - - - -20 20 uA VOH - - IOH = -2mA 2.4 - V VOL - - IOL = 2mA - 0.4 V ICC1 One Bank Active CKE ≥ VIH tCC=min tRC=min No Burst - 1000 mA 1,2 Both CKE ≥ VIH - 1240 mA 1,2 - 640 mA 3 mA 2 mA 3 ILI Output Leakage Current Output High Voltage Output Low Voltage Average Power Supply Current (Operating) ICC1D Banks Power Supply Current (Stand by) Average Power Supply Current (Clock Suspenson) Average Power Supply Current (Active Stand by) Power Supply Current (Burst) ICC2 ICC3S Active Both Banks Precharge tCC=min tRC=min tRRD=min No Burst CKE ≥ VIH tCC=min CKE ≤ VIL tCC=min - 344 CKE ≥ VIH tCC=min - 680 Both Banks Active One Bank Active CKE ≥ VIH tCC=min - 1160 mA CKE ≥ VIH tCC=min tRC=min - 960 mA - 32 mA - 32 mA Both Banks Active ICC3 One Banks Active ICC4 Power Supply Current (Auto-Refresh) (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Module Note Unit Spec. ICC5 Average Power Supply Current (Self-Refresh) ICC6 Both Banks Precharge CKE ≤ VIL tCC=min Average Power Supply Current (Power down) ICC7 Both Banks Precharge CKE ≤ VIL tCC=min NOTE: 1. 2. 3. Measured with the output open. The address and data can be changed once or left uncharged during one cycle. The address and data can be changed once or left unchanged during two cycles. 1,2 2 MSC23S4641E-8BS16 (98.06.22) MODE SET ADDRESS KEYS A6 0 0 0 0 1 1 1 1 /CAS Latency A5 A4 CL 0 0 Reserved 0 1 Reserved 1 0 2 1 1 3 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved Note: Burst Type A3 BT 0 Sequential 1 Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 BT=0 0 1 1 2 0 4 1 8 0 Reserved 1 Reserved 0 Reserved 1 Full Page BT=1 1 2 4 8 Reserved Reserved Reserved Reserved A7,A8,A9, A10 and A11 should stay "L" during mode set cycle. POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level,pause for 200us or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. MSC23S4641E-8BS16 (98.06.22) AC CHARACTERISTIC Parameter Symbol (VCC = 3.3 ± 0.3V, Ta = 0 ~70°C) NOTE 1,2 Module Spec. Unit Note Min. Max. tCH 8 12 3 6 10 - ns ns ns ns ns Clock "L" Pulse Time Input Setup Time(CLK,ADD,DIN) Input Hold Time(CLK,ADD,DIN) Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock /RAS Cycle Time /RAS Precharge Time /RAS Active Time tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS 3 2 1 3 3 70 20 48 9 100,000 ns ns ns ns ns ns ns ns ns /RAS to /CAS Delay Time Write Recovery Time tRCD tWR 20 8 - ns ns Write Command Input Time from Output /RAS to /RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time tOWD tRRD tREF tPDE tT 20 20 10 - 64 3 ns ns ms ns ns /CAS to /CAS Delay Time (Min) Clock Disable Time from CKE Data Output High Impedance Time from DQM Data Input Mask Time from DQMB Data Input Time from Write Command Data Output High Inpedance Time Active Command Input Time from MODE ICCD ICKE IDOZ IDOD IDWD IROH IMRD Clock Cycle Time Access Time from Clock CL=3 CL=2 CL=3 CL=2 Clock "H" Pulse Time NOTES: 1) 2) 3) 4) 5) tCC tAC 1 1 2 0 0 CL 3 3,4 3,4 Cycle Cycle Cycle Cycle Cycle Cycle Cycle AC measurements assume that tT=1ns. The reference level for timing of input signals is 1.4V. This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF (R Load is 50ohm). An access time is measured at 1.4V. If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL. 1.4v 50Ω OUTPUT OUTPUT LOAD 50pF . MSC23S4641E-8BS16 (98.06.22) FUNCTION TRUTH TABLE (Table1)(1/2) Current State Idle Row Active Read Write Read with Auto Precharge Write with Auto Precharge /CS H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L H L L L L L L /RAS X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L /CAS X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L /WE X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X BA X X BA BA BA BA X L X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA,A10 CA,A10 RA A10 X X X X CA,A10 CA,A10 RA A10 X X X X CA,A10 CA,A10 RA A10 X X X X CA,A10 X RA,A10 X X X X CA,A10 X RA,A10 X Action NOP NOP 2 ILLEGAL 2 ILLEGAL Row Active 4 NOP 5 Auto-Refresh or Self-Refresh Mode Register write NOP NOP Read Write 2 ILLEGAL Precharge ILLEGAL NOP(Continue Row Active after Burst ends) NOP(Continue Row Active after Burst ends) Reserved Term Burst,start new Burst Read Term Burst,start new Burst Write 2 ILLEGAL Term Burst,execute Row Precharge ILLEGAL NOP(Continue Row Active after Burst ends) NOP(Continue Row Active after Burst ends) 2 ILLEGAL Term Burst,start new Burst Read Term Burst,start new Burst Write 2 ILLEGAL Term Burst,execute Row Precharge ILLEGAL NOP(Continue Burst to End and enter Row Precharge) NOP(Continue Burst to End and enter Row Precharge) 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL NOP(Continue Burst to End and enter Row Precharge) NOP(Continue Burst to End and enter Row Precharge) 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL MSC23S4641E-8BS16 (98.06.22) FUNCTION TRUTH TABLE (Table1)(2/2) Current State Precharge Write Recovery Row Active Refresh Mode Resister Access /CS H L L L L L L H L L L L L L H L L L L L L H L L L L H L L L L /RAS X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L /CAS X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X /WE X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X BA X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X Action NOP Idle after tRP NOP Idle after tRP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 4 NOP ILLEGAL NOP NOP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Row Active after tRCD NOP Row Active after tRCD 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Idle after tRC NOP Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Æ Æ Æ Æ ABBREVIATIONS RA=Row Address CA=Column Address BA=Bank Address AP=Auto Precharge NOP=No Operation command Notes: 1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state,but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of tCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. MSC23S4641E-8BS16 (98.06.22) FUNCTION TRUTH TABLE (CKE) (Table2) Current State(n) Self Refresh Power Down All Banks idle (ABI) Any State Other than Listed Above 6 CKEn-1 H L L L L L L H L L L L L L H H H H H H H H L H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X H L L L L L L X X X X X /RAS X X H H H L X X X H H H X X X X H H H L L L X X X X X /CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X /WE X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self Refresh) INVALID Exit Power Down ABI Exit Power Down ABI ILLEGAL ILLEGAL 6 ILLEGAL NOP(Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension Æ Æ Æ Æ Notes: 6. Power-down and self refresh can be entered only when all the banks are in an idle state.