FEDD51V4265E-01 1Semiconductor MSM51V4265E This version: June 2001 Previous version : 262,144-Word × 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM51V4265E is a 262,144-word × 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM51V4265E achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM51V4265E is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP. FEATURES ∙ 262,144-word × 16-bit configuration ∙ Single 3.3V power supply, ±0.3V tolerance ∙ Input : LVTTL compatible, low input capacitance ∙ Output : LVTTL compatible, 3-state ∙ Refresh : 512 cycles/8ms ∙ Fast page mode with EDO, read modify write capability ∙ CAS before RAS refresh, hidden refresh, RAS-only refresh capability ∙ Packages 40-pin 400mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM51V4265E-xxJS) 44/40-pin 400mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM51V4265E-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Family MSM51V4265E tRAC tAA tCAC tOEA Cycle Time (Min.) 60ns 70ns 30ns 35ns 15ns 20ns 15ns 20ns 104ns 124ns Power Dissipation Operating (Max.) 414mW 378mW Standby (Max.) 1.8mW 1/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 NC 12 WE 13 RAS 14 NC 15 A0 16 A1 17 A2 18 A3 19 VCC 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40-Pin Plastic SOJ VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC 13 NC 14 WE 15 RAS 16 NC 17 A0 18 A1 19 A2 20 A3 21 VCC 22 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS 44/40-Pin Plastic TSOP (K Type) Pin Name Function A0–A8 Address Input RAS Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS Upper Byte Column Address Strobe DQ1–DQ16 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (3.3V) VSS Ground (0V) NC No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E BLOCK DIAGRAM WE OE Timing Generator RAS I/O Controller LCAS UCAS I/O Controller 9 9 Output Buffers 8 Input Buffers 8 8 Input Buffers 8 8 Output Buffers 8 DQ1 – DQ8 Column Address Buffers 9 Internal Address Counter A0 – A8 8 Sense Amplifiers Refresh Control Clock Row Address Buffers 9 Row Decoders Column Decoders Word Drivers 16 I/O Selector 16 DQ9 – DQ16 Memory Cells 8 VCC On Chip VBB Generator VSS FUNCTION TABLE Input Pin DQ Pin Function Mode RAS LCAS UCAS WE OE DQ1-DQ8 DQ9-DQ16 H * * * * High-Z High-Z Standby L H H * * High-Z High-Z Refresh L L H H L DOUT High-Z Lower Byte Read L H L H L High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don’t Care Lower Byte Write L H L L H Don’t Care DIN Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High-Z * : “H” or “L” 3/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on Any Pin Relative to VSS VT –1.0 to 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C *: Ta = 25°C RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70°C) Parameter Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 VCC + 0.3 V Input Low Voltage VIL – 0.3 0.8 V Power Supply Voltage PIN CAPACITANCE (VCC = 3.3V ± 0.3V, Ta = 25°C, f = 1 MHz) Parameter Symbol Min. Max. Unit CIN1 6 pF (RAS, LCAS, UCAS, WE, OE) CIN2 7 pF Output Capacitance (DQ1 - DQ16) CI/O 7 pF Input Capacitance (A0 - A8) Input Capacitance 4/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Parameter Symbol MSM51V4265 E-60 MSM51V4265 E-70 Min. Max. Min. Max. 2.4 VCC 2.4 VCC V 0 0.4 0 0.4 V –10 10 –10 10 µA –10 10 –10 10 µA 115 105 mA 1,2 RAS, CAS = VIH 2 2 RAS, CAS ≥ VCC–0.2V mA 1 0.5 0.5 115 105 mA 1,2 5 5 mA 1 115 105 mA 1,2 115 105 mA 1,3 Condition Output High Voltage VOH IOH = −2.0mA Output Low Voltage VOL IOL = 2mA Unit Note 0V ≤ VI ≤ VCC+0.3V; Input Leakage Current ILI Output Leakage Current ILO Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) ICC1 ICC2 All other pins not under test = 0V DQ disable 0V ≤ VO ≤ VCC RAS, CAS cycling, tRC = Min. RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E AC CHARACTERISTICS (1/2) (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note 1,2,3 MSM51V4265 E-60 MSM51V4265 E-70 Min. Max. Min. Max. tRC 104 124 ns Read Modify Write Cycle Time tRWC 135 160 ns Fast Page Mode Cycle Time tHPC 25 30 ns tHPRWC 68 78 ns Access Time from RAS tRAC 60 70 ns 4, 5, 6 Access Time from CAS tCAC 15 20 ns 4,5 Access Time from Column Address tAA 30 35 ns 4,6 Access Time from CAS Precharge tCPA 35 40 ns 4,13 Access Time from OE tOEA 15 20 ns 4 Output Low Impedance Time from CAS tCLZ 0 0 ns 4 Data Output Hold After CAS Low tDOH 5 5 ns CAS to Data Output Buffer Turn-off Delay Time tCEZ 0 15 0 20 ns 7,8 RAS to Data Output Buffer Turn-off Delay Time tREZ 0 15 0 20 ns 7,8 OE to Data Output Buffer Turn-off Delay Time tOEZ 0 15 0 20 ns 7 WE to Data Output Buffer Turn-off Delay Time tWEZ 0 15 0 20 ns 7 Transition Time tT 1 50 1 50 ns 3 Refresh Period tREF 8 8 ms RAS Precharge Time tRP 40 50 ns RAS Pulse Width tRAS 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode with EDO) tRASP 60 100,000 70 100,000 ns RAS Hold Time tRSH 10 13 ns RAS Hold Time referenced to OE tROH 10 13 ns CAS Precharge Time (Fast Page Mode with EDO) tCP 10 10 ns CAS Pulse Width tCAS 10 10,000 13 10,000 ns CAS Hold Time tCSH 40 45 ns CAS to RAS Precharge Time tCRP 5 5 ns 13 RAS Hold Time from CAS Precharge tRHCP 35 40 ns 13 OE Hold Time from CAS (DQ Disable) tCHO 5 5 ns RAS to CAS Delay Time tRCD 14 45 14 50 ns 5 RAS to Column Address Delay Time tRAD 12 30 12 35 ns 6 Parameter Random Read or Write Cycle Time Fast Page Mode Read Modify Write Cycle Time Symbol Unit Note 15 6/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E AC CHARACTERISTICS (2/2) (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note 1,2,3 Parameter Symbol MSM51V4265 E-60 MSM51V4265 E-70 Min. Max. Min. Max. Unit Note Row Address Set-up Time tASR 0 0 ns Row Address Hold Time tRAH 10 10 ns Column Address Set-up Time tASC 0 0 ns 12 Column Address Hold Time tCAH 10 13 ns 12 Column Address to RAS Lead Time tRAL 30 35 ns Read Command Set-up Time tRCS 0 0 ns 12 Read Command Hold Time tRCH 0 0 ns 9,12 Read Command Hold Time referenced to RAS tRRH 0 0 ns 9 Write Command Set-up Time tWCS 0 0 ns 10,12 Write Command Hold Time tWCH 10 13 ns 12 Write Command Pulse Width tWP 10 10 ns WE Pulse Width (DQ Disable) tWPE 10 10 ns OE Command Hold Time tOEH 10 13 ns OE Precharge Time tOEP 10 10 ns OE Command Hold Time tOCH 10 10 ns Write Command to RAS Lead Time tRWL 10 13 ns Write Command to CAS Lead Time tCWL 10 13 ns 14 Data-in Set-up Time tDS 0 0 ns 11,12 Data-in Hold Time tDH 10 13 ns 11,12 OE to Data-in Delay Time tOED 15 20 ns CAS to WE Delay Time tCWD 35 45 ns 10 Column Address to WE Delay Time tAWD 50 60 ns 10 RAS to WE Delay Time tRWD 80 95 ns 10 CAS Precharge WE Delay Time tCPWD 55 65 ns 10 CAS Active Delay Time from RAS Precharge tRPC 5 5 ns 12 RAS to CAS Set-up Time (CAS before RAS) tCSR 5 5 ns 12 RAS to CAS Hold Time (CAS before RAS) tCHR 10 10 ns 13 7/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF. The output timing reference levels are VOH=2.0 (IOH= –2mA) and VOL=0.8V (IOL= 2mA). 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. tCEZ, and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high. 8/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E TIMING CHART Read Cycle RAS tRC tRAS VIH tRP VIL tCSH tCRP CAS tRCD VIH tRAD VIL tRAL tASR Address WE OE tCRP tRSH tCAS VIH tRAH tASC Row VIL tCAH Column tRCS tRRH VIH tAA VIL tRCH tROH VIH VIL tCAC tRAC DQ tREZ tOEA tCEZ tOEZ tCLZ VOH Valid Data-out Open VOL "H” or “L” Write Cycle (Early Write) RAS tRC tRAS VIH tRP VIL tCSH tCRP CAS VIH tRAD VIL tRAL tASR Address VIH VIL tRAH tASC Row OE tCWL VIH tWCH tWP VIL tRWL VIH VIL tDS DQ tCAH Column tWCS WE tCRP tRSH tCAS tRCD VIH VIL tDH Valid Data-in Open “H” or “L” 9/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E Read Modify Write Cycle tRWC RAS tRAS VIH tRP VIL tCSH tCRP CAS tRAD VIL VIH VIL tCRP tRSH tCAS VIH tASR Address tRCD tRAH Row tCWL tRWL tCAH tASC Column tCWD tRCS tRWD WE OE tWP VIH VIL tAWD tAA tOEH tOEA VIH tOED VIL tDH tCAC tRAC DQ VI/OH VI/OL tOEZ tCLZ Valid Data-out tDS Valid Data-in “H” or “L” 10/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E Fast Page Mode Read Cycle (Part-1) tRASP RAS VIH VIL Address tHPC tCSH tCRP CAS VIH VIL tRAD tASR tASC tRAH Row tRHCP tCP tCP tCAS VIH VIL tRP tRCD tCAS tCAH tASC Column tCAS tASC tCAH Column tCAH Column tRCS WE OE tOCH VIH tAA VIL tCAC tRAC tAA VIH VIL tCAC tOEP tOEA tOEA tOEZ tOEZ tDOH VOH Valid Data-out VOL tCAC tAA tCHO tOEP tCPA tOEA DQ tRRH Valid Data-out Valid * Data-out tREZ Valid * Data-out tCLZ * : Same Data, “H” or “L” Fast Page Mode Read Cycle (Part-2) tRP tRASP RAS VIH VIL tCRP tCSH Address VIH VIL tCAS tCAS tASR tRAD tRAH Row tASC tCAH OE tCAH tASC Column Column tRCS WE tCP tCP VIH VIL tCRP tHPC tRCD CAS tRHCP tHPC tCAS tASC tCAH Column tRCS VIH VIL tAA tRAC tRCH tWPE tOEA VIH tAA tCPA tAA tCAC tDOH VIL tCAC tCAC DQ VOH VOL tWEZ Valid Data-out Valid Data-out tCEZ Valid Data-out tCLZ “H” or “L” 11/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS CAS Address WE OE tCSH VIH VIL tCRP tHPC tRCD tCP VIH VIL tRAD tASR tASC tRAH Row tASC Column tWCS VIH tRSH tCAS tCAS tCAH tASC tCAH Column tWCS tWCH tCAH Column tWCS tWCH tWCH VIL VIH VIL tDS DQ tCP tCAS VIH VIL tHPC VIH tDH tDS Valid Data-in VIL tDH tDS tDH Valid Data-in Valid Data-in “H” or “L” Fast Page Mode Read Modify Write Cycle tRASP RAS CAS VIH VIL tRWD tCRP tRCD tCP VIH VIL VIH VIL tASC tASC tRAD tHPRWC tRAH Row Column VIH VIL Column VIH tAWD tAWD tAA tDS tAA tOED VI/OH tCLZ tDS tWP tOEA VIL VI/OL tWP tOEA tCAC DQ tCWD tRCS tRAC OE tCAH tCPA tCWL tCAH tRCS WE tRWL tCWD tASR Address tCPWD tOED tOEH tOEZ tDH Valid Data-out Valid Data-in tCAC tOEH tOEZ Valid Data-out tDH Valid Data-in tCLZ “H” or “L” 12/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E RAS-only Refresh Cycle RAS tRC RAS CAS Address tRAS VIH VIL tRP tRPC tCRP VIH VIL tASR VIH tRAH Row VIL tCEZ DQ VOH Open VOL Note: WE, OE = “H” or “L” “H” or “L” CAS before RAS Refresh Cycle tRP RAS CAS tRC tRAS VIH VIL tRPC tCP tRP tCSR tRPC tCHR VIH VIL tCEZ DQ VOH VOL Open Note: WE, OE, Address = “H” or “L” 13/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E Hidden Refresh Read Cycle tRC RAS CAS VIH VIL tCRP tRAS tRCD tRSH VIH tRP tRAD VIL tRAH VIH tASC Row VIL tCAH Column tRCS WE tRP tCHR tASR Address tRC tRAS tCAC VIH VIL tRRH tRAL tREZ tAA tROH OE DQ tCEZ tOEA VIH VIL tRAC tOEZ tCLZ VOH Open VOL Valid Data-out “H” or “L” Hidden Refresh Write Cycle tRC RAS CAS VIH VIL tCRP tRAS tRCD tRSH VIH tRAD VIL VIH VIL tRP tRP tCHR tASR Address tRC tRAS tRAH tASC Row tCAH Column tRAL tRWL WE tWP VIH VIL tWCS OE DQ tWCH VIH VIL VIH tDS tDH Valid Data-in VIL “H” or “L” 14/15 FEDD51V4265E-01 1Semiconductor MSM51V4265E NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 15/15