E2G0152-29-41 ¡ Semiconductor MSM5118160D/DSL ¡ Semiconductor This MSM5118160D/DSL version: Apr. 1999 Previous version: Oct. 1998 1,048,576-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM5118160D/DSL is a 1,048,576-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5118160D/DSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal CMOS process. The MSM5118160D/DSL is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP. The MSM5118160DSL (the self-refresh version) is specially designed for lower-power applications. FEATURES • 1,048,576-word ¥ 16-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (SL version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Package options: 42-pin 400 mil plastic SOJ (SOJ42-P-400-1.27) (Product : MSM5118160D/DSL-xxJS) 50/44-pin 400 mil plastic TSOP (TSOPII50/44-P-400-0.80-K)(Product : MSM5118160D/DSL-xxTS-K) (TSOPII50/44-P-400-0.80-L) (Product : MSM5118160D/DSL-xxTS-L) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM5118160D/DSL-50 50 ns 25 ns 13 ns 13 ns 90 ns 743 mW MSM5118160D/DSL-60 60 ns 30 ns 15 ns 15 ns 110 ns 688 mW MSM5118160D/DSL-70 70 ns 35 ns 20 ns 20 ns 130 ns 633 mW 5.5 mW/ 1.1 mW (SL version) 1/16 ¡ Semiconductor MSM5118160D/DSL PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 NC 12 WE 13 42 VSS 50 VSS VCC 1 VSS 50 1 VCC 41 DQ16 DQ1 2 49 DQ16 DQ16 49 2 DQ1 40 DQ15 DQ2 3 48 DQ15 DQ15 48 3 DQ2 39 DQ14 DQ3 4 47 DQ14 DQ14 47 4 DQ3 38 DQ13 DQ4 5 46 DQ13 DQ13 46 5 DQ4 45 VSS 6 VCC 37 VSS VCC 6 VSS 45 36 DQ12 DQ5 7 44 DQ12 DQ12 44 7 DQ5 35 DQ11 DQ6 8 43 DQ11 DQ11 43 8 DQ6 34 DQ10 DQ7 9 42 DQ10 DQ10 42 9 DQ7 33 DQ9 DQ8 10 41 DQ9 DQ9 41 10 DQ8 32 NC NC 11 40 NC NC 40 11 NC 31 LCAS 30 UCAS RAS 14 29 OE NC 15 28 A9 NC 15 36 NC NC 36 15 NC NC 16 27 A8 NC 16 35 LCAS LCAS 35 16 NC A0 17 26 A7 WE 17 34 UCAS UCAS 34 17 WE A1 18 25 A6 RAS 18 33 OE OE 33 18 RAS A2 19 24 A5 NC 19 32 A9 A9 32 19 NC A3 20 23 A4 NC 20 31 A8 A8 31 20 NC VCC 21 22 VSS A0 21 30 A7 A7 30 21 A0 A1 22 29 A6 A6 29 22 A1 A2 23 28 A5 A5 28 23 A2 A3 24 27 A4 A4 27 24 A3 VCC 25 26 VSS VSS 26 25 VCC 42-Pin Plastic SOJ 50/44-Pin Plastic TSOP (K Type) Pin Name A0 - A9 RAS Function Address Input Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS Upper Byte Column Address Strobe DQ1 - DQ16 OE Note : 50/44-Pin Plastic TSOP (L Type) Data Input/Data Output Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16 ¡ Semiconductor MSM5118160D/DSL BLOCK DIAGRAM WE RAS OE Timing Generator I/O Controller LCAS UCAS I/O Controller 10 Column Address Buffers 10 Internal Address Counter A0 - A9 10 Refresh Control Clock Row Address 10 Buffers Row Decoders 8 Output Buffers 8 Input Buffers 8 8 Input Buffers 8 8 DQ1 - DQ8 Column Decoders Sense Amplifiers I/O Selector 16 16 Memory Cells Word Drivers DQ9 - DQ16 8 Output Buffers 8 VCC On Chip VBB Generator On Chip IVCC Generator VSS FUNCTION TABLE Input Pin DQ Pin Function Mode RAS LCAS UCAS WE OE DQ1 - DQ8 DQ9 - DQ16 H * H * * High-Z High-Z L * H Refresh H * L High-Z L * H High-Z L DOUT High-Z Lower Byte Read L H L H L High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don't Care DIN Lower Byte Write Don't Care Standby Upper Byte Write L H L L H L L L L H DIN DIN Word Write H High-Z High-Z — L L L H *: "H" or "L" 3/16 ¡ Semiconductor MSM5118160D/DSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to VCC + 0.5 V Voltage on VCC Supply Relative to VSS VCC –0.5 to 7 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C *: Ta = 25°C Recommended Operating Conditions (Ta = 0°C to 70°C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.4 — VCC + 0.5*1 V VIL –0.5*2 — 0.8 V Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS – 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VSS is applied). Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Parameter Input Capacitance (A0 - A9) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) Symbol Typ. Max. Unit CIN1 — 5 pF CIN2 — 7 pF CI/O — 7 pF 4/16 ¡ Semiconductor MSM5118160D/DSL DC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Condition MSM5118160 MSM5118160 MSM5118160 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –5.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2 mA 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 135 — 125 — 115 mA 1, 2 — 2 — 2 — 2 — 1 — 1 — 1 mA 1 — 200 — 200 — 200 mA 1, 5 — 135 — 125 — 115 mA 1, 2 — 5 — 5 — 5 mA 1 — 135 — 125 — 115 mA 1, 2 — 135 — 125 — 115 mA 1, 3 — 300 — 300 — 300 mA — 300 — 300 — 300 mA 0 V £ VI £ 6.5 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) DQ disable 0 V £ VO £ VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, Average Power ICC3 CAS = VIH, Supply Current (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, DQ = enable Average Power ICC6 Supply Current (CAS before RAS Refresh) RAS cycling, CAS before RAS RAS = VIL, Average Power ICC7 CAS cycling, Supply Current (Fast Page Mode) tPC = Min. Average Power tRC = 125 ms, ICC10 CAS before RAS, Supply Current tRAS £ 1 ms (Battery Backup) 1, 4, 5 Average Power Supply Current (CAS before RAS ICCS RAS £ 0.2 V, CAS £ 0.2 V 1, 5 Self-Refresh) Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ VCC + 0.5 V, –0.5 V £ VIL £ 0.2 V. SL version. 5/16 ¡ Semiconductor MSM5118160D/DSL AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM5118160 MSM5118160 MSM5118160 D/DSL-60 D/DSL-50 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. 90 131 — — 110 — — tPC 35 — 155 40 — — 130 tRWC tPRWC 76 — Access Time from RAS tRAC — Access Time from CAS tCAC Access Time from Column Address Access Time from CAS Precharge tAA tCPA Access Time from OE Output Low Impedance Time from CAS Random Read or Write Cycle Time Read Modify Write Cycle Time tRC — 185 45 85 — 50 — — 13 — — 25 30 tOEA tCLZ — 0 CAS to Data Output Buffer Turn-off Delay Time tOFF OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period tOEZ tT tREF Refresh Period (SL version) ns — ns ns 100 — ns 60 — 70 ns 4, 5, 6 — 15 — 20 ns 4, 5 — — 30 35 — — 35 40 ns ns 4, 6 4, 12 13 — — 0 15 — — 0 20 — ns ns 4 4 0 0 3 — 13 13 50 16 0 0 3 — 15 15 50 16 0 0 3 — 20 20 50 16 ns ns ns ms 7 7 3 tREF — 128 — 128 — 128 ms 15 RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH RAS Hold Time referenced to OE tROH 13 13 — — 15 15 — — 20 20 — — ns ns Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time CAS Precharge Time (Fast Page Mode) tCP 7 — 10 — 10 — ns CAS Pulse Width tCAS 13 10,000 15 10,000 20 10,000 ns CAS Hold Time tCSH — — 5 — — 70 tCRP 50 5 60 CAS to RAS Precharge Time 5 — — ns ns RAS Hold Time from CAS Precharge tRHCP RAS to CAS Delay Time tRCD RAS to Column Address Delay Time tRAD 30 17 12 — 37 25 35 20 15 — 45 30 40 20 15 — 50 35 ns ns ns Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 7 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns 11 11 14 12 12 5 6 Column Address Hold Time tCAH 7 — 10 — 15 — ns Column Address to RAS Lead Time tRAL 25 — 30 — 35 — ns Read Command Set-up Time tRCS 0 — 0 — 0 — ns 11 Read Command Hold Time tRCH 0 — 0 — 0 — ns 8, 11 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 6/16 ¡ Semiconductor MSM5118160D/DSL AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM5118160 MSM5118160 MSM5118160 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. Write Command Set-up Time tWCS 0 — 0 — 0 — ns 9, 11 Write Command Hold Time tWCH 7 — 10 — 15 — ns 11 Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time tWP tOEH tRWL tCWL 7 13 — — 10 15 — — 10 20 — — ns ns 13 13 — — 15 15 — — 20 20 — — ns ns 13 Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time tDS tDH tOED tCWD tAWD tRWD 0 7 13 36 48 73 — — — — — — 0 10 15 40 55 85 — — — — — — 0 15 20 50 65 100 — — — — — — ns ns ns ns ns ns 10, 11 10, 11 CAS Precharge WE Delay Time 9 9 9 tCPWD 53 — 60 — 70 — ns 9 CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns 11 RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tCSR tCHR 10 10 — — 10 10 — — 10 10 — — ns ns 11 12 tRASS 100 — 100 — 100 — ms 15 tRPS 90 — 110 — 130 — ns 15 tCHS –50 — –50 — –50 — ns 15 RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) 7/16 ¡ Semiconductor Notes: MSM5118160D/DSL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 12. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 13. tCWL should be satisfied by both UCAS and LCAS. 14. tCP is determined by the time both UCAS and LCAS are high. 15. Only SL version. 8/16 E2G0103-29-41P ,,, , ,,,, ¡ Semiconductor MSM5118160D/DSL TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH – VIL – tCRP tCSH tCRP tRCD VIH – CAS VIL – tRAD tASR Address VIH – VIL – tRSH tCAS tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tOEA VIH – VIL – tCAC tRAC DQ tRCH tRRH VOH – tOEZ Open VOL – tOFF Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tCRP tCRP VIH – CAS VIL – WE OE VIH – VIL – tASC Row tCAS tCAH tRAL Column tWCS VIH – tWCH tCWL tWP VIL – tRWL VIH – VIL – tDS DQ tRSH tRAD tRAH tASR Address tCSH tRCD VIH – VIL – tDH Valid Data-in Open "H" or "L" 9/16 ,,, ¡ Semiconductor MSM5118160D/DSL Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tRP tCRP tCSH tCRP tRCD tRSH tCAS VIH – CAS VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tAWD tRCS tOEA tOED tCAC tRAC DQ VI/OH– VI/OL– tCWL tRWL tWP tCWD tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/16 ,, , , ,,, ¡ Semiconductor MSM5118160D/DSL Fast Page Mode Read Cycle tRASP VIH – RAS V – IL VIH – CAS VIL – Address WE VIH – VIL – tRP tRHCP tCRP tPC tRCD tCP tASR tCP tCAS tCAS tRAD tRAH tASC tCSH tCAH tASC Column Row VIH – VIL – tCAC VOH – DQ VOL – Column tRCS tRCH tRRH tCPA tOEA tOFF tOEZ tRCH tAA tAA tCAC tOEA tOFF tCAC tOEZ tCLZ Valid Data-out tCLZ tRCS tCPA tOEA tRAC tRAL tCAH tASC Column tAA VIH – OE VIL – tCAS tCAH tRCH tRCS tCRP tRSH tCLZ tOFF tOEZ Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tPC VIH – RAS V – IL tCRP VIH – CAS VIL – Address VIH – VIL – tCAS tASR tRAH tASC Row tRAD VIH – VIL – tDS DQ VIH – VIL – tRHCP tRSH tRCD tWCS WE tRP tCSH tCAH Column tCWL tWCH tWP tDH Valid Data-in tCP tCRP tCP tCAS tASC tCAH tASC Column tCWL tWCS tWCH tWP tDS tDH Valid Data-in tCAS tCAH tRAL Column tRWL tCWL tWCS tWCH tWP tDS tDH Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/16 ¡ Semiconductor MSM5118160D/DSL ,, , , , , , Fast Page Mode Read Modify Write Cycle tRASP VIH – RAS VIL – tRP tCSH tPRWC tRCD VIH – CAS VIL – tASC tCAH tRAH VIH – VIL – tCRP tCAS tASC tCAH tCAH Column Column tASC Column Row tRCS tCPWD tCWD tRWD tCWD tRCS V WE IH – VIL – tCWL tAWD tCWL tWP tDH VI/OH– VI/OL – Out tCLZ tOEA tOED tOEZ tCAC In tDH tDS tOEA tOEZ tCAC tWP tCPA tAA tOED VIH – OE V – IL tCWL tROH tWP tDH tDS tOEA tRWL tAWD tCPA tAA tAA tRAL tRCS tCPWD tCWD tAWD tDS tRAC DQ tCP tCAS tRAD tASR Address tCP tCAS tRSH Out tOED In tCLZ tOEZ tCAC Out In tCLZ "H" or "L" RAS-Only Refresh Cycle tRC RAS CAS Address VIL – VIH – VIL – VIH – VIL – tRP tRAS VIH – tCRP tASR tRPC tRAH Row tOFF DQ VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L" 12/16 ^ ] \ ¡ Semiconductor MSM5118160D/DSL CAS before RAS Refresh Cycle tRC tRP RAS tRP tRAS VIH – VIL – tRPC tRPC tCP CAS tCSR tCHR VIH – VIL – , ,, , tOFF DQ VOH – VOL – Open Note: WE, OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRAS RAS tRP VIL – VIH – VIL – VIH – VIL – tRSH tRCD tRAD tASC tRAH tASR Address tRAS tRP VIH – tCRP CAS tRC Row tCHR tCAH Column tRCS tRAL VIH – WE V IL – tRRH tAA tROH tOEA VIH – OE V IL – tRAC DQ VOH – VOL – tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" 13/16 ¡ Semiconductor MSM5118160D/DSL Hidden Refresh Write Cycle tRC tRAS VIH – VIL – RAS VIH – VIL – Address tCRP tRCD tRSH tRAD tASC tASR tCAH tRAH Row WE VIH – VIL – OE VIH – VIL – tCHR tRAL Column tWCS tDS VIH – VIL – DQ tRP , ,,,, , VIH – VIL – CAS tRC tRAS tRP tWCH tWP tWRP tWRH tDH Valid Data-in "H" or "L" CAS before RAS Self-Refresh Cycle tRASS tRP VIH – RAS VIL – tRPC tCP CAS tRPS tRPC tCHS tCSR VIH – VIL – tOFF DQ VOH – VOL – Open Note: WE, OE, Address = "H" or "L" Only SL version "H" or "L" 14/16 ¡ Semiconductor MSM5118160D/DSL PACKAGE DIMENSIONS (Unit : mm) SOJ42-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.86 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MSM5118160D/DSL (Unit : mm) TSOPII50/44-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.60 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16 E2Y0002-29-11 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan