CDC2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS597 – DECEMBER 1997 D D D D D D D D PW PACKAGE (TOP VIEW) Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Ten Outputs Single Output Enable Terminal Controls All Ten Outputs External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3-V VCC Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC G FBOUT 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CLK AVCC VCC 1Y9 1Y8 GND GND 1Y7 1Y6 1Y5 VCC FBIN description The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC2510 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDC2510 is characterized for operation from 0°C to 70°C. FUNCTION TABLE OUTPUTS INPUTS CLK 1Y (0:9) X L L L L H L H H H H H G FBOUT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDC2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS597 – DECEMBER 1997 functional block diagram G 11 3 4 5 8 9 15 16 CLK 24 ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 17 PLL FBIN AVCC 13 20 21 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 23 12 AVAILABLE OPTIONS PACKAGE 2 1Y0 TA SMALL OUTLINE (PW) 0°C to 70°C CDC2510PWR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FBOUT CDC2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS597 – DECEMBER 1997 Terminal Functions TERMINAL NAME NO. TYPE DESCRIPTION CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CDC2510 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. G 11 I Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has and integrated 25-Ω series-damping resistor. 1Y (0:9) 3, 4, 5, 8, 9 15, 16, 17, 20, 21 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via the G input. These outputs can be disabled to a logic-low state by deasserting the G control input. Each output has an integrated 25-Ω series-damping resistor. AVCC 23 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC GND 2, 10, 14, 22 Power Power supply 6, 7, 18, 19 Ground Ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CDC2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS597 – DECEMBER 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions (see Note 4) MIN MAX VCC VIH Supply voltage 3 3.6 High-level input voltage 2 VIL VI Low-level input voltage IOH IOL UNIT V V 0.8 V V High-level output current VCC –12 mA Low-level output current 12 mA 70 °C Input voltage 0 TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II ICC§ ∆ICC Ci Co TEST CONDITIONS VCC II = –18 mA IOH = –100 µA MIN TYP‡ 3V MIN to MAX IOH = –12 mA IOH = – 6 mA IOL = 100 µA IOL = 12 mA 3V VCC – 0.2 2.1 3V 2.4 VI = VCC or GND, One input at VCC – 0.6 V, IO = 0, Outputs: low or high Other inputs at VCC or GND 0.2 0.8 3V 0.55 V 3.6 V ±5 µA 3.6 V 10 µA 3.3 V to 3.6 V 500 µA VI = VCC or GND VO = VCC or GND POST OFFICE BOX 655303 V 3V 3.3 V 4 pF 3.3 V 6 pF ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § For ICC of AVCC, see Figure 5. 4 UNIT –1.2 V MIN to MAX IOL = 6 mA VI = VCC or GND MAX • DALLAS, TEXAS 75265 CDC2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS597 – DECEMBER 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature fclock Clock frequency Input clock duty cycle Stabilization time† MIN MAX UNIT 25 125 MHz 40% 60% 1 ms † Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Note 5 and Figures 1 and 2)‡ PARAMETER tphase error, reference (see Figure 3) tphase error – jitter (see Note 6) tsk(o)§ Jitter(pk-pk) Duty cycle reference (see Figure 4) VCC = 3.3 V ± 0.165 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) 66 MHz < CLKIN↑ < 100 MHz FBIN↑ CLKIN↑ = 100 MHz FBIN↑ Any Y or FBOUT Any Y or FBOUT 200 ps F(clkin > 66 MHz) Any Y or FBOUT –100 100 ps Any Y or FBOUT 43% 55% MIN TYP –500 MAX MIN –50 TYP MAX –0.7...0.1 ns – 310 ps tr Any Y or FBOUT 1.3 1.9 0.8 2.1 tf Any Y or FBOUT 1.7 2.3 1.2 2.5 ‡ These parameters are not production tested. § The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 6. Phase error does not include jitter. The total phase error is – 600 ps to 50 ps for the 5% VCC range. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns 5 CDC2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS597 – DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION 3V Input 50% VCC 0V tpd From Output Under Test 30 pF 500 W Output 2V 0.4 V tr LOAD CIRCUIT FOR OUTPUTS 50% VCC VOH 2V 0.4 V VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms CLKIN FBIN tphase error FBOUT Any Y tsk(o) Any Y Any Y tsk(o) Figure 2. Phase Error and Skew Calculations 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS597 – DECEMBER 1997 TYPICAL CHARACTERISTICS PHASE ERROR vs CLOCK FREQUENCY OUTPUT DUTY CYCLE vs CLOCK FREQUENCY 0 57% VDD = 3.3 V TA = 25°C –0.1 VDD = 3.3 V CL = 30 pF 55% 53% Output Duty Cycle –0.3 –0.4 –0.5 –0.6 51% 49% 47% –0.7 45% –0.8 –0.9 25 35 45 55 65 75 85 95 43% 105 115 125 30 40 fclk – Clock Frequency – MHz 50 60 70 80 90 100 110 120 130 fclk – Clock Frequency – MHz Figure 3 Figure 4 ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY 9 VDD = 3.3 V TA = 25°C 8 Analog Supply Current – mA Phase Error – ns –0.2 7 6 5 4 3 2 1 0 25 35 45 55 65 75 85 95 105 115 125 fclk – Clock Frequency – MHz Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CDC2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS597 – DECEMBER 1997 MECHANICAL INFORMATION PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 1,20 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: D. E. F. G. 8 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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