IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER FEATURES: frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CSPF2510C operates at 3.3V and provides integrated series-damping resistors that make it ideal for driving point-to-point loads, single or dual. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the control G input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSPF2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CSPF2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for the test purposes by strapping AVDD to ground. The CSPF2510C is characterized for operation from 0°C to +85°C. This device is also available (on special order) in Industrial (-40°C to +85°C) temperatures. See Ordering Information for more details. • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to synchronize the output to the clock input signal • On-chip series damping resistors with each driver • No external RC network required for PLL loop stability • Operates at 3.3V VDD • tpd Phase Error at 133MHz: < ±150ps • Jitter (cycle-cycle)(peak-to-peak) at 66MHz to 133MHz: | 70 | ps • Spread Spectrum Compatible • Operating frequency 25MHz to 140MHz • Fully conforms to PC133 specifications • Available in 24-Pin TSSOP package DESCRIPTION: The IDTCSPF2510C is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both FUNCTIONAL BLOCK DIAGRAM 11 G 3 Y0 4 Y1 5 Y2 8 Y3 9 Y4 15 Y5 16 Y6 17 CLK 24 Y7 PLL 20 13 Y8 FBIN 21 AV DD Y9 23 12 FBOUT The IDT logo is a registered trademark of Integrated Device Technology, Inc. 0ººC TO 85ººC TEMPERATURE RANGE AUGUST 2002 1 c 2002 Integrated Device Technology, Inc. DSC-5409/6 IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) AGND 1 24 CLK VDD 2 23 AVDD Y0 3 22 VDD Y1 4 21 Y9 Y2 5 20 Y8 19 GND GND 6 Symbol Rating Max VDD Supply Voltage Range –0.5 to +4.6 V VI(1) VO(1,2) Input Voltage Range Voltage range applied to any –0.5 to +6.5 –0.5 to VDD + 0.5 V V IIK output in the high or low state Input clamp current –50 mA (VI <0) IOK Terminal Voltage with Respect ±50 mA (VO <0 or VO > VDD) to GND (inputs VIH 2.5, VIL 2.5) Continuous Output Current ±50 mA ±100 – 65 to +150 mA °C +150 °C GND 7 18 GND IO (VO = 0 to VDD) Y3 8 17 Y7 VDD or GND TSTG Continuous Current Storage Temperature Range Y4 9 16 Y6 TJ Junction Temperature VDD 10 15 Y5 G 11 14 VDD FBOUT 12 13 FBIN Unit NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. TSSOP TOP VIEW CAPACITANCE Parameter CIN APPLICATIONS: Description Input Capacitance Min. Typ. Max. Unit 5 pF 6 pF 25 pF VI = VDD or GND • SDRAM Modules • PC Motherboards • Workstations CO Output Capacitance VC = VDD or GND CL Load Capacitance NOTE: 1. Unused inputs must be held high or low to prevent them from floating. RECOMMENDED OPERATING CONDITIONS Symbol VDD, AVDD TA Min. Max. Unit Power Supply Voltage Description 3 3.6 V Operating Free-Air Temperature 0 +85 °C 2 IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE PIN DESCRIPTION Terminal Name No. Type CLK 24 I Description Clock input. CLK provides the clock signal to be distributed by the CSPF2510C clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The G 11 I Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When FBOUT 12 O integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25Ω series-damping resistor. Y (0:9) 3, 4, 5, 8, 9, O 15, 16, 17, Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G input. These outputs can be disabled to a logic-low state by de-asserting the G control input. Each output has an integrated 25Ω series-damping resistor. 20, 21 AVDD 23 Power Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VDD 2, 10, 14, 22 Power Power supply GND 6, 7, 18, 19 Ground Ground STATIC FUNCTION TABLE (AVDD = 0V) Inputs DYNAMIC FUNCTION TABLE (AVDD = 3.3V) Outputs Inputs Outputs G CLK Y (0:9) FBOUT G L L L L X L L L L H L H L running L running in H H H H H L L L L H L H H running running running H running running in running in phase with CLK phase with CLK H H H H CLK Y (0:9) FBOUT phase with CLK 3 IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) Symbol Test Conditions VDD Min. Typ. Max. Unit VIH Input HIGH Level 2 V VIL Input LOW Level 0.8 V VIK II = -18mA 3V – 1.2 V IOH = -100µA Min. to Max. VDD – 0.2 VOH IOH = -12mA 3V 2.1 IOH = -6mA 3V 2.4 IOL = 100µA Min. to Max. 0.2 IOL = 12mA 3V 0.8 VOH V V 3V 0.55 VI = VDD or GND 3.6V ±5 µA IDD VI = VDD or GND, AVDD = GND, IO = 0, Outputs: LOW or HIGH 3.6V 10 µA ∆IDD One input at VDD - 0.6V, other inputs at VDD or GND 3.3V to 3.6V 500 µA CPD Power Dissipation Capacitance 3.6V 10 14 pF AVDD = 3.3V 10 mA IOL = 6mA II (2) AVDD Power Supply Current IDDA NOTES: 1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions. 2. For IDD of AVDD, see TYPICAL CHARACTERISTICS. TIMING REQUIREMENTS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Min. Max. Unit 25 140 MHz Input clock duty cycle 40% 60% Stabilization time(1) 1 Clock frequency fCLOCK ms NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 25pF VDD = 3.3V ± 0.165V Parameter (1) tPHASE error (2) From (Input) To (Output) Min. Typ. Max. Min. Typ. Max. Unit 100MHz < CLK↑ < 133MHz FBIN↑ – 150 150 ps 1.3 1.9 0.8 1.7 2.5 0.8 tPHASE error – jitter(2,4) CLK↑ = 133MHz FBIN↑ – 50 tSK(o) (3) Any Y (133MHz) Any Y Jitter (cycle-cycle) CLK = 66MHz to 133MHz Any Y or FBOUT (peak-to-peak) CLK = 100MHz to 133MHz Any Y or FBOUT CLK = 133MHz Any Y or FBOUT Duty cycle reference (5) VDD = 3.3V ± 0.3V tR Any Y or FBOUT tF Any Y or FBOUT 50 NOTES: 1. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 2. See PARAMETER MEASUREMENT INFORMATION. 3. The tSK(O) specification is only valid for equal loading of all outputs. 4. Phase error does not include jitter. 5. See TYPICAL CHARACTERISTICS. 4 45 | 70 | | 65 | ps 150 ps ps 55 % 2.1 ns 2.5 ns ps IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION(2) 3V From Output Under Test See Note 5 0V Input t PHA SE ER R OR C L = 25pF 2V 0.4V 500 Ω (1) Output or FBIN See Note 5 tR tF Load Voltage Waveforms Propagation Delay Times Load Circuit Waveforms PHASE ERROR AND SKEW CALCULATIONS (3,4,5) CLK FBIN CLK ERRO R Y C L = 25pF CSPF2510C F BIN tPHASE (1) 500 Ω on each Y output FBOUT F BOU T Any Y t SK(o) CF PCB TR AC E Any Y Any Y t SK(o) NOTES: 1. CL includes probe and jig capacitance. 2. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz, ZO = 50Ω, tR ≤ 1.2 ns, tF ≤ 1.2 ns. 3. The outputs are measured one at a time with one transition per measurement. 4. Phase error measurements require equal loading at outputs Y and FBOUT. CF = CL – CFBIN – CPCBTRACE; CFBIN ≅ 6pF. 5. V threshold set at 1.5V across Voltage/Temp operating range. 5 V OH 2V 0.4V VOL IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE TYPICAL CHARACTERISTICS Phase Error vs Clock Frequency AVDD and VDD = 3.3V Ta = 25C 200 150 100 Time (ps) 50 0 -50 -100 -150 -200 Clock Frequency (MHz) Analog Supply Current vs. Clock Frequency AVDD and VDD = 3.3V Ta = 25C 16 14 Analog Current (mA) 12 10 8 6 4 2 0 25 33 66 100 Clock Frequency (MHz) 6 133 140 IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE TYPICAL CHARACTERISTICS (continued) Output Duty Cycle vs Clock Frequency AV DD and V DD = 3.3V Ta = 25C 55.00 54.00 53.00 Time (ps) 52.00 51.00 50.00 49.00 48.00 47.00 46.00 45.00 25 50 66 100 133 140 Clock Frequency (MHz) Jitter vs. Clock Frequency Avcc and Vcc = 3.3V Ta = 25C 100 90 80 70 Jitter (ps) 60 50 40 Peak to Peak 30 20 10 Cycle to Cycle 0 50 66 100 133 Clock Frequency (MHz) NOTE: Refer to note 5 (page 5) for test conditions. 7 140 150 IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE ORDERING INFORMATION IDTCSP XXXXX Device Type XX Package X Process Blank I 0°C to +85°C (Standard) -40°C to +85°C (Industrial) PG PGG Thin Shrink Small Outline Package TSSOP - Green F2510C 3.3V Phase-Lock Loop Clock Driver DATA SHEET DOCUMENT HISTORY 4/15/2002 Added Commercial temp. 7/31/2002 Removed Commercial Temp and put in 0C to 85C instead. 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