OKI MSM7540

FEDL7540-03
FEDL7540-03
¡ Semiconductor
MSM7540/7560
¡ Semiconductor
This version:
Nov. 1999
MSM7540/7560
Previous version: Aug. 1998
Single Rail ADPCM CODEC
GENERAL DESCRIPTION
The MSM7540/7560 are single channel ADPCM CODEC ICs which perform mutual transcoding
between an analog voice band signal 300 to 3400 Hz and 32 kbps ADPCM serial data.
Using advanced circuit technology, these devices operate using a single 5 V power supply and
have low power consumption.
The MSM7540/7560 are optimized for advanced digital cordless telephone system applications.
FEATURES
• Single 5 V Power Supply Operation
• ADPCM Algorithm :
Complies completely with 1988's version ITU-T
G.721 (32 kbps)
• Transmit/Receive Full-Duplex Operation
• Transmit/Receive Synchronous Mode Only
• Serial ADPCM Transmission Data Rate :
32 kbps to 2048 kbps
• Serial PCM Transmission Data Rate :
64 kbps to 2048 kbps
• PCM Interface Coding Format
MSM7540 :
A-law or Linear (14-bit, 2's compliment) Selectable
MSM7560 :
m-law or Linear (14-bit, 2's compliment) Selectable
• Low Power Consumption
Operating Mode :
60 mW Typ.
Power-Down Mode :
1.0 mW Typ.
• Two Analog Input Amplifier Stages :
Externally Adjustable Gain
• Analog Output Stage :
Push-pull Drive (direct drive of 350 W␣ + 120 nF)
• Built-in Crystal Oscillator (10.368 MHz)
• Built-in Reference Voltage Supply
• Option Reset Specified by ITU-T G. 721/ADPCM
• Package:
28-pin plastic SOP
(SOP28-P-430-1.27-K) (Product name: MSM7540GS-K)
(Product name: MSM7560GS-K)
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GSX1
AIN2
X2
–
+
RCLPF
–
+
A/D
Conv.
0
BPF
1
1
COMPANDER
0
ADPCM
CODER
P
/
S
XSYNC
IS
BCLKA
0
P
/
S
PCMSO
S
/
P
PCMSI
¡ Semiconductor
AIN1
X1
BLOCK DIAGRAM
V DD AG DG
GSX2
SG
V REF
1
PDN
MCK
RES
CLOCK/
TIMING
BCLKB
LPS
AOUT+
–1
AOUT–
–
+
S
/
P
PCMRI
PCMRO
0
P
/
S
ADPCM
DECODER
S
/
P
1
PWI
VFRO
D/A
Conv.
1
LPF
0
EXPANDER
0
1
IR
RSYNC
FEDL7540-03
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MSM7540/7560
RCLPF
FEDL7540-03
MSM7540/7560
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
RES 1
28 BCLKB
PCMRI 2
27 BCLKA
PCMRO 3
26 XSYNC
IR 4
25 RSYNC
IS 5
24 MCK
PCMSI 6
23 X2
PCMSO 7
22 X1
LPS 8
21 PDN
DG 9
20 VDD
AG 10
19 AOUT+
SG 11
18 AOUT–
AIN1 12
17 PWI
GSX1 13
16 VFRO
AIN2 14
15 GSX2
28-Pin Plastic SOP
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FEDL7540-03
MSM7540/7560
¡ Semiconductor
PIN AND FUNCTIONAL DESCRIPTIONS
AIN1, AIN2, GSX1, GSX2
Transmit analog inputs and the output for transmit gain adjustment.
AIN1 (AIN2) connects to the inverting input of the internal transmit amplifier. GSX1 (GSX2)
connects to the internal transmit amplifier output. Refer to Fig. 1 for gain adjustment.
VFRO, AOUT+, AOUT–, PWI
Receive analog output and the output for receive gain adjustment.
VFRO is the receive filter output. AOUT+ and AOUT– are differential analog signal outputs
which can directly drive ZL = 350 W + 120 nF. Refer to Fig. 1 for gain adjustment.
Analog Input
C1
R1
AIN1
–
+
R2
GSX1
C2
R3
AIN2
–
to ENCODER
+
R4
GSX2
Transmit Gain:
= (R2/R1) ¥ (R4/R3)
VFRO
RS*
Receive Gain:
= (R6/R5)
from DECODER
R5
PWI
R6
–
AOUT–
+
Z L =120 nF
+ 350 W
V0
Analog Output
–1
AOUT+
* : Side Tone Pass (Gain = R6/RS)
Figure 1 Analog Input/Output Interface
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FEDL7540-03
¡ Semiconductor
MSM7540/7560
SG
Analog signal ground voltage output.
The output voltage of this pin is approximately 2.4 V. Put bypass capacitors between this pin
and the AG pin. During power-down this output voltage is 0 V. The external SG voltage, if
necessary, should be used via a buffer.
AG
Analog ground.
DG
Digital ground.
This ground is separated internally from the analog signal ground pin (AG). The DG pin must
be kept as close as possible to AG on the PCB.
VDD
+5 V power supply.
LPS
PCM coding law selection.
MSM7540 only ; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
A-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).
MSM7560 only ; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
m-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).
PDN
Power down control input.
If this pin is "0", this device is in the power-down state.
Normally, this pin is set to "1".
RES
Optional reset input specified by ITU-T Recommendation G. 721.
If this pin is "0", the device is in the reset state. The reset width (during "L") should be 125ms or
more.
MCK
Master clock input.
The frequency must be 10.368 MHz. The master clock signal may be asynchronous to BCLKA,
BCLKB, XSYNC, and RSYNC.
PCMSO
Transmit PCM data output.
PCM is output from MSB in synchronization with the rising edge of BCLKB and XSYNC.
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FEDL7540-03
¡ Semiconductor
MSM7540/7560
PCMSI
Transmit PCM data input.
This signal is converted to the transmit ADPCM data. PCM is shifted in synchronization with
the falling edge of BCLKB. Normally, this pin is connected to PCMSO.
PCMRO
Receive PCM data output.
PCM is the output signal after ADPCM decoder processing. This signal is output serially from
MSB in synchronization with the rising edge of BCLKB and RSYNC.
PCMRI
Receive PCM data input.
PCM is shifted on the falling edge of the BCLKB and input from MSB. Normally, this pin is
connected to PCMRO.
IS
Transmit ADPCM signal output.
After having encoded PCM with ADPCM, this signal is output from MSB in synchronization
with the rising edge of BCLKA and XSYNC . This pin is an open drain output and remains in a
high impedance state during power-down. IS requires a pull-up resistor.
IR
Receive ADPCM signal input.
The ADPCM signal is shifted in series and synchronization with the falling edge of BCLKA and
RSYNC, starting with MSB.
BCLKB
Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI).
The frequency is set in the 64 kHz to 2048 kHz range.
XSYNC
8 kHz synchronous signal input for transmit PCM and ADPCM data.
Synchronize this signal with BCLKA and BCLKB signal. XSYNC is used to indicate the MSB of
the serial PCM and ADPCM data stream.
Be sure to input the XSYNC signal because it is also used as the input of the timing generator.
RSYNC
8 kHz synchronous signal input for receive PCM and ADPCM data.
Synchronize this signal with BCLKA and BCLKB signal. RSYNC is used to indicate the MSB of
the serial PCM and ADPCM data stream.
BCLKA
Shift clock input for the ADPCM data (IS, IR).
The frequency is set in the range of 32 kHz to 2048 kHz.
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MSM7540/7560
¡ Semiconductor
X1, X2
Crystal oscillator (10.368 MHz) connection.
Connect X2, the clock output pin, directly to the MCK pin.
When using a conventional external clock of 10.368 MHz, X1 should be connected to the ground,
leave X2 open, and provide the external clock through the MCK pin.
<Using a self-oscilation circuit>
<Using an external clock>
MSM7540/60
MSM7540/60
X1
X2
10.368 MHz
MCK
X1
X2
MCK
10.368 MHz
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FEDL7540-03
MSM7540/7560
¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
VDD
—
–0.3 to +7
V
Analog Input Voltage
VAIN
—
–0.3 to VDD + 0.3
V
Digital Input Voltage
VDIN
—
–0.3 to VDD + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
Power Supply Voltage
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Min.
Typ.
Max.
Unit
Power Supply Voltage
Parameter
VDD
Voltage must be fixed
4.5
—
5.5
V
Operating Temperature
Ta
—
–25
+25
+70
°C
Input High Voltage
VIH
2.2
—
VDD
V
0
—
0.6
V
–0.01%
10.368
+0.01%
MHz
32
—
2048
kHz
MCK, XSYNC, RSYNC, PCMRI,
PCMSI, BCLKA, BCLKB, IR,
LPS, PDN, RES
MCK, XSYNC, RSYNC, PCMRI,
Input Low Voltage
VIL
PCMSI, BCLKA, BCLKB, IR,
LPS, PDN, RES
Master Clock Frequency
Bit Clock Freqency
Synchronous Signal Frequency
fMCK
MCK
fBCKA
BCLKA
fBCKB
BCLKB
64
—
2048
kHz
fSYMC
XSYNC, RSYNC
—
8.0
—
kHz
MCK, BCLKA, BCLKB
30
50
70
%
—
—
50
ns
—
—
50
ns
Clock Duty Ratio
DC
Digital Input Rise Time
tIr
MCK, XSYNC, RSYNC, PCMRI,
PCMSI, BCLKA, BCLKB, IR,
LPS, PDN, RES
MCK, XSYNC, RSYNC, PCMRI,
Digital Input Fall Time
tIf
PCMSI, BCLKA, BCLKB, IR,
LPS, PDN, RES
tXS
BCLKA, BCLKB to XSYNC
100
—
—
ns
tXS
XSYNC to BCLKA, BCLKB
100
—
—
ns
tRS
BCLKA, BCLKB to RSYNC
100
—
—
ns
tSR
RSYNC to BCLKA, BCLKB
100
—
—
ns
Synchronous Signal Width
tWS
XSYNC, RSYNC
1 BCLK
—
100
ms
PCM, ADPCM Set-up Time
tDS
—
100
—
—
ns
PCM, ADPCM Hold Time
tDH
—
100
—
—
ns
Transmit Sync Signal Setting Time
Receive Sync Signal Setting Time
Digital Output Load
Bypass Capacitor for SG
RDL
IS (Pull-up Resistor)
500
—
—
W
CDL
IS, PCMSO, PCMRO
—
—
100
pF
CSG
SG´GND
—
10 + 0.1
—
mF
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FEDL7540-03
MSM7540/7560
¡ Semiconductor
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C)
Parameter
Symbol
IDD1
Power Supply Current
IDD2
Condition
Operating Mode,
(When no signal, and VDD = 5.0 V)
Power Down Mode
(When VDD = 5.0 V)
Min.
Typ.
Max.
Unit
—
12
24
mA
—
0.2
0.5
mA
Input High Voltage
VIH
—
2.2
—
VDD
V
Input Low Voltage
VIL
—
0.0
—
0.6
V
Input Leakage Current
Output Low Voltage
IIH
VI = VDD
—
—
2.0
mA
IIL
VI = 0 V
—
—
0.5
mA
VOL
1 LSTTL, Pull-up: 500 W
0.0
0.2
0.4
V
IS
—
—
10
mA
—
—
5
—
pF
Condition
Output Leakage Current
IO
Input Capacitance
CIN
Transmit Analog Interface Characteristics
Parameter
*
Min.
Typ.
Max.
Unit
Input Resistance
Symbol
RINX
AIN1, AIN2
10
—
—
MW
Output Load Resistance
RLGX
GSX1, GSX2
50
—
—
kW
Output Load Capacitance
CLGX
GSX1, GSX2
—
—
100
pF
Output Amplitude
VOGX
GSX1, GSX2, RL = 50 kW
—
—
*2.226
VPP
Input Offset Voltage
VOFGX
Pre–OPAMPs
–20
—
+20
mV
SG Output Voltage
VSG
—
—
2.4
—
V
SG Output Impedance
RSG
—
—
40
80
kW
SG Rise Time
TSG
—
700
—
ms
SG´GND 10 mF + 0.1 mF
(Rise time to 90% of max. level)
–3 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 2.226 VPP (MSM7540)
–3 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 2.226 VPP (MSM7560)
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MSM7540/7560
¡ Semiconductor
Receive Analog Interface Characteristics
Parameter
Input Resistance
Output Load Resistance
Output Capacitance
Output Voltage Level
Symbol
RINPW PWI
Open Loop Gain
*
Min.
Typ.
Max.
Unit
10
—
—
MW
RLVF
VFRO
50
—
—
kW
RLAO
AOUT+, AOUT–
1.2
—
—
kW
CLVF
VFRO
—
—
100
pF
CLAO
AOUT+, AOUT–
VOVF
VFRO
VOAO
AOUT+,
AOUT–
VOFVF
Offset Voltage
Condition
VOFAO
GDB
—
—
100
pF
RL = 50 kW
—
—
*2.226
VPP
RL = 1.2 kW
—
—
*2.226
VPP
—
—
*2.226
VPP
–100
—
+100
mV
–20
—
+20
mV
40
—
—
dB
ZL = 350 W
+ 120 nF(See Fig.1)
VFRO
AOUT+, AOUT– (GAIN = 0 dB),
Power amp only
Power amp (0.3 to 3.4 kHz,
ZL = 350 W + 120 nF)(See Fig.1)
–3 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 2.226 VPP (MSM7540)
–3 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 2.226 VPP (MSM7560)
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MSM7540/7560
¡ Semiconductor
AC Chracteristics
(VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C)
Condition
Parameter
Symbol
Freq.
Level
(Hz)
(dBm0)
LOSS T1
0 to 60
Others
LOSS T2 300 to 3000
Transmit Frequency
LOSS T3
1020
Response
LOSS T4
3300
Receive Frequency
Response
to Distortion Ratio
Receive Signal
to Distortion Ratio
Transmit Gain
Tracking
Receive Gain
Tracking
Typ.
Max.
Unit
25
—
—
dB
—
+0.20
–0.15
0
—
Reference
dB
dB
–0.15
—
+0.80
dB
LOSS T5
3400
0
—
0.80
dB
LOSS T6
3968.75
14
—
—
dB
–0.15
—
+0.20
LOSS R1
0 to 3000
LOSS R2
1020
LOSS R3
3300
LOSS R4
3400
LOSS R5
3968.75
SD T1
Transmit Signal
Min.
0
—
3
SD T2
SD T3
Reference
0
1020
–30
(*1)
dB
dB
–0.15
—
+0.80
dB
0
—
0.80
dB
14
—
—
dB
35
—
—
dB
35
—
—
dB
35
—
—
dB
—
dB
SD T4
–40
28
—
SD T5
–45
23
—
—
dB
SD R1
3
35
—
—
dB
35
—
—
dB
35
—
—
dB
SD R2
SD R3
0
1020
–30
(*1)
SD R4
–40
28
—
—
dB
SD R5
–45
23
—
—
dB
GT T1
3
–0.2
—
+0.2
dB
GT T2
–10
GT T3
–0.2
—
+0.2
dB
–50
–0.5
—
+0.5
dB
GT T5
–55
–1.2
—
+1.2
dB
GT R1
3
–0.2
—
+0.2
dB
GT R2
–10
1020
–40
dB
GT T4
GT R3
1020
Reference
–40
—
Reference
dB
–0.2
—
+0.2
dB
GT R4
–50
–0.5
—
+0.5
dB
GT R5
–55
–1.2
—
+1.2
dB
—
*1 Use the P-message weighted filter
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FEDL7540-03
MSM7540/7560
¡ Semiconductor
AC Characteristics (Continued)
(VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C)
Condition
Parameter
Symbol
NIDLT
Freq.
Level
(Hz)
(dBm0)
—
AIN = SG
Idle Channel Noise
NIDLR
Absolute Signal
Amplitude
—
—
AVT
1020
PSRRT
Noise Freq.
Noise Level
Rejection Ratio
PSRRR : 0 to 50 kHz
: 50 mVPP
Delay Time
(*1)
(*1)
(*2)
Min.
Typ.
—
—
—
GSX2
0.488
VFRO
0.488
0
AVR
Power Supply Noise
Digital Output
Others
—
0.548
(*3)
0.548
(*3)
Max.
Unit
–69
(–72)
dBm0p
–72
(dBmp)
(–75)
0.615
Vrms
0.615
Vrms
30
—
—
dB
30
—
—
dB
tSDX
50
—
200
ns
tSDR
50
—
200
ns
50
—
200
ns
50
—
200
ns
50
—
200
ns
tXD1, tRD1
tXD2, tRD2
—
1 LSTTL + 100 pF,
Pull-up: 500 W
tXD3, tRD3
—
—
*1 Use the P-message weighted filter
*2 PCMRI input code "11010101"(MSM7540)
"11111111"(MSM7560)
*3 0.548 Vrms = 0 dBm0= –3 dBm
Note: All ADPCM coder and decoder characteristics comply with ITU-T Recommendation
G.721.
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FEDL7540-03
MSM7540/7560
¡ Semiconductor
TIMING DIAGRAM
Transmit Side PCM/ADPCM Data Interface
0
BCLKB
txs
XSYNC
1
2
tsx
3
4
5
6
7
8
txd1
txd2
10
11
12
13
14
txd3
MSB
PCMSO
9
tws
LSB
txd3
tsdx
MSB
PCMSO
(during linear)
BCLKA
0
txs
XSYNC
IS
1
2
txd1
txd2
tsx
LSB
3
4
5
7
8
9
10
7
8
9
10
9
10
txd3
MSB
tsdx
6
LSB
Receive Side PCM/ADPCM Data Interface
BCLKA
0
trs
1
2
tsr
3
4
5
6
11
12
13
14
tws
RSYNC
tds
IR
txd3
tdh
MSB
0
BCLKB
trs
1
LSB
2
tsr
3
4
5
6
7
8
RSYNC
trd1
PCMRO
txd3
trd2
MSB
LSB
trd3
tsdx
PCMRO
(during linear)
MSB
LSB
Note: Linear format
A code of an input/output level is determined by the 14-bit 2'compliment.
Refer to the table below for code format.
Input/Output level
MSB to LSB
+Full-scall
01111111111111
0
00000000000000
–Full-scall
10000000000000
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FEDL7540-03
MSM7540/7560
¡ Semiconductor
APPLICATION CIRCUIT
V DD
MSM7540/7560GS
1
V DD
2
Receive
PCM Output
Receive ADPCM Input
3
4
5
Transmit ADPCM Output
6
Transmit
PCM Output
7
8
9
10
11
Transmit Analog Input
12
13
14
RES
BCLKB
PCMRI
BCLKA
PCMRO
XSYNC
IR
RSYNC
IS
MCK
PCMSI
X2
PCMSO
X1
LPS
PDN
DG
V DD
AG
AOUT+
SG
AOUT–
AIN1
PWI
GSX1
VFRO
AIN2
GSX2
ADPCM Algorithm
Reset Input
28
Shift Clock Input for
PCM, ADPCM Data
(64 kHz to 2048 kHz)
27
26
8 kHz Sync Signal Input
25
24
23
22
21
10.368 MHz
Power Down Input
20
19
18
17
16
15
Receive Analog Output
(Push-Pull)
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FEDL7540-03
¡ Semiconductor
MSM7540/7560
PACKAGE DIMENSIONS
(Unit : mm)
SOP28-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.75 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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FEDL7540-03
¡ Semiconductor
MSM7540/7560
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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