E2U0025-29-82 ¡ Semiconductor MSM7575 ¡ Semiconductor This version: Aug. 1999 MSM7575 Previous version: Jan. 1998 Multi-Function PCM CODEC GENERAL DESCRIPTION The MSM7575, developed for advanced digital cordless telephone systems, is a single channel full duplex CODEC which performs mutual transcoding between the analog voice band signal and the 64 kbps PCM serial data. This device performs DTMF tone and several kinds of tone generation, transmit/receive data mute and gain control, side-tone pass and its gain control, and VOX function. Using advanced circuit technology, this device operates from a single 3 V power supply and provides low power consumption. FEATURES • Single 3 V Power Supply Operation VDD: 2.7 V to ␣ 3.6 V • Transmit/Receive Full-Duplex Single Channel Operation • Transmit/Receive Synchronous Mode Only • PCM Interface Data Format : A-law/µ-law/linear (2's complement) Selectable • Serial PCM Transmission Data Rate : 64 kbps to 2048 kbps • Low Power Consumption Operating Mode : 24 mW Typ. (VDD = 3.0 V) Power-Down Mode : 0.03 mW Typ. (VDD = 3.0 V) • Two Analog Input Amplifier Stages: Externally Gain Adjustable • Analog Output Stage Push-pull Drive (direct drive of 350 W␣ + 120 nF) • Master Clock Frequency : 9.600/19.200 MHz Selectable • Transmit/Receive Mute, Transmit/Receive Programmable Gain Control • Side Tone Path with Programmable Attenuation (8-step Level Adjustment) • Built-in DTMF Tone Generator • Built-in Various Ringing Tones Generator • Built-in Various Ring Back Tone Generator • Control by Serial MCU Interface • Built-in VOX Control Transmit side : Voice/Silence Signal Detect Receive side : Background Noise Generation • Built-in Op-amps and Analog Switches for Various Analog Interfaces. • Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK)(Product name : 7575GS-BK) 1/25 VOXO VOXI Prefilter BPF A/D P / S Compand PCMSO ATT GSX2 XSYNC ATT -1 AOUT+ ¡ Semiconductor + - Voice Signal Detect BLOCK DIAGRAM AIN2 V DD DG AG + - SG SGB AIN1+ AIN1GSX1 Tone GEN. VREF BCLK + - AOUT- Back ground Noise Gen. ATT PWI VFRO -1 SAO Postfilter + S / P Expand ATT PCMRI TOUT1 TOUT2 TOUT3 + REF1 AVIN + - REF2 To each circuit DIN DOUT DEN EXCK MCU Interface V DD + V DD V DD Clock/ Timing + SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 X2 X1 MCK PDN/ RESET IO14 IO13 IO12 IO11 IO10 IO9 IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 + - 2/25 MSM7575 AIN4+ AIN4GSX4 + -1 RINGC AIN3+ AIN3GSX3 LPF D/A RSYNC MSM7575 ¡ Semiconductor , VOXI VOXO DOUT DIN EXCK DEN PCMRI MCK X2 NC NC X1 PDN/RESET NC TOUT3 TOUT2 TOUT1 RINGC VDD REF2 REF1 AVIN NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN CONFIGURATION (TOP VIEW) 1 48 AOUT+ 2 47 AOUT- 3 46 PWI 4 45 VFRO 5 44 SAO 6 43 GSX2 7 42 AIN2 32 AIN3+ AG 33 31 16 SG IO4 30 AIN3- SGB 34 29 15 NC IO3 28 GSX3 NC 35 27 14 NC IO2 26 AIN4+ IO14 36 25 13 IO13 IO1 24 AIN4- IO12 37 23 12 IO11 DG 22 GSX4 21 38 IO9 11 IO10 BCLK 20 AIN1+ IO8 39 19 10 IO7 XSYNC 18 AIN1- IO6 GSX1 40 17 41 9 IO5 8 RSYNC PCMSO 64-Pin Plastic QFP NC : No connect pin 3/25 MSM7575 ¡ Semiconductor PIN AND FUNCTIONAL DESCRIPTIONS AIN1+, AIN1–, AIN2, GSX1, GSX2 Transmit analog input and the output for transmit gain adjustment. The pin AIN1– (AIN2) connects to the inverting input of the internal transmit amplifier, and the pin AIN1+ connects to the non-inverting input of the internal transmit amplifier. The pin GSX1 (GSX2) connects to output of the internal transmit amplifier. Gain adjustment should be referred to Fig. 1. VFRO, AOUT+, AOUT–, PWI, SAO, RINGC Used for the receive analog output and the output for receive gain adjustment. VFRO is an output of the receive filter. AOUT+ and AOUT– are differential analog signal outputs which can directly drive ZL = 350 W + 120 nF or the 1.2 kW load. Gain adjustment should be referred to Fig. 1. The ORed signal with the control register data CR4-B5 and the external pin RINGC determines the output pins (AOUT+ and AOUT- /SAO+ and SAO-) for the speech signal and an acoustic component of the sounder tone, DTMF tone, R tone, F tone, various kinds of tones at either the VFRO pin or the SAO pin. AIN1– Differential Analog Input C1 Vi R1 – V REF + AIN1+ C1 0.1 mF R2 R1 R2 10 mF + – GSX1 SG AIN2 C2 R3 to ENCODER + R4 GSX2 Transmit Gain: V GSX2 /Vi = (R2/R1) ¥ (R4/R3) Receive Gain: Vo/V VFRO = 2 ¥ (R6/R5) – VFRO from DECODER R5 PWI SELECT R6 AOUT– Z L = 120 nF + 350 W VO Differential Analog Output – + AOUT+ from MCU INT. TOUT1 –1 TOUT2 SAO Sounder Output Signal +1 RINGC + TOUT3 – from MCU INT. Figure 1 Analog Input/Output Interface 4/25 MSM7575 ¡ Semiconductor TOUT1, TOUT2, TOUT3 These are pins for outputs of the NOR gates whose inputs are the comparator output signal between the SAO output level and the SG level, and each register signal stored by the MCU interface. The each output is NOR-gated with the comparator output and the invented signal of CR1-B7 at TOUT3, the inverted signal of CR1-B6 at TOUT2, and the inverted signal of CR1-B5 at TOUT1. AVIN, REF1, REF2 These pins are for inputs of two comparators internal to the device. AVIN is connected to each non-inverting input of comparator1 and comparator2. REF1 is connected to an inverting input of comparator1 and REF2 is connected to an inverting input of comparator2. The output of each comparator is connected to the input of ENOR. The interval analog switch SW1 is ON/OFF controlled by the output which is the logical OR of the ENOR and the CR5-B7 signal. When CR5B7 is at "0", the SW1 is turned to OFF if AVIN is within the voltage range of REF1 and REF2 and the SW1 is turned to ON if AVIN is out of the voltage range of REF1 and REF2. AIN3+, AIN3-, GSX3, AIN4+, AIN4-, GSX4 These pins are for inputs and outputs of the internal op-amps. Refer to BLOCK DIAGRAM for the connection. IO1 to IO14 These pins are for inputs and outputs of the internal analog switch. Refer to BLOCK DIAGRAM and FUNCTIONAL DESCRIPTION for the connection and the control method. X1, X2 Crystal oscillator connection pins. X2 is for the clock output pin. When a conventional external clock is used, X1 should be connected to the ground, X2 should be left open, and the clock should be input to the MCK pin. For the use of a self-oscilation circut For the use of an external clock MSM7575 MSM7575 X1 X2 9.6 MHz or 19.2 MHz MCK X1 X2 MCK 9.6 MHz or 19.2 MHz Figure 2 Connection to a Crystal Oscillator or an External Clock 5/25 ¡ Semiconductor MSM7575 SG, SGB Analog signal ground output. The output voltage is about 1.4 V. The bypass capacitors (10 µF in parallel with 0.1 µF ceramic type) should be put between this pin and AG to get the specified noise characteristics. This output voltage is 0 V during power-down. AG Analog ground. DG Digital ground. This ground is separated from the analog signal ground(AG) in this device. The DG pin must be kept as close to the AG pin possible on the PCB. VDD +3 V power supply. PDN/RESET Power down and reset control input. “L” level makes the whole chip enter to power down state, and, at the same time, all of control register data are reset to the initial state. Set this pin to “H” level during normal operating mode. The power down state is controlled by a logical OR with CR0-B5 of the control register. When using the pin PDN/RESET for the power down and reset control, CR0-B5 should be set to digital “0”. MCK Master clock input. The frequency must be 9.6 MHz or 19.2 MHz. The applied clock frequency is selected by the control register data CR0-B6. The master clock signal is allowed to be asynchronous with BCLK, XSYNC, and RSYNC. PCMSO Transmit PCM data output. This PCM output signal is output from MSB in synchronization with the rising edge of BCLK or XSYNC. A pull-up resistor must be connected to this pin, because this output is configuared as an open drain. During power down, this output is at high impedance state. 6/25 MSM7575 ¡ Semiconductor PCMRI Receive PCM data input. This PCM input signal is shifted on the falling edge of BCLK and input from MSB. BCLK Shift clock input for the PCM data (PCMSO, PCMRI). The frequency is set in the range of 64 kHz to 2048 kHz. XSYNC 8 kHz synchronous signal input for Transmit PCM data. This signal should be synchronized with BCLK. XSYNC is used for indicating MSB of the transmit serial PCM. Be sure to input the XSYNC signal because it is also used as the input of the timing circuit and the clock source of the tone generator. RSYNC 8 kHz synchronous signal input for Receive PCM data. This signal should be synchronized with BCLK signal. RSYNC is used for indicating the MSB of the receive serial PCM. BCLK XSYNC PCMSO MSB LSB RSYNC PCMRI MSB LSB 8kHz (125ms) Figure 3 PCM Interface Basic Timing Diagram 7/25 MSM7575 ¡ Semiconductor VOXO Transmit VOX function signal output. VOX function is to recognize the presence or absence of the transmit voice signal by detecting the signal energy. “H” and “L” levels set to this pin correspond to the presence and the absence, respectively. This result appears also at the register data CR7-B7. The signal energy detect threshold is set by the control register data CR6-B6, B5. VOXI Signal input for receive VOX function. The “H” level at VOXI indicates the presence of voice signal, the decoder block processes normal receive signal, and the voice signal appears at analog output pins . The “L” level indicates the absence of voice signal, the background noise generated in this device is transferred to the analog output pins. The background noise amplitude is set by the control register CR6. Because this signal is ORed with the register data CR6-B3, the control register data CR6-B3 should be set to digital “0”. Voice Input GSX2 (Absence) VOXO (Presence) (Presence) TVXOFF Absence Detect (Hang-over time) TVXON Presence Detect (a) Transmit VOX Function Timing Diagram (Absence) VOXI (Presence) (Presence) Voice Output VFRO Normal Voice Signal Decoded Time period Background Noise (b) Receive VOX Function (CR6-B3: digital "0") Timing Diagram Note: VOXO, VOXI function become valid when setting CR6-B7 to digital “1”. Figure 4 VOX Function 8/25 MSM7575 ¡ Semiconductor DEN , EXCK, DIN, DOUT , , Serial control ports for MCU interface. Reading and writing data is performed by an external MCU through these pins. Total 8 registers with 8 bits are provided on the devices. DEN is the “Enable” control signal input, EXCK is the data shift clock input, DIN is the address and data input, and DOUT is the data output from which inverted data of the contents of the register is output. Fig.5 shows the input or output timing diagram. DEN EXCK W DIN A2 A1 A0 DOUT B7 B6 B5 B4 B3 B2 B1 B0 B2 B1 B0 High Impedance (a) Write Data Timing Diagram DEN EXCK DIN R DOUT A2 A1 A0 B7 High Impedance B6 B5 B4 B3 (b) Read Data Timing Diagram Figure 5 MCU Interface Input/Output Timing Register map is shown below. Table-1 Name Address Control and Detect Data A2 A1 A0 CR0 0 0 0 CR1 0 0 1 CR2 0 1 0 CR3 0 1 1 CR4 1 0 0 CR5 1 0 1 CR6 1 1 0 CR7 1 1 1 B7 B6 B5 B4 B3 B2 B1 — LNR B0 A/m MCK PDN PDN PDN SEL SEL ALL TX RX TOUT3 TOUT2 TOUT1 -CONT -CONT -CONT — — — — TX TX TX TX RX RX RX RX ON/OFF GAIN2 GAIN1 GAIN0 ON/OFF GAIN2 GAIN1 GAIN0 TONE TONE TONE TONE TONE ON/OFF GAIN3 GAIN2 GAIN1 GAIN0 TONE4 TONE3 TONE2 TONE1 TONE0 Side Tone Side Tone Side Tone PDN SAO/AOUT GAIN1 GAIN0 TONE SAO/ SEND VFRO SW8- SW9- SW5& SW4- SW3- SW2- SW1- CONT CONT CONT SW6-CONT CONT CONT CONT CONT VOX ON ON OUT LVL1 LVL0 R/W : Enable to read/write R/W RX PAD R/W GAIN2 DTMF/ OTHERS SEL SW7- ON/OFF LVL1 LVL0 VOX TX NOISE TX NOISE R/W RX NOISE RX NOISE RX NOISE OFF VOX TIME IN LEVEL SEL LVL1 LVL0 — — — — — R/W R/W R/W R/W R/W R R : Read only register. 9/25 MSM7575 ¡ Semiconductor ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Power Supply Voltage VDD Analog Input Voltage VAIN Digital Input Voltage Rating Unit — –0.3 to +5 V — – 0.3 to VDD + 0.3 V VDIN — –0.3 to VDD + 0.3 V Operating Temperature Top — –30 to +85 °C Storage Temperature TSTG — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS Symbol Condition Min. Typ. Max. Unit Power Supply Voltage Parameter VDD — +2.7 — +3.6 V Operating Temperature Range Ta — –25 +25 +70 °C 0.45 ¥ VDD — VDD V 0 — 0.16 ¥ VDD V MCK, XSYNC, RSYNC, PCMRI, Input High Voltage VIH RINGC, BCLK, VOXI, PDN/RESET, DEN, EXCK, DIN MCK, XSYNC, RSYNC, PCMRI, Input Low Voltage VIL RINGC, BCLK, VOXI, PDN/RESET, DEN, EXCK, DIN fMCK1 MCK (CR0–B6 = "0") –0.01% 9.600 +0.01% MHz fMCK2 MCK (CR0–B6 = "0") –0.01% 19.200 +0.01% MHz Bit Clock Freqency fBCK BCLK 64 — 2048 kHz Synchronous Signal Frequncy fSYNC XSYNC, RSYNC — 8.0 — kHz MCK, BCLK, EXCK 30 50 70 % — — 50 ns — — 50 ns Master Clock Frequency Clock Duty Ratio DC MCK, XSYNC, RSYNC, PCMRI, Digital Input Rise Time tIr RINGC, BCLK, VOXI, PDN/RESET, DEN, EXCK, DIN MCK, XSYNC, RSYNC, PCMRI, Digital Input Fall Time tIf RINGC, BCLK, VOXI, PDN/RESET, DEN, EXCK, DIN tXS BCLK to XSYNC 100 — — ns tSX XSYNC to BCLK 100 — — ns tRS BCLK to RSYNC 100 — — ns tSR RSYNC to BCLK 100 — — ns Synchronous Signal Width tWS XSYNC, RSYNC 1 BCLK — 100 ms PCM Set-up Time tDS — 100 — — ns — 100 — — ns 500 — — W — — 100 pF 10 + 0.1 — — mF Transmit Sync Signal Setting Time Receive Sync Signal Setting Time PCM Hold Time tDH RDL Digital Output Load Bypass Capacitors for SG CDL CSG PCMSO (Pull-up Resistor) TOUT1, TOUT2, TOUT3, PCMSO, VOXO, DOUT SG to AG 10/25 MSM7575 ¡ Semiconductor ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Symbol Condition Min. IDD1 Operating Mode, (VDD = 3.0 V) — IDD2 Power Down Mode, (VDD = 3.0 V) — Input High Voltage VIH — 0.45¥VDD Input Low Voltage VIL — 0.0 Power Supply Current Input Leakage Current Typ. Max. Unit 8 6 mA 0.01 0.1 mA — VDD V — 0.16¥VDD V IIH VI = VDD — — 2.0 mA IIL VI = 0 V — — 0.5 mA IOH = 0.4 mA 0.5 ¥ VDD — VDD V IOH = 1 mA 0.8 ¥ VDD — VDD V 1 LSTTL, Pull-up: 500 W 0.0 0.2 0.4 V PCMSO — — 10 mA — 5 — pF — 25 50 kW Output High Voltage VOH Output Low Voltage VOL Output Leakage Current IO Input Capacitance CIN Output Resistance ROSG — SG Transmit Analog Interface Characteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Min. Typ. Max. Unit Input Resistance Parameter Symbol RINX AIN1+ , AIN1– , AIN2 Condition 10 — — MW Output Load Resistance RLGX GSX1, GSX2 20 — — kW Output Load Capacitance CLGX GSX1, GSX2 — — 100 pF Output Amplitude VOGX GSX1, GSX2, RL = 20 kW — — 1.30 (*1) VPP Input Offset Voltage VOFGX Pre–OPAMPs –20 — 20 mV *1 –7.7 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 1.30 VPP (m-law Selected) 11/25 MSM7575 ¡ Semiconductor Receive Analog Interface Characteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Voltage Level Symbol RINPW Comparator Input Voltage Range PWI, AIN3+/–, AIN4+/–, REF1, REF2, AVIN Min. Typ. Max. Unit 10 — — MW RLVF VFRO, SAO 20 — — kW RLAO AOUT+, AOUT–, GSX3, GSX4 1.2 — — kW CLVF VFRO, SAO — — 100 pF CLAO AOUT+, AOUT–, GSX3, GSX4 — — 100 pF VOVF VFRO, SAO RL = 20 kW AOUT+, RL = 1.2 kW AOUT–, ZL = 350 kW GSX3, + 120 nF(See Fig.1) GSX4 — — 1.30 (*1) VPP — — 1.30 (*1) VPP — — 1.30 (*1) VPP –100 — 100 mV –20 — 20 mV 0.85 — VDD–0.75 — 100 — 400 W VOAO VOFVF Offset Voltage Condition VOFAO GDB VFRO, SAO AOUT+, AOUT– (Gain = 0 dB, Power amp only) GSX3, GSX4 AVIN, REF1, REF2 IO1-IO2, IO3-IO4, IO5-IO6, Analog Switch "ON" Resistance RSW IO7-IO8, IO9-IO10, IO10-IO11, IO12-VDD, IO13-VDD, IO14-VDD *1 –7.7 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 1.30 VPP (m-law Selected) 12/25 MSM7575 ¡ Semiconductor AC Chracteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Condition Parameter Symbol Freq. Level (Hz) (dBm0) LOSS T1 0 to 60 Others LOSS T2 300 to 3000 Min. Typ. Max. Unit 25 — — dB — 0.20 dB –0.15 Transmit Frequency LOSS T3 1020 Response LOSS T4 3300 –0.15 — 0.80 dB LOSS T5 3400 0 — 0.80 dB LOSS T6 3968.75 13 — — dB –0.15 — 0.20 dB Receive Frequency Responce LOSS R1 0 to 3000 LOSS R2 1020 LOSS R3 3300 LOSS R4 3400 LOSS R5 3968.75 SD T1 Transmit Signal to Distortion Ratio Receive Signal to Distortion Ratio Transmit Gain Tracking Receive Gain Tracking 0 –30 (*2) dB –0.15 — 0.80 dB 0 — 0.80 dB 13 — — dB 35 — — dB 35 — — dB 35 — — dB SD T4 –40 28 — — dB SD T5 –45 23 — — dB SD R1 3 35 — — dB 35 — — dB 35 — — dB SD R2 SD R3 0 1020 –30 (*2) SD R4 –40 28 — — dB SD R5 –45 23 — — dB GT T1 3 –0.2 — 0.2 dB GT T2 –10 GT T3 1020 dB –0.2 — 0.2 dB –50 –0.5 — 0.5 dB GT T5 –55 –1.2 — 1.2 dB GT R1 3 –0.2 — 0.2 dB — –10 GT R2 GT R3 –40 Reference GT T4 1020 –40 Reference — GT R4 –50 –0.5 — 0.5 dB GT R5 –55 –1.2 — 1.2 dB — AIN = SG NIDLR — — AVT 1020 AVR — (*2) (*2) (*3) –0.2 dB 0.2 NIDLT Amplitude — 0 1020 dB Reference Idle Channel Noise Absolute Signal — 3 SD T2 SD T3 0 Reference — — — — GSX2 0.285 VFRO 0.285 0 0.320 (*4) 0.320 (*4) dB –68 (–75.7) dBmOp –72 (dBmp) (–79.7) 0.359 Vrms 0.359 Vrms 13/25 MSM7575 ¡ Semiconductor AC Characteristics (Continued) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Condition Parameter Symbol Freq. Level (Hz) (dBm0) Power Supply Noise PSRRT Noise Freq. Noise Level Rejection Ratio PSRRR : 0 to 50 kHz : 50 mVPP Others Setting Time Typ. Max. Unit 30 — — dB 30 — — dB 0 — 0 — 0 — tXD3 0 — tM1 50 — — ns tM2 50 — — ns tM3 50 — — ns — tSDX Digital Input/Output Min. tXD1 — tXD2 1LSTTL + 100 pF See pull-up: 500 W Fig.4 200 *5(100) 200 *5(100) 200 *5(100) 200 *5(100) ns ns ns ns tM4 50 — — ns Serial Port Digital tM5 100 — — ns Input/Output Setting tM6 50 — — ns Time tM7 50 — — ns tM8 0 — 50 ns tM9 50 — — ns tM10 50 — — ns 0 — 50 ns — — 10 MHz — CLoad = 100 pF See Fig.7 tM11 Shift Clock Frequency FEXCK — — EXCK *2 Use the P-message weighted filter *3 PCMRI input code "11010101"(A-law) "11111111"(m-law) *4 0.320 Vrms = 0 dBm0 = –7.7 dBm *5 Value in ( ) is for CLoad = 10 pF Pull-up £ 20 kW Note: All ADPCM coder and decoder characteristics comply with ITU-T Recommendation G.721. 14/25 MSM7575 ¡ Semiconductor AC Characteristics (DTMF and Other Tones) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Frequency Difference Condition Symbol DFT1 DTMF Tones DFT2 Other Tones VTL Original (reference) Tone Signal Level *6 VTH VRL VRH Relative Level of DTMF Tones RDTMF Transmit Tones DTMF (Low) DTMF (High) and Other Tones DTMF (Low) Receive Tones DTMF (High) and Other Tones VTH/VTL, VRH/VRL Min. Typ. Max. Unit –7 — +7 Hz –7 — +7 Hz –18 –16 –14 dBm0 –16 –14 –12 dBm0 –4 –2 0 dBm0 –2 0 +2 dBm0 +1 +2 +3 dBm0 *6 Not contain the setting value of the programmable gain AC Characteristics (Programmable Gain Stages) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Gain Accuracy Symbol Condition Min. Typ. Max. Unit DG All gain stages, to programmed value –1 0 +1 dB AC Characteristics (VOX Function) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Symbol Condition Transmit VOX Detect Time tVXON OFF Æ ON VOXO, (Voice signal ON/OFF detect time) tVXOF ON Æ OFF Fig.4 Transmit VOX Detect Level Accuracy (Threshold Level) DVX To the setting of detect level by CR6-B6, B5. Min. Typ. Max. Unit — 5 — ms 150/310 160/320 170/330 ms 0 dB –2.5 +2.5 15/25 MSM7575 ¡ Semiconductor TIMING DIAGRAM Transmit Side PCM Data Interface BCLK 0 tXS XSYNC 1 tSX 2 tWS tXD1 tXD2 3 4 5 6 7 8 10 tXD3 LSB MSB PCMSO 9 tSDX Receive Side PCM Data Interface BCLK 0 tRS 1 tSR 2 RSYNC tDS PCMRI 3 4 5 6 7 8 9 10 tWS tDH MSB LSB Figure 6 PCM Data Interface 16/25 MSM7575 ¡ Semiconductor Serial Port Data Transfer for MCU Interface DEN tM1 DIN tM3 2 3 4 tM6 tM4 W/R tM10 tM5 tM2 1 EXCK A2 5 6 11 12 tM9 tM7 A1 A0 B7 B1 B0 tM11 tM8 DOUT B7 B1 B0 Figure 7 MCU Interface 17/25 MSM7575 ¡ Semiconductor FUNCTIONAL DESCRIPTION Control Registers (1) CR0 (Basic operating mode) B7 CR0 Initial Value B6 B5 B4 B3 B2 B1 A/m SEL MCK SEL PDN ALL PDN TX PDN RX — LNR 0 0 0 0 0 0 0 B0 PDN SAO/AOUT 0 Note) "Initial": Reset state by PDN/RESET B7 ...PCM Companding law select: 0/µ-law, 1/A-law B6 ...Master clock frequency select: 0/9.600 MHz, 1/19.200 MHz B5 ...Power down (whole system): 0/Power on, 1/Power down When using this data for power down control, pin PDN/RESET should be set at “H”level. The control registers are not reset by this signal. B4 ...Power down (Transmit only): 0/Power on, 1/Power down B3 ...Power down (Receive only including the op-amps of GSX3, GSX4 and comparator): 0/ Power on, 1/Power down B2 ...Not used B1 ...PCM interface linear code select: 0/Companding law selected by CR0-B7 1/14-bit Linear code (2's complement) in spite of the value of CR0-B7 B0 ...Power Down for Sounder output amps: (SAO), or Receiver output amp (AOUT, VFRO ): When this data is set to digital “1”, the circut which is not selected by CR4-B5 are at the power down state. When this data is set to digital "0", sounder amplifiers and receiver amplifiers are in the power-on state. 18/25 MSM7575 ¡ Semiconductor (2) CR1 B7 CR1 Initial Value B6 B5 TOUT3 TOUT2 TOUT1 –CONT –CONT –CONT 0 0 0 B4 B3 B2 B1 B0 — — — — RX PAD 0 0 0 0 0 B7 ... TOUT3 control bit : 0/TOUT3 = "0", 1/Enable TOUT3 B6 ... TOUT2 control bit : 0/TOUT2 = "0", 1/Enable TOUT2 B5 ... TOUT1 control bit : 0/TOUT1 = "0", 1/Enable TOUT1 B4 ... Not used B3 ... Not used B2 ... Not used B1 ... Not used B0 ... Receive side PAD : 1/inserted,12 dB loss 0/no PAD 19/25 MSM7575 ¡ Semiconductor (3)CR2 (PCM CODEC operational mode setting and transmit/receive gain adjustment) B7 CR2 B6 B5 B4 B3 B2 B1 B0 TX ON/OFF TX GAIN2 TX GAIN1 TX GAIN0 RX ON/OFF RX GAIN2 RX GAIN1 RX GAIN0 Initial Value 0 0 1 1 0 0 1 1 B7 ... PCM Coder disable : 0/Enable, 1/Disable (transmit PCM idle pattern) B6, B5, B4 ... Transmit gain adjustment, refer to Table-2. B3 ... PCM Decoder disable : 0/Enable, 1/Disable (receive PCM idle pattern) B2, B1, B0 ... Receive gain setting, refer to Table-2. Table-2 Transmit/Receive Gain Setting table B6 B5 B4 Transmit Gain B2 B1 B0 Receive Gain 0 0 0 –6 dB 0 0 0 –6 dB 0 0 1 –4 dB 0 0 1 –4 dB 0 1 0 –2 dB 0 1 0 –2 dB 0 1 1 0 dB 0 1 1 0 dB 1 0 0 +2 dB 1 0 0 +2 dB 1 0 1 +4 dB 1 0 1 +4 dB 1 1 0 +6 dB 1 1 0 +6 dB 1 1 1 +8 dB 1 1 1 +8 dB This programmable gain table should be assigned, not only for transmit/receive voice signal, but also for the transmitted DTMF and other tones. The transmission of these tone signals are enabled, by the CR4-B6 data described later, The original (reference) signal amplitude of these tones are analogically defined as follows. DTMF low-group-tones .................................... –16 dBm0/Tone DTMF high-group-tones and others............... –14 dBm0/Tone For example, when selecting +8 dB (B6, B5, B4) = (1,1,1) as a transmit gain, each tone signal amplitude with analogical expression on the pin PCMSO becomes as follows . DTMF low-group tones .................................... –8 dBm0 DTMF high-group tones and other tones ...... –6 dBm0 Gain setting of side tone (path to receive side from transmit side) and receive side tone is performed by register CR3. 20/25 MSM7575 ¡ Semiconductor (4) CR3 (Side tone and other tone generator gain setting) B7 B6 B5 Side. Tone Side. Tone Side. Tone CR3 Initial Value B4 B3 B2 B1 B0 TONE TONE TONE TONE TONE GAIN2 GAIN1 GAIN0 ON/OFF GAIN3 GAIN2 GAIN1 GAIN0 0 0 0 0 0 0 0 0 B7, B6, B5 ... Side tone path gain setting, refer to Table-3. B4 ... Tone generator enable : 0/Disable, 1/Enable B3, B2, B1, B0 ... Tone generator gain adjustment for receive side, refer to Table-4 Table-3 Side Tone Gain Setting Table B7 B6 B5 0 0 0 OFF 0 0 1 –21 dB 0 1 0 –19 dB 0 1 1 –17 dB 1 0 0 –15 dB 1 0 1 –13 dB 1 1 0 –11 dB 1 1 1 –9 dB Side Tone Path Gain Table-4 Receive Tone Generator Gain Setting Table B3 B2 B1 B0 Tone Generator Gain B3 B2 B1 B0 Tone Generator Gain 0 0 0 0 –36 dB 1 0 0 0 –20 dB 0 0 0 1 –34 dB 1 0 0 1 –18 dB 0 0 1 0 –32 dB 1 0 1 0 –16 dB 0 0 1 1 –30 dB 1 0 1 1 –14 dB 0 1 0 0 –28 dB 1 1 0 0 –12 dB 0 1 0 1 –26 dB 1 1 0 1 –10 dB 0 1 1 0 –24 dB 1 1 1 0 –8 dB 0 1 1 1 –22 dB 1 1 1 1 –6 dB The tone generator gain setting table for receive side, shown by Table-4, depends upon the following reference level. DTMF low-group tones ................................ –2 dBm0 DTMF high-group tones and others ............ 0 dBm0 For example, when selecting –6 dB (B3, B2, B1, B0) = (1, 1, 1, 1) as a tone generator gain, each DTMF tone signal amplitude on SAO or VFRO is as follows. DTMF low-group tone .................................. –8 dBm0 DTMF high-group tone or other tones ....... –6 dBm0 21/25 MSM7575 ¡ Semiconductor (5) CR4 (Tone genereator operating mode and frequency setting) B7 CR4 B6 B5 B4 B3 B2 B1 B0 TONE4 TONE3 TONE2 TONE1 TONE0 0 0 0 0 0 DTMF/OTHERS TONE SAO/ SEL SEND VFRO 0 0 0 Initial Value B7 ... DTMF or Other tones select : 0/Others, 1/DTMF B6 ... Tone transmit enable (Transmit side) : 0/Voice signal (transmit), 1/Tone transmit B5 ... Tone output pin select (Receive side) : 0/VFRO, 1/SAO B4, B3, B2, B1, B0 ... Tone frequency setting, referred to Table-5-1, -2. (a) B7 = 1 (DTMF tone) Table-5-1 B4 B3 B2 B1 B0 Frequency B4 B3 B2 B1 B0 Frequency * 0 0 0 0 697 Hz + 1209 Hz * 1 0 0 0 852 Hz + 1209 Hz * 0 0 0 1 697 Hz + 1336 Hz * 1 0 0 1 852 Hz + 1336 Hz * 0 0 1 0 697 Hz + 1477 Hz * 1 0 1 0 852 Hz + 1477 Hz * 0 0 1 1 697 Hz + 1633 Hz * 1 0 1 1 852 Hz + 1633 Hz * 0 1 0 0 770 Hz + 1209 Hz * 1 1 0 0 941 Hz + 1209 Hz * 0 1 0 1 770 Hz + 1336 Hz * 1 1 0 1 941 Hz + 1336 Hz * 0 1 1 0 770 Hz + 1477 Hz * 1 1 1 0 941 Hz + 1477 Hz * 0 1 1 1 770 Hz + 1633 Hz * 1 1 1 1 941 Hz + 1633 Hz *Unrelated (b) B7 = 0 (Other tones) Table-5-2 Tone Generator Frequency Setting B4 B3 B2 B1 B0 Frequency B4 B3 B2 B1 B0 Frequency 0 0 0 0 0 2 k/2.48 kHz, 8 Hz wamble 1 0 0 0 0 2000 Hz 0 0 0 0 1 2 k/2.2 kHz, 8 Hz wamble 1 0 0 0 1 2042 Hz 0 0 0 1 0 2 k/2.48 kHz, 4 Hz wamble 1 0 0 1 0 2514 Hz 0 0 0 1 1 2 k/2.2 kHz, 4 Hz wamble 1 0 0 1 1 500 Hz 0 0 1 0 0 1 k/1.333 kHz, 8 Hz wamble 1 0 1 0 0 667 Hz 0 0 1 0 1 2.73 k/2.5 kHz, 8 Hz wamble 1 0 1 0 1 1333 Hz 0 0 1 1 0 1.8 k/2 kHz, 8 Hz wamble 1 0 1 1 0 2100 Hz 0 0 1 1 1 400 Hz,16 Hz wamble 1 0 1 1 1 — 0 1 0 0 0 400 Hz,20 Hz wamble 1 1 0 0 0 — 0 1 0 0 1 400 Hz 1 1 0 0 1 — 0 1 0 1 0 350 Hz + 440 Hz Mix 1 1 0 1 0 — 0 1 0 1 1 1.5kHz 1 1 0 1 1 — 0 1 1 0 0 1.8kHz 1 1 1 0 0 — 0 1 1 0 1 800 Hz 1 1 1 0 1 — 0 1 1 1 0 1000 Hz 1 1 1 1 0 — 0 1 1 1 1 1300 Hz 1 1 1 1 1 — 22/25 MSM7575 ¡ Semiconductor Wamble Tone Wave t Repeatative waveform Tf1 Tf2 4Hz wamble... Tf1 = Tf2 = 125 ms 8Hz wamble... Tf1 = Tf2 = 62.5 ms 16Hz wamble...Tf1 = Tf2 = 31.25 ms 20Hz wamble...Tf1 = Tf2 = 25 ms (6) CR5 (Analog switch control) CR5 Initial Value B7 B6 B5 B4 B3 B2 B1 B0 SW7_ SW8_ SW9_ SW5&SW6_ SW4_ SW3_ SW2_ SW1_ CONT CONT CONT CONT CONT CONT CONT CONT 0 0 0 0 0 0 0 0 B7 ... Control Analog switch SW7 between IO12 and VDD : 0/SW7 OFF, 1/SW7 ON B6 ... Control Analog switch SW8 between IO13 and VDD : 0/SW8 OFF, 1/SW8 ON B5 ... Control Analog switch SW9 between IO14 and VDD : 0/SW9 OFF, 1/SW9 ON B4 ... Control Analog switch SW5 between IO9 and IO10, and Analog switch SW6 between IO10 and IO11 : 0/SW5 OFF, SW6 ON, 1/SW5 ON, SW6 OFF B3 ... Control Analog switch SW4 between IO7 and IO8 : 0/SW4 OFF, 1/SW4 ON B2 ... Control Analog switch SW3 between IO5 and IO6 : 0/SW3 OFF, 1/SW3 ON B1 ... Control Analog switch SW2 between IO3 and IO4 : 0/SW2 OFF, 1/SW2 ON B0 ... Control Analog switch SW1 between IO1 and IO2 : 0/SW1 OFF, 1/SW1 ON 23/25 MSM7575 ¡ Semiconductor (7) CR6 (VOX function control) CR6 Initial Value B7 B6 B5 B4 B3 VOX ON ON OFF VOX IN ON/OFF LVL1 LVL0 TIME 0 0 0 0 0 B2 B1 B0 RX NOISE RX NOISE RX NOISE LEVEL SEL LVL1 LVL0 0 0 0 B7 ... VOX function enable : 0/Disable, 1/Enable B6, B5 ... Transmit signal energy detect (Transmit VOX) threshold (0, 0): –30 dBm0 (0, 1): –35 dBm0 (1, 0): –40 dBm0 (1, 1): –45 dBm0 B4 ... Hang-over time (Fig. 2, TVXOFF) : 0/160 ms, 1/320 ms B3 ... Receive VOX function setting : 0/Background noise transmit, 1/Voice signal detect When using this data for control, the pin VOXI should be set at a “L” level. B2 ... Background noise amplitude setting : 0/Automatic, 1/Programmable by B1 and B0 Automatic : The noise is set at the voice signal amplitude at the time when B3 (or VOXI) changes from “1” to digital “0”. B1, B0 ... (0, 0): No noise (0, 1): –55 dBm0 (1, 0): –45 dBm0 (1, 1): –35 dBm0 (8) CR7 (Detect register, read only) B7 CR7 Initial VOX B6 B5 TX NOISE TX NOISE OUT LVL1 LVL0 0 0 0 B4 B3 B2 B1 B0 — — — — — * * * * * * For IC test B7 ... Transmit VOX function result : 0/Absence, 1/Presence B6, B5 ... Transmit voiceless level (indicator) : (0, 0) : below –60 dBm0 Note) These outputs are valid only when VOX (0, 1) : –50 to –60 dBm0 function is enabled by CR6-B7. (1, 0) : –40 to –50 dBm0 (1, 1) : over –40 dBm0 B4 ... Not used B3 ... Not used B2 ... Not used B1 ... Not used B0 ... Not used 24/25 MSM7575 ¡ Semiconductor PACKAGE DIMENSIONS (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/25 E2Y0002-29-62 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. 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The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan