E2U0041-28-81 ¡ Semiconductor MSM7717-01/02/03 ¡ Semiconductor This version: Aug. 1998 MSM7717-01/02/03 Previous version: Nov. 1996 Single Rail CODEC GENERAL DESCRIPTION The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400 Hz with filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the device is optimized for ISDN terminals and telephone terminals in digital wireless systems. The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B. The analog output, which can drive a 1.2 kW load, can directly drive a handset receiver differentially. FEATURES • Single power supply: 2.7 V to 3.8 V • Low power consumption Operating mode: 20 mW Typ. VDD = 3 V Power-down mode: 0.03 mW Typ. VDD = 3 V • Conforms to ITU-T Companding law MSM7717-01: m/A-law pin selectable MSM7717-02: m-law MSM7717-03: A-law • Built-in PLL eliminates a master clock • Serial data rate: 64/128/256/512/1024 kHz 96/192/384/768/1536/1544/2048/200 kHz • Adjustable transmit gain • Adjustable receive gain • Built-in reference voltage supply • Package options: 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM7717-01GS-K) (Product name: MSM7717-02GS-K) (Product name: MSM7717-03GS-K) 20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K) (Product name: MSM7717-02MS-K) (Product name: MSM7717-03MS-K) 1/19 ¡ Semiconductor MSM7717-01/02/03 BLOCK DIAGRAM AIN– AIN+ – + RC LPF 8th BPF PCMOUT AD CONV. TCONT AUTO ZERO PLL GSX XSYNC BCLK SGC SG SG GEN VR GEN VFRO – + 5th LPF SG RTIM RSYNC (ALAW) DA CONV. RCONT PCMIN PWI AOUT– AOUT+ – + – + SG SG PWD PWD Logic PDN VDD AG DG 2/19 ¡ Semiconductor MSM7717-01/02/03 PIN CONFIGURATION (TOP VIEW) SG 1 24 SGC SG 1 20 SGC AOUT+ 2 23 AIN+ AOUT+ 2 19 AIN+ AOUT– 3 22 AIN– AOUT– 3 18 AIN– NC 4 21 GSX PWI 4 17 GSX PWI 5 20 NC VFRO 5 16 NC VFRO 6 19 NC VDD 6 15 (ALAW)* 18 (ALAW)* DG 7 14 AG NC 7 VDD 8 17 NC PDN 8 DG 9 16 AG RSYNC 9 12 XSYNC 15 BCLK PCMIN 10 11 PCMOUT PDN 10 RSYNC 11 14 XSYNC PCMIN 12 13 PCMOUT 13 BCLK NC : No connect pin 20-Pin Plastic SSOP NC : No connect pin 24-Pin Plastic SOP * The ALAW pin is only supported by the MSM7717-01GS-K/MSM7717-01MS-K. 3/19 ¡ Semiconductor MSM7717-01/02/03 PIN AND FUNCTIONAL DESCRIPTIONS AIN+, AIN–, GSX Transmit analog input and transmit level adjustment. AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is connected to the output of the op-amp. The level adjustment should be performed in any method shown below. When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power-saving and power-down modes, the GSX output is at AG voltage. 1) Inverting input type C1 R2 Analog input R1 GSX AIN– AIN+ SG – + R1 : variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F) Gain = R2/R1 < 10 2) Noninverting input type C2 AIN+ AIN– GSX Analog input R5 R4 R3 SG + – R3 > 20 kW R4 > 20 kW R5 > 50 kW C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) (F) Gain = 1 + R4 / R3 £ 10 AG Analog signal ground. VFRO Receive filter output. The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMIN and can drive a load of 20 kW or more. For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO and PWI. During power-saving mode this output is in a high impedance state, and during power-down mode, the VFRO output is at an SG level. When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency Characteristics Adjustment Circuit. 4/19 ¡ Semiconductor MSM7717-01/02/03 PWI, AOUT+, AOUT– PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted with respect to the output of AOUT–. Since these outputs provide differential drive of an impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being activated during the power-saving mode, the amplifiers can output other external signals from AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during the power-down mode. VI External Signal Input Receive filter VFRO PWI SG – + R6 R6 > 20 kW R7 Gain = VO/VI = R7/R6 £ 1 AOUT– Analog output VO ZL SG – + ZL > 1.2 kW AOUT+ Analog inverted output VDD Power supply for 2.7 V to 3.8 V. (Typically 3.0 V) PCMIN PCM data input. A serial PCM data input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLK signal. The data rate of PCM is equal to the frequency of the BCLK signal. PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. BCLK Shift clock signal input for the PCMIN and PCMOUT signal. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive driver amplifiers are in the operating mode and the other circuits are in the non-operating mode. 5/19 ¡ Semiconductor MSM7717-01/02/03 RSYNC Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are not guaranteed. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, if the frequency characteristic of an applied system is not specified exactly, this device operates in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. 6/19 ¡ Semiconductor MSM7717-01/02/03 DG Ground for the digital signal circuits. This ground is separate from the analog signal ground AG. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground AG. PDN Power down control signal. A logic "0" level drives both transmit and receive circuits to a power down state. PCMOUT PCM signal output. Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from MSD in a sequential order. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power saving or power down mode. A pull-up resistor must be connected to this pin because its output is configured as an open drain. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7717-03 (A-law) outputs the character signal, inverting the even bits. PCMIN/PCMOUT Input/Output Level +Full scale MSM7717-02 (m-law) MSM7717-03 (A-law) MSD MSD 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 +0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 –0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 –Full scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 7/19 ¡ Semiconductor MSM7717-01/02/03 SG Signal ground voltage output. The output voltage is 1/2 of the power supply voltage. The output drive current capability is ±200 mA. This pin provides the SG level for CODEC peripherals. This output voltage level is undefined during power-saving or power-down mode. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Only the MSM7717-01GS-K/7717-01MS-K has this pin. The CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will has this pin operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is internally pulled down. 8/19 ¡ Semiconductor MSM7717-01/02/03 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD Analog Input Voltage VAIN — –0.3 to +7 V — –0.3 to VDD + 0.3 V Digital Input Voltage Storage Temperature VDIN — –0.3 to VDD + 0.3 V TSTG — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supply Voltage VDD Operating Temperature Ta Condition Voltage must be fixed — Min. Typ. Max. Unit 2.7 3.0 3.8 V –30 +25 +85 °C 1.4 VPP Analog Input Voltage VAIN Connect AIN– and GSX — — High Level Input Voltage VIH XSYNC, RSYNC, BCLK, 0.45¥VDD — VDD V Low Level Input Voltage VIL PCMIN, PDN, ALAW 0 — 0.16¥VDD V Clock Frequency FC BCLK Sync Pulse Frequency FS XSYNC, RSYNC Clock Duty Ratio DC BCLK 40 50 60 % Digital Input Rise Time tlr XSYNC, RSYNC, BCLK, — — 50 ns 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, kHz 1536, 1544, 200 Digital Input Fall Time Transmit Sync Pulse Setting Time 6.0 8.0 10 kHz tlf PCMIN, PDN, ALAW — — 50 ns tXS BCLKÆXSYNC, See Fig. 1 100 — — ns tSX XSYNCÆBCLK, See Fig. 1 100 — — ns tRS BCLKÆRSYNC, See Fig. 1 100 — — ns tSR RSYNCÆBCLK, See Fig. 1 100 — — ns High Level Sync Pulse Width tWSH XSYNC, RSYNC, See Fig. 1 1 BCLK — — ms Low Level Sync Pulse Width tWSL XSYNC, RSYNC, See Fig. 1 1 BCLK — — ms PCMIN Setup Time tDS See Timing Diagram 100 — — ns PCMIN Hold Time tDH See Timing Diagram 100 — — ns RDL Pull-up resistor Receive Sync Pulse Setting Time Digital Output Load CDL Analog Input Allowable DC Offset Voff Allowable Jitter Width — 0.5 — — kW — — — 100 pF Transmit gain stage, Gain = 1 –100 — +100 mV Transmit gain stage, Gain = 10 –10 — +10 mV XSYNC, RSYNC, BCLK — — 1000 ns 9/19 ¡ Semiconductor MSM7717-01/02/03 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Condition Min. Typ. Max. Operating mode VDD = 3.8 V — 10 14 No signal VDD = 3.0 V — 6.5 10.0 — 2.0 8.0 mA — 0.005 0.05 mA 0.45¥VDD — VDD V 0.0 — 0.16¥VDD V Power-saving mode, PDN = 1, BCLK or XSYNC Æ OFF Power-down mode, PDN = 0, BCLK OFF XSYNC, RSYNC, BCLK, Unit mA High Level Input Voltage VIH Low Level Input Voltage VIL High Level Input Leakage Current IIH — — — 2.0 mA Low Level Input Leakage Current IIL — — — 0.5 mA Digital Output Low Voltage VOL PCMIN, PDN, ALAW XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW Pull-up resistor > 500 W 0.0 0.2 0.4 V Digital Output Leakage Current IO — — — 10 mA Input Capacitance CIN — — 5 — pF 10/19 ¡ Semiconductor MSM7717-01/02/03 Transmit Analog Interface Characteristics (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Min. Typ. Max. Unit Input Resistance Symbol RINX AIN+, AIN– 10 — — MW Output Load Resistance RLGX GSX with respect to SG 20 — — kW Output Load Capacitance CLGX — — 30 pF –0.7 — +0.7 V –20 — +20 mV Output Amplitude VOGX Offset Voltage VOSGX Condition Gain = 1 Receive Analog Interface Characteristics (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Input Resistance Symbol RLVF Output Load Resistance Output Load Capacitance Condition Min. Typ. Max. Unit 10 — — MW 20 — — kW 0.6 — — kW VFRO — — 30 pF AOUT+, AOUT– — — 50 pF –1.0 — +1.0 V –1.0 — +1.0 V –100 — +100 mV –100 — +100 mV RINPW PWI RLAO CLVF CLAO VOVF Output Amplitude VOAO VFRO with respect to SG AOUT+, AOUT– (each) with respect to SG VFRO, RL = 20 kW with respect to SG AOUT+, AOUT–, RL = 0.6 kW with respect to SG VOSVF VFRO with respect to SG Offset Voltage VOSAO AOUT+, AOUT–, Gain = 1 with respect to SG 11/19 ¡ Semiconductor MSM7717-01/02/03 AC Characteristics Parameter (FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Symbol Loss T1 Transmit Frequency Response Receive Frequency Response Freq. (Hz) 60 Loss T2 300 Loss T3 1020 Loss T4 2020 Loss T5 3000 20 26 — +0.07 +0.2 –0.15 Reference 0 –0.15 –0.01 +0.2 –0.15 +0.15 +0.2 0 0.4 0.8 300 –0.15 –0.03 +0.2 Loss R2 1020 Loss R3 2020 Loss R4 Loss R5 –0.02 +0.2 3000 –0.15 +0.15 +0.25 3400 0 0.56 0.8 3 35 43 — SD T2 0 35 41 — SD T3 –30 35 38 — 28 30 — SD T4 1020 0 –40 *1 SD T5 –45 23 25 — SD R1 3 36 43 — SD R2 0 36 41 — 36 40 — 30 33.5 SD R4 –30 1020 –40 –45 GT T1 3 GT T2 –10 GT T3 1020 *1 *2 *2 29 32 25 30 24 27 –0.3 +0.01 — dB dB dB +0.3 Reference –40 –0.3 0 +0.3 –50 –0.6 –0.03 +0.6 GT T5 –55 –1.2 +0.15 +1.2 GT R1 3 –0.3 –0.06 +0.3 dB Reference –10 –40 –0.3 –0.02 +0.3 GT R4 –50 –0.6 –0.02 +0.6 GT R5 –55 –1.2 –0.27 +1.2 1020 dB — GT T4 GT R3 Unit Reference –0.15 GT R2 Receive Gain Tracking Max. 3400 SD R5 Transmit Gain Tracking Typ. Loss T6 SD R3 Receive Signal to Distortion Ratio Min. Loss R1 SD T1 Transmit Signal to Distortion Ratio Level Condition (dBm0) dB *1 Psophometric filter is used. *2 Upper columns are specified for the m-law, lower for the A-law. 12/19 ¡ Semiconductor MSM7717-01/02/03 AC Characteristics (Continued) Parameter Idle Channel Noise (FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Symbol Freq. (Hz) Nidle T — Nidle R — Level Condition (dBm0) AIN = SG — *1 — (Deviation of Temperature and Power) Typ. –72.5 –70.5 Max. –68 AV Tt *4 1020 0 VDD = 2.7 V to 3.8 V Ta = –30 AV Rt to 85°C *4 Unit dBm0p — –76.5 –74 0.338 0.35 0.362 0.483 0.5 0.518 –0.2 — +0.2 dB –0.2 — +0.2 dB — — 0.6 ms — 0.19 0.75 — 0.11 0.35 — 0.02 0.125 Vrms Ta = 25°C AV R Absolute Level — *2 *1 *3 VDD = 3.0 V AV T Absolute Level (Initial Difference) Min. A to A Absolute Delay Td 1020 tGD T1 500 0 BCLK = 64 kHz Transmit Group Delay Receive Group Delay Crosstalk Attenuation *1 *2 *3 *4 *5 tGD T2 600 tGD T3 1000 tGD T4 2600 — 0.05 0.125 tGD T5 2800 — 0.07 0.75 tGD R1 500 — 0.00 0.75 tGD R2 600 tGD R3 1000 tGD R4 tGD R5 CR T CR R 0 *5 — 0.00 0.35 — 0.00 0.125 2600 — 0.09 0.125 2800 — 0.12 0.75 TRANS Æ RECV 75 80 — RECV Æ TRANS 70 76 — 1020 0 0 *5 ms ms dB Psophometric filter is used. Upper column is specified for the m-law, lower for the A-law. Input "0" code to PCMIN. AVR is defined at VFRO output. With respect to minimum value of the group delay distortion 13/19 ¡ Semiconductor MSM7717-01/02/03 AC Characteristics (Continued) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio (FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Freq. Level Condition (Hz) (dBm0) 0 to 4.6 kHz to DIS 0 4000 Hz 72 kHz Symbol S IMD 300 to 3400 fa = 470 fd = 320 PSR T 0 to PSR R 50 kHz 0 –4 50 mVPP 4.6 kHz to 100 kHz 2fa – fd *6 tSD Digital Output Delay Time tXD1 tXD2 CL = 100 pF + 1 LSTTL tXD3 Min. Typ. Max. Unit 30 32 — dB — –37.5 –35 dBm0 — –52 –35 dBm0 — 30 — dB 20 — 200 20 — 200 20 — 200 20 — 200 ns *6 Measured under idle channel noise. 14/19 , , ¡ Semiconductor MSM7717-01/02/03 TIMING DIAGRAM PCM Data Input/Output Timing Transmit Timing BCLK 1 tXS XSYNC 3 4 5 6 7 8 9 10 tSX tWSL tWSH tXD1 PCMOUT 2 tSD tXD2 MSD D2 D3 D4 D5 D6 D7 tXD3 D8 When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1. When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD. Receive Timing BCLK 1 tRS RSYNC PCMIN 2 3 4 5 6 7 8 9 10 tSR tWSL tWSH MSD tDS D2 D3 tDH D4 D5 D6 D7 D8 Figure 1 Basic Timing 15/19 ¡ Semiconductor MSM7717-01/02/03 APPLICATION CIRCUIT +3 V MSM7717-01 51 kW AIN– Analog input 0.1 mF PCMOUT PCM signal output XSYNC 8 kHz SYNC signal input RSYNC BCLK PCMIN PCM shift clock input PCM data GSX AIN+ SG Analog inverted output* AOUT+ Analog output* AOUT– Control of companding law 1: A-law 0: m-law ALAW PWI VFRO 51 kW SGC * Power down control input 1: Normal operation 0: Power down 0.1 mF 10 mF 0V +3 V PDN AG 1 mF + VDD 0 to 10 W DG These output signals have amplitudes above and below the offset level of VDD/2. FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT MSM7717-XX Microphone amp M R1 AIN– C1 C2 R2 Transmit frequency characteristic Adjustment determined by C1, C2, R1 and R2 GSX AIN+ SG AOUT+ R5 C4 R4 AOUT– Receive frequency characteristic Adjustment determined by C3, C4, R3 and R4 PWI VFRO R3 C3 16/19 ¡ Semiconductor MSM7717-01/02/03 NOTES ON USE • To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 17/19 ¡ Semiconductor MSM7717-01/02/03 PACKAGE DIMENSIONS (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/19 ¡ Semiconductor MSM7717-01/02/03 (Unit : mm) SSOP20-P-250-0.95-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.18 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/19