E2O0011-27-X2 This version: Jan. 1998 MSM80C88A-10RS/GS/JS Previous version: Aug. 1996 ¡ Semiconductor MSM80C88A-10RS/GS/JS ¡ Semiconductor 8-Bit CMOS MICROPROCESSOR GENERAL DESCRIPTION The MSM80C88A-10 is internal 16-bit CPUs with 8-bit interface implemented in Silicon Gate CMOS technology. It is designed with the same processing speed as the NMOS8088-1, but with considerably less power consumption. The processor has attributes of both 8 and 16-bit microprocessor. It is directly compatible with MSM80C86A-10 software and MSM80C85AH hardware and peripherals. FEATURES • 8-Bit Data Bus interface • 16-Bit Internal Architecture • 1 Mbyte Direct Addressable Memory Space • Software Compatible with MSM80C86A-10 • Internal 14-Word by 16-bit Register Set • 24-Operand Addressing Modes • Bit, Byte, Word and String Operations • 8 and 16-bit Signed and Unsigned Arithmetic Operation • From DC to 10 MHz Clock Rate (Note) • Low Power Dissipation (10mA/MHz) • Bus Hold Circuitry Eliminated Pull-Up Resistors • 40-pin Plastic DIP (DIP 40-P-600-2.54): (Product name: MSM80C88A-10RS) • 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM80C88A-10JS) • 56-pin Plastic QFP (QFP56-P-1519-1.00-K): (Product name: MSM80C88A-10GS-K) (Note) 10 MHz Spec. is not compatible with Intel 8088-1 spec. 1/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS FUNCTIONAL BLOCK DIAGRAM Exeuction Unit Bus Interface Unit Register File Relocation Register File Data Pointer and Index Registers (8 Words) Segment Registers and Instruction Pointer (5 Words) 16Bit ALU Flags 12 Bus Interface Unit SS0 A19. / S6 .. A8 8 AD7 - AD0 4 INTA, RD, WR, IO/M 3 DT/R, DEN, ALE 4-byte Instruction Queue TEST INTR NMI RQ/GT0, 1 LOCK 2 Control & Timing HOLD HLDA 2 QS0, QS1 3 S2, S1, S0 3 CLK RESET READY MN/MX GND VCC 2/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS PIN CONFIGURATION (TOP VIEW) 40 pin Plastic DIP GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0(HIGH) MN/MX RD HOLD(RQ/GT0) HLDA(RQ/GT1) WR(LOCK) IO/M(S2) DT/R(S1) DEN(S0) ALE(QS0) INTA(QS1) TEST READY RESET 56 55 54 53 52 51 50 49 48 47 46 45 44 43 A11 A12 A13 A14 NC GND NC VCC VCC NC A15 A16/S3 A17/S4 A18/S5 56 pin Plastic QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 A18/S5 41 A17/S4 43 A15 42 A16/S3 1 NC 44 VCC 2 GND pin Plastic QFJ 3 A14 4 A13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 5 A12 NC A19/S6 SS0(HIGH) MN/MX RD HOLD(RQ/GT0) NC NC NC HLDA(RQ/GT1) WR(LOCK) IO/M(S2) DT/R(S1) 44 DEN(S0) 6 A11 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A10 7 39 NC A9 8 38 A19/S6 A8 9 37 HIGH FIX(SS0) (ALE)QS0 28 (INTA)QS1 27 29 DEN(S0) TEST 26 30 DT/R(S1) AD0 17 READY 25 31 M/IO(S2) AD1 16 RESET 24 32 WR(LOCK) AD2 15 NC 23 33 HLDA(RQ/GT1) AD3 14 GND 22 34 HOLD(RQ/GT0) AD4 13 CLK 21 35 RD AD5 12 INTR 20 36 MN/MX AD6 11 NC 18 AD7 10 NM1 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NMI INTR CLK NC NC GND VCC NC NC RESET READY TEST INTA(QS1) ALE(QS0) NC A10 A9 A8 AD7 AD6 NC NC AD5 AD4 AD3 AD2 AD1 AD0 3/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS ABSOLUTE MAXIMUM RATING Rating Parameter Symbol Power Supply Voltage VCC –0.5 to +7 V Input Voltage VIN –0.5 to VCC +0.5 V VOUT TSTG –0.5 to VCC +0.5 V –65 to +150 °C — W Ta = 25°C Output Voltage Storage Temperature Power Dissipation PD MSM80C88A-10RS MSM80C88A-10GS MSM80C88A-10JS 1.0 Units 0.7 Condition With respect to GND OPERATING RANGE Parameter Symbol Range Unit Power Supply Voltage VCC 4.75 to 5.25 V Operating Temperature Top 0 to +70 °C RECOMMENDED OPERATING CONDITIONS Symbol Min. Typ. Max. Unit Power Supply Voltage Parameter VCC 4.75 5.0 5.25 V Operating Temperature Top 0 +25 +70 °C "L" Input Voltage VIL –0.5 — +0.8 V "H" Input Voltage VIL *1 VCC -0.8 — VCC +0.5 V *2 2.0 — VCC +0.5 V *1 Only CLK *2 Except CLK 4/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS DC CHARACTERISTICS (VCC = 4.5 to 5.5 V, Ta = –40°C to +85°C) Parameter "L" Output Voltage Symbol VOL Min. Typ. Max. Unit — — 0.4 V — — V 3.0 Conditions IOL = 2.5 mA IOH = –2.5 mA "H" Output Voltage VOH Input Leak Current ILI –1.0 — +1.0 mA 0 £ VIN £ VCC Output Leak Current ILO –10 — +10 mA VO = VCC or GND Input Leakage Current (Bus Hold Low) IBHL 50 — 400 mA Input Leakage Current (Bus Hold High IBHH –50 — –400 mA VIN = 0.8 V *3 VIN = 3.0 V *4 Bus Hold Low Overdrive IBHLO — — 600 mA Bus Hold High Overdrive IBHHO — — –600 mA Operating Power Supply Current ICCS — — 10 mA/MHz Standby Power Current ICC — — 500 mA VIN = VCC or GND Outputs Unloaded CLK = GND or VCC VCC –0.4 IOH = –100 mA *5 *6 VIL = GND VIH = VCC CIN — — 10 pF *7 Output Capacitance COUT — — 15 pF *7 I/O Capacitance CI/O — — 20 pF *7 Input Capacitance *3 Test conditions are to lower VIN to GND and then raise VIN to 0.8 V on pins 2-16, and 35-39. *4 Test conditions are to raise VIN to VCC and then lower VIN to 3.0 V on pins 2-16, 26-32, and 3439. *5 An external driver must source at least IBHLO to switch this node from LOW to HIGH. *6 An external driver must sink at least IBHHO to switch this node from HIGH to LOW. *7 Test Conditions: a) Freq = 1 MHz. b) Ummeasured Pins at GND. c) VIN at 5.0 V or GND. 5/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS AC CHARACTERISTICS Minimum Mode System Timing Requirements Parameter 5 MHz Spec. 8 MHz Spec. 10 MHz Spec. VCC = 4.5 V to 5.5 V VCC = 4.75 V to 5.25 V VCC = 4.75 V to 5.25 V Unit Symbol Ta = -40 to +85°C Ta = 0 to +70°C Ta = 0 to +70°C TCLCL TCLCH TCHCL Min. 200 118 69 Max. DC — — Min. 125 68 44 Max. DC — — Min. 100 46 44 Max. DC — — ns ns ns TCH1CH2 — 10 — 10 — 10 ns TCL2CL1 — 10 — 10 — 10 ns TDVCL TCLDX 30 10 — — 20 10 — — 20 10 — — ns ns TR1VCL 35 — 35 — 35 — ns TCLR1X 0 — 0 — 0 — ns TRYHCH 118 — 68 — 46 — ns READY Hold Time into MSM80C88A-10 TCHRYX 30 — 20 — 20 — ns READY inactive to CLK (See Note 3) TRYLCL –8 — –8 — –8 — ns THVCH 35 — 20 — 20 — ns TINVCH 30 — 15 — 15 — ns TILIH — 15 — 15 — 15 ns TIHIL — 15 — 15 — 15 ns CLK Cycle Period CLK Low Time CLK High Time CLK Rise Time (From 1.0 V to 3.5 V) CLK Fall Time (From 3.5 V to 1.0 V) Data in Setup Time Data in Hold Time RDY Setup Time into MSM 82C84A-2 (See Notes 1, 2) RDY Hold Time into MSM 82C84A-2 (See Notes 1, 2) READY Setup Time into MSM80C88A-10 HOLD Setup Time INTR, NMI, TEST Setup Time (See Note 2) Input Rise Time (Except CLK) (From 0.8 V to 2.0 V) Input Fall Time (Except CLK) (From 2.0 V to 0.8 V) 6/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Timing Responses Parameter 5 MHz Spec. 8 MHz Spec. 10 MHz Spec. VCC = 4.5 V to 5.5 V VCC = 4.75 V to 5.25 V VCC = 4.75 V to 5.25 V Unit Symbol Ta = –40 to +85°C Ta = 0 to +70°C Ta = 0 to +70°C Max. 110 — Min. 10 10 Max. 60 — Min. 10 10 — ns tCLAZ tLHLL tCLLH tCHLL tLLAX tCLDV tCHDX tWHDX tCVCTV tCHCTV tCVCTX tAZRL tCLRL Min. 10 10 tCLAX tCLCH-20 — — tCLCH-10 10 10 tCLCH-30 10 10 10 0 10 80 — 80 85 — 110 — — 110 110 110 — 165 tCLAX tCLCH-10 — — tCLCH-10 — — tCLCH-30 10 10 10 0 10 50 — 50 55 — 60 — — 70 60 70 — 100 tCLAX tCLCH-10 — — tCLCH-10 10 10 tCLCH-25 10 10 10 0 10 50 — 40 45 — 60 — — 55 50 55 — 70 ns ns ns ns ns ns ns ns ns ns ns ns ns RD Inactive Delay RD Inactive to Next Address Active tCLRH tRHAV 10 tCLCH-45 150 10 ns ns 10 80 — 100 — — — 15 15 60 — tCLHAV tRLRH tWLWH tAVAL tOLOH tOHOL tCLCH-40 10 2tCLCL-50 2tCLCL-40 tCLCH-40 — — 10 tCLCL-35 HLDA Valid Delay RD Width WR Width Address Valid to ALE Low Ouput Rise Time (From 0.8 V to 2.0 V) Output Fall Time (From 2.0 V to 0.8 V) — 160 — — — 15 15 10 60 — — — 15 15 ns ns ns ns ns ns Address Valid Delay tCLAV Address Hold Time tCLAX Address Float Delay ALE Width ALE Active Delay ALE Inactive Delay Address Hold Time to ALE Inactive Data Valid Delay Data Hold Time Data Hold Time after WR Control Active Delay 1 Control Active Delay 2 Control Inactive Delay Address Float to RD Active RD Active Delay 2tCLCL-75 2tCLCL-60 tCLCH-60 — — 2tCLCL-40 2tCLCL-35 tCLCH-35 — — Max. 60 ns Notes: 1. Signals at MSM82C84A-2 shown for reference only. 2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 3. Applies only to T2 state. (8 ns into T3) 7/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Maximum Mode System (Using MSM82C88-2 Bus Controller) Timing Requirements Parameter 5 MHz Spec. 8 MHz Spec. 10 MHz Spec. VCC = 4.5 V to 5.5 V VCC = 4.75 V to 5.25 V VCC = 4.75 V to 5.25 V Unit Symbol Ta = –40 to +85°C Ta = 0 to +70°C Ta = 0 to +70°C tCLCL tCLCH tCHCL Min. 200 118 69 Max. DC — — Min. 125 68 44 Max. DC — — Min. 100 46 44 Max. DC — — ns ns ns tCH1CH2 — 10 — 10 — 10 ns tCL2CL1 — 10 — 10 — 10 ns tDVCL tCLDX 30 10 — — 20 10 — — 20 10 — — ns ns tR1VCL 35 — 35 — 35 — ns tCLR1X 0 — 0 — 0 — ns tRYHCH 118 — 68 — 46 — ns READY Hold Time into MSM80C88A-10 tCHRYX 30 — 20 — 20 — ns READY inactive to CLK (See Note 3) Setup Time for Recognition (NMI, INTR, TEST) (See Note 2) tRYLCL –8 — –8 — –8 — ns tINVCH 30 — 15 — 15 — ns RQ/GT Setup Time tGVCH 30 — 15 — 15 — ns RQ Hold Time into MSM80C88A-10 tCHGX 40 — 30 — 20 — ns tILIH — 15 — 15 — 15 ns tIHIL — 15 — 15 — 15 ns CLK Cycle Period CLK Low Time CLK High Time CLK Rise Time (From 1.0 V to 3.5 V) CLK Fall Time (From 3.5 V to 1.0 V) Data in Setup Time Data in Hold Time RDY Setup Time into MSM 82C84A-2 (See Notes 1, 2) RDY Hold Time into MSM82C84A-2 (See Notes 1, 2) READY Setup Time into MSM80C88A-10 Input Rise Time (Except CLK) (From 0.8 V to 2.0 V) Input Fall Time (Except CLK) (From 2.0 V to 0.8 V) 8/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Timing Responses Parameter 5 MHz Spec. 8 MHz Spec. 10 MHz Spec. VCC = 4.5 V to 5.5 V VCC = 4.75 V to 5.25 V VCC = 4.75 V to 5.25 V Unit Symbol Ta = –40 to +85°C Ta = 0 to +70°C Ta = 0 to +70°C Command Active Delay (See Note 1) tCLML Min. 5 Max. 45 Min. 5 Max. 35 Min. 5 Max. 35 ns Command Inactive Delay (See Note 1) tCLMH 5 45 5 45 5 45 ns tRYHSH — 110 — 65 — 45 ns tCHSV tCLSH tCLAV tCLAX tCLAZ tSVLH 10 10 10 10 10 10 10 10 tSVMCH tCLLH tCLMCH tCHLL tCLDV tCHDX tCVNV tCVNX tAZRL tCLRL tCLRH tRHAV tCLAX — — — — 4 10 10 5 45 60 60 — 50 25 30 25 25 25 60 — 45 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 0 10 10 tCLCL-45 45 — 165 150 — tCLAX — — — — 4 10 10 5 5 0 10 10 tCLCL-40 60 70 60 — 50 25 30 25 25 25 60 — 45 45 — 100 80 — 10 10 10 10 tCLAX — — — — 4 10 10 5 110 130 110 — 80 35 35 35 35 35 110 — 45 5 0 10 10 tCLCL-35 45 — 70 60 — ns ns ns ns ns tCHDTL — 50 — 50 — 50 ns tCHDTH — 35 — 30 — 30 ns tCLGL tCLGH tRLRH tOLOH tOHOL 0 0 85 85 — 15 15 0 0 50 50 — 15 15 0 0 45 45 — 15 15 ns ns ns ns ns READY Active to Status Passive (See Note 4) Status Active Delay Status Inactive Delay Address Valid Delay Address Hold Time Address Float Delay Status Valid to ALE High (See Note 1) Status Valid to MCE High (See Note 1) CLK Low to ALE Valid (See Note 1) CLK Low to MCE High (See Note 1) ALE Inactive Delay (See Note 1) Data Valid Delay Data Hold Time Control Active Delay (See Note 1) Control Inactive Delay (See Note 1) Address Float to RD Active RD Active Delay RD Inactive Delay RD Inactive to Next Address Active Direction Control Active Delay (See Note 1) Direction Control Inactive Delay (See Note 1) GT Active Delay (See Note 5) GT Inactive Delay RD Width Output Rise Time (From 0.8 V to 2.0 V) Output Fall Time (From 2.0 V to 0.8 V) 2tCLCL-75 — — 2tCLCL-50 — — 2tCLCL-40 — — Notes: 1. Signals at MSM82C84A-2 or MSM82C88-2 are shown for reference only. 2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 3. Applies only to T2 state (8 ns into T3) 4. Applies only to T3 and wait states. 5. CL = 40 pF (RQ/GT0, RQ/GT1) 9/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS A.C. Testing Input, Output Waveform 2.4 Test Points 1.5 A.C. Testing Load Circuit Device Under Test 1.5 0.45 A.C. Testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0" timing measurements are 1.5 V for both a logic "1" and "0". CL = 100 pF CL includes jig capacitance. TIMING CHART Minimum Mode T1 T2 tCLCL VIH CLK (MSM82C84A-2 Output) VIL IO/M, SS0 A15 - A8 A19/S6 - A16/S3 ALE tCHCTV tCLCH A15 - A8 (Float during INTA) tCLDV tCLAV tCLAX tCLLH A19 - A16 tLHLL tCHDX S6 - S3 tLLAX tAVAL tR1VCL VIH VIL Read Cycle (NOTE 1) (WR, INTA = VOH) RD DT/R DEN tCLR1X tCHRYX tCLAV AD7 - AD0 T4 tCL2CL1 tCH1CH2 tRYLCL READY (MSM80C88A-10 Input) Tw tCHCL tCHLL RDY (MSM82C84A-2 Input) See NOTE 4 T3 tRYHCH tAVAL tLLAX tCLAZ tCLAX AD7 - AD0 tAZRL tCHCTV tCLRL tCVCTV Float tDVCL Data In tCLRH tRLRH tCLDX Float tRHAV tCHCTV tCVCTX 10/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Minimum Mode (continued) T2 tCLCL CLK (MSM82C84A-2 Output) VIH VIL T3 tCH1CH2 tCHCL tCHCTV T4 TW tCL2CL1 tCLCH IO/M, SS0 tCLAV tCLAX A19/S6 - A16/S3 tCHDX A19 - A16 tCLLH tLHLL tCLAV tAVAL tCHLL tCLDV tCLAX AD7 - AD0 ALE AD7 - AD0 Write Cycle (NOTE 1) RD, INTA DT/R = VOH tCLDV S6 - S3 tLLAX tCHDX Data Out tAVAL tCVCTV tWHDX DEN tCVCTV tWLWH WR tCVCTX tDVCL tCLAZ AD7 - AD0 Float Pointer tCHCTV INTA Cycle (NOTES 1 & 3) (RD, WR = VOH BHE = VOL) tCVCTX tLLAX tCLDX Float tCHCTV DT/R tCVCTV INTA tCVCTV tCVCTX DEN Software Halt RD, WR, INTA = VOH DT/R = Indeterminate Invalid Address Software Halt TCLAV tCLAV Notes: 1. All signals switch between VOH and VOL unless otherwise specified. 2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted. 3. Two INTA cycles run back-to-back. The MSM80C88A-10 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control signals shown for second INTA cycle. 4. Signals at MSM82C84A-2 shown for reference only. 5. All timing measurements are made at 1.5 V unless otherwise noted. 11/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Maximum Mode T1 T2 tCH1CH2 tCLCL VIH CLK (MSM82C84A-2 Output) VIL tCLAV QS0, QS1 tCHCL ,, tCLSH (See NOTE 8) A15 - A8 A15 - A8 tCLDV tCLAV tCLAX A19/S6 - A16/S3 See NOTE 5 ALE (MSM82C88-2 Output) T4 tCLCH tCHSV S2, S1, S0 (Except Halt) T3 tCL2CL1 Tw tSVLH tCLLH RDY (MSM82C84A-2 Input) A19 - A16 tCHLL tR1VCL VIH VIL tRYLCL READY (MSM80C88A-10 Input) tCHDX S6 - S3 tCLR1X tCHRYX tRYHSH tCLAX Read Cycle tCLAV AD7 - AD0 RD DT/R MSM82C88-2 Outputs See NOTES 5, 6 MRDC or IORC tCLAZ AD7 - AD0 tAZRL tCLRL tCHDTL tRYHCH Float tDVCL Data In tCLRH tRLRH tCLDX Float tRHAV tCHDTH tCLMH tCLML tCVNV DEN tCVNX 12/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Maximum Mode (continued) T1 CLK (MSM82C84A-2 Outputs) VIH VIL tCHSV S2, S1, S0 (Except Halt) tCLAV Write Cycle T2 AD7 - AD0 T4 Tw tCLSH (See NOTE 8) tCLDV tCLAX tCHDX Data AD7 - AD0 tCVNV tCVNX DEN MSM82C88-2 Outputs See NOTES 5, 6 T3 tCLML ANMC or AIOWC tCLMH tCLML MWTC or IOWC INTA Cycle A15 - A8 (See NOTES 3 & 4) AD7 - AD0 Reserved for Cascade ADDR tCLAZ tSVMCH tCVNX MCE/ PDEN t CLMCH MSM82C88-2 Outputs See NOTES 5, 6 Float tCHDTL DT/R Float tDVCL Pointer tCLMH Float tCLDX Float tCHDTH tCLML INTA tCLMH tCVNV DEN Software Halt (DEN VOL; RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA VOH) tCVNX Invalid Address AD7 - AD0, A15 - A8 tCLAV S2, S1, S0 Notes: 1. All signals switch between VOH and VOL unless otherwise specified. 2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted. 3. Cascade address is valid between first and second INTA cycle. 4. Two INTA cycles run back-to-back. The MSM80C86A-10 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control for pointer address is shown for second INTA cycle. 5. Signal at MSM82C84A-2 or MSM82C88-2 shown for reference only. The issuance of the MSM82C88-2 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high MSM82C88-2 CEN. 7. All timing measurements are made at 1.5 V unless otherwise noted. 8. Status inactive in state just prior to T4. 13/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Asynchronous Signal Recognition CLK tINVCH (See NOTE 1) NMI INTR Signal TEST NOTE: 1 Setup requirements for asynchronous signals only to guarantee recognition at next CLK Bus Lock Signal Timing (Maximum Mode Only) Reset Timing ≥ 50msec Any CLK Cycle Any CLK Cycle VCC CLK tCLAV CLK tCLAV tCLDX tDVCL Reset LOCK ≥ 4 CLK Cycles Request/Grant Sequence Timing (Maximum Mode Only) Any CLK Cycle > 0 CLK Cycle CLK tCLGH ≥ tCLCL Pulse 1 Coprocessor RQ RQ/GT AD7 - AD0, A15 - A8 A19/S6 - A16/S3 S2, S1, S0, RD, COCK tGVCH tCHGX ≥ tCLCL tCLGH tCLGL Pulse 2 MSM80C88 GT Pulse 3 Coprocessor Release tCLAZ Previous Grant MSM80C88A-10 Coprocessor MSM80C88A-10 (See NOTE 1) NOTE: 1 The coprocessor may not drive the busses outside the region shown without risking contention Hold/Hold Acknowledge Timing (Minimum Mode Only) £ 1 CLK Cycle 1 or 2 Cycles CLK tHVCH tHVCH HOLD tCLHAV tCLHAV HLDA AD7 - AD0, A15 - A8 A19/S6 - A16/S3 RD IO/M DT/R, WR, DEN tCLAZ MSM80C88A-10 Coprocessor MSM80C88A-10 14/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS PIN DESCRIPTION AD0 - AD7 ADDRESS DATA BUS: Input/Output These lines are the multiplexed address and data bus. These are the address bus at T1 cycle and the data bus at T2, T3, TW and T4 cycle. T2, T3, TW and T4 cycle. These lines are high impedance during interrupt acknowledge and hold acknowledge. A8 - A15 ADDRESS BUS: Output These lines are the address bus bits 8 thru 15 at all cycles. These lines do not have to be latched by an ALE signal. These lines are high impedance during interrupt acknowledge and hold acknowledge. A16/S3, A17/S4, A18/S5, A19/S6 ADDRES/STATUS : Output These are the four most significant address as at the T1, cycle. Accessing I/O port address, these are low at T1 Cycle. These lines are Status lines at the T2, T3, TW and T4 Cycles. S5 indicates interrupt enable Flag. S3 and S4 are encoded as shown below. S3 S4 0 0 1 0 Stack 0 1 Code or None 1 1 Data Characteristics Alternate Data These lines are high impedance during hold acknowledge. RD READ: Output This line indicates that CPU is in a memory or I/O read cycle. This line is the read strobe signal when CPU reads data from a memory or I/O device. This line is active low. This line is high impedance during hold acknowledge. READY READY:Input This line indicates to the CPU that the addressed memory or I/O device is ready to read or write. This line is active high. If the setup and hold time are out of specification, an illegal operation will occur. INTR INTERRUPT REQUEST: Input This line is the level triggered interrupt request signal which is sampled during the last clock cycle of instruction and string manipulations. It can be internally masked by software. This signal is active high and internally synchronized. 15/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS TEST TEST: Input This line is examined by a "WAIT" instruction. When TEST is high, the CPU enters an idle cycle. When TEST is low, the CPU exits in an idle cycle. NMI NON MASKABLE INTERRUPT: Input This line causes a type 2 interrupt. NMI is not maskable. This signal is internally synchronized and needs 2-clock cycle pulse width. RESET RESET:Input This signal causes the CPU to initialize immediately. This signal is active high and must be at least four clock cycles. CLK CLOCK: Input This signal provides the basic timing for the internal circuit. MN/MX MINIMUM/MAXIMUM: Input This signal selects the CPU’s operating mode. When VCC is connected, the CPU operates in minimum mode. When GND is connected, the CPU operates in maximum mode. VCC VCC: +5V supplied. GND GROUND The following pin function descriptions are for maximum mode only. Other pin functions are already described. SO, S1, S2 STATUS: Output These lines indicate bus status and they are used by the MSM82C88-2 Bus Controller to generate all memory and I/O access control signals. These lines are high impedance during hold acknowledge. These status lines are encoded as shown below. S2 S1 S0 Characteristics 0 (LOW) 0 0 Interrupt acknowledge 0 0 1 Read I/O Port 0 1 0 Write I/O Port 0 1 1 Halt 1 (HIGH) 0 0 Code Access 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive 16/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS RQ/GT0 RQ/GT1 REQUEST/GRANT:Input/Output These lines are used for Bus Request from other devices and Bus GRANT to other devices. These lines are bidirectional and active low. LOCK LOCK:Output This line is active low. When this line is low, other devices cannot gain control of the bus. This line is high impedance hold acknowledge. QS0/QS1 QUEUE STATUS: Output These are Queue Status Lines that indicate internal instruction queue status. QS1 QS0 0 (LOW) 0 Characteristics No operation 0 1 First Byte of Op Code from Queue 1 (HIGH) 0 Empty the Queue 1 1 Subsequent Byte from Queue The following pin function descriptions are minimum mode only. Other pin functions are already described. IO/M STATUS: Output This line selects memory address space or I/O address space. When this line is low, the CPU selects memory address space and when it is high, the CPU selects I/O address space. This line is high impedance during hold acknowledge. WR WRITE: Output This line indicates that the CPU is in a memory or I/O write cycle. This line is a write strobe signal when the CPU writes data to memory or an I/O device. This line is active low. This line is high impedance during hold acknowledge. INTA INTERRUPT ACKNOWLEDGE: Output This line is a read strobe signal for the interrupt acknowledge cycle. This line is active low. 17/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS ALE ADDRESS LATCH ENABLE: Output This line is used for latching an address into the MSM82C12 address latch it is a positive pulse and the trailing edge is used to strobe the address. This line is never floated. DT/R DATA TRANSMIT/RECEIVE: Output This line is used to control the direction of the bus transceiver. When this line is high, the CPU transmits data, and when it is low. the CPU receives data. This line is high impedance during hold acknowledge. DEN DATA ENABLE: Output This line is used to control the output enable of the bus transceiver. This line is active low. This line is high impedance during hold acknowledge. HOLD HOLD REQUEST: Input This line is used for a Bus Request from an other device. This line is active high. HLDA HOLD ACKNOWLEDGE: Output This line is used for a Bus Grant to an other device. This line is active high. SS0 STATUS: Output This line is logically equivalent to S0 in the maximum mode. 18/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS STATIC OPERATION The MSM80C88A-10 circuitry is of static design. Internal registers, counters and latches are static and require no refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The MSM80C88A-10 can operate from DC to the appropriate upper frequency limit. The processor clock may be stopped in either state (high/low) and held there indefinitely. This type of operation is especially useful for system debug or power critical applications. The MSM80C88A-10 can be signal stepped using only the CPU clock. This state can be maintained as long as is necessary. Signal step clock operation allows simple interface circuitry to provide critical information for bringing up your system. Static design also allows very low frequency operation (down to DC). In a power critical situation, this can provide extremely low power operation since 80C88A power dissipation is directly related to operating frequency. As the system frequency is reduced, so is the operating power until, ultimately, at a DC input frequency, the MSM80C88A-10 power requirement is the standby current (500 mA maximum). FUNCTIONAL DESCRIPTION General Operation The internal function of the MSM80C88A-10 consists of a Bus interface Unit (BIU) and an Execution Unit (EU). These units operate mutually but perform as separate processors. The BIU performs instruction fetch and queueing, operand fetch, DATA read and write address relocation and basic bus control. By performing instruction prefetch while waiting for decoding and execution of instruction, the CPU’s performance is increased. Up to 4-bytes for instruction stream can be queued. EU receives pre-fetched instructions from the BIU queue, decodes and executes instructions and provides an un-relocated operand address to the BIU. Memory Organization The MSM80C88A-10 has a 20-bit address to memory. Each address has 8-bit data width. Memory is organized 00000H to FFFFFH and is logically divided into four segments: code, data, extra data and stack segment. Each segment contains up to 64 Kbytes and locates on a 16-byte boundary. (Fig. 3a) All memory references are made relative to a segment register according to a select rule. Memory location FFFF0H is the start address after reset, and 00000H through 003FFH are reserved as an interrupt pointer. There are 256 types of interrupt pointer: Each interrupt type has a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset address. 19/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Memory Organization Reserved Memory Locations FFFFFH 64KB FFFFFH Reset Bootstrap Program Jump Code Segment XXXXOH +Offset Segment Register File CS SS DS ES Stack Segment Data Segment Interrupt Pointer for Type 255 Interrupt Pointer for Type 1 Interrupt Pointer for Type 0 FFFFOH 3FFH 3FCH 7H 4H 3H 0H Extra Data Segment OOOOOH Memory Reference Need Segment Register Used Segment Selection Rule Instructions CODE (CS) Automatic with all instruction prefetch. Stack STACK (CS) All stack pushes and pops. Memory references relative to BP base register except data references. Local Data DATA (DS) Data references when relative to stack, destination of string operation, or explicitly overridden. External (Global Data) EXTRA (ES) Destination of string operations: Explicitly selected using a segment override. Minimum and Maximum Modes The MSM80C88A-10 has two system modes: minimum and maximum. When using the maximum mode, it is easy to organize a multiple-CPU system with the MSM82C88-2 Bus Controller which generates the bus control signal. When using the minimum mode, it is easy to organize a simple system by generating the bus control signal itself. MN/MX is the mode select pin. Definition of 24-31, 34 pin changes depends on the MN/MX pin. 20/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Bus Operation The MSM80C88A-10 has a time multiplexed address and data bus. If a non-multiplexed bus is desired for the system, it is only needed to add the address latch. A CPU bus cycle consists of at least four clock cycles: T1, T2, T3 and T4. (Fig. 4) The address output occurs during T1, and data transfer occurs during T3 and T4. T2 is used for changing the direction of the bus during read operation. When the device which is accessed by the CPU is not ready to data transfer and send to the CPU “NOT READY” is indicated TW cycles are inserted between T3 and T4. When a bus cycle is not needed, T1 cycles are inserted between the bus cycles for internal execution. At the T1 cycle an ALE signal is output from the CPU or the MSM82C88-2 depending in MN/MX, at the trailing edge of an ALE, a valid address may be latched. Status bits S0, S1 and S2 are used, in maximum mode, by the bus controller to recognize the type of bus operation according to the following table. S2 S1 S0 0 (LOW) 0 0 Interrupt acknowledge 0 0 1 Read I/O 0 1 0 Write I/O 0 1 1 Halt 1 (HIGH) 0 0 Instruciton Fetch 1 0 1 Read Data from Memory 1 1 0 Write Data to Memory 1 1 1 Passive (no bus cycle) Characteristics Status bits S3 through S6 are multiplexed with A16-A19, and therefore they are valid during T2 through T4. S3 and S4 indicate which segment register was selected on the bus cycle, according to the following table. S4 S3 0 (LOW) 0 Characteristics Alternate Data (Extra Segment) 0 1 Stack 1 (HIGH) 0 Code or None 1 1 Data S5 indicates interrupt enable Flag. I/O Addressing The MSM80C88A-10 has a 64 Kbyte I/O. When the CPU accesses an I/O device, addresses A0A15 are in same format as a memory access, and A16-A19 are low. I/O ports addresses are same as four memory. 21/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Basic System Timing (4 + N*WAIT) = TCY T1 T2 T3 TWAIT (4 + N*WAIT) = TCY T4 T1 T2 T3 TTWAIT T4 CLK Goes inactive in the state just prior to T4 ALE S2, S1, S0 A19 - A16 ADDR/ Status A19 - A16 S6 - S3 S6 - S3 A15 - A8 ADDR A15 - A8 Bus reserved for Data In A7 - A0 D7 - D0 Valid A7 - A0 ADDR/ Data Data Out (D7 - D0) RD, INTA Ready Ready Ready Wait Wait DT/R DEN Memory Access Time WR 22/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS EXTERNAL INTERFACE Reset CPU initialization is executed by the RESET pin. The MSM80C88A-10’s RESET High signal is required for greater than 4 clock cycles. The rising edge of RESET terminates the present operation immediately. The falling edge of RESET triggers an internal reset sequence for approximately 10 clock cycles. After internal reset sequence is finished, normal operation begins from absolute location FFFF0H. Interrupt Operations The interrupt operation is classified as software or hardware, and hardware interrupt is classified as non-markable or maskable. An interrupt causes a new program location which is defined by the interrupt pointer table, according to the interrupt type. Absolute location 00000H through 003FFH is reserved for the interrupt pointer table. The interrupt pointer table consists of 256-elements. Each element is 4 bytes in size and corresponds to an 8-bit type number which is sent from an interrupt request device during the interrupt acknowledge cycle. Non-maskable Interrupt (NMI) The MSM80C88A-10 has a non-maskable interrupt (NMI) which is of higher priority than a maskable interrupt request (INTR). An NMI request pulse width needs minimum of 2 clock cycles. The NMI will be serviced at the end of the current instruction or between string manipulations. Maskable Interrupt (INTR) The MSM80C88A-10 provides another interrupt request (INTR) which can be masked by software. INTR is level triggerd, so it must be held until interrupt request is acknowledged. The INTR will be serviced at the end of the current instruction or between string manipulations. Interrupt Acknowledge During the interrupt acknowledge sequence, further interrupts are disabled. The interrupt enable bit is reset by any interrupt, after which the Flag register is automatically pushed onto the stack. During an acknowledge sequence, the CPU emits the lock signal from T2 of first bus cycle to T2 of second bus cycle. At the second bus cycle, a byte is fetched from the external device as a vector which identifies the type of interrupt. This vector is multiplied by four and used as an interrupt pointer address (INTR only). The interrupt Return (IRET) instruction includes a Flag pop operation which returns the original interrupt enable bit when it restores the Flag. 23/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS HALT When a Halt instruction is executed, the CPU enters Halt state. An interrupt request or RESET will force the MSM80C88A-10 out of the Halt state. System Timing – Minimum Mode A bus cycle begins at T1 with an ALE signal. The trailing edge of ALE is used to latch the address. From T1 to T4 the IO/M signal indicates a memory or I/O operation. From T2 to T4, the address data bus changes the address but to the data bus. The read (RD), write (WR), and interrupt acknowledge (INTA) signals caused the addressed device to enable the data bus. These signals become active at the beginning of T2 and inactive at the beginning of T4. System Timing – Maximum Mode In maximum mode, the MSM82C88-2 Bus Controller is added to system. The CPU sends status information to the Bus Controller. Bus timing signals are generated by the Bus Controller. Bus timing is almost the same as in minimum mode. Interrupt Acknowledge Sequence T1 T2 T3 T4 TI T1 T2 T3 T4 ALE LOCK INTA AD0 - AD7 Float Type Vector 24/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS BUS HOLD CIRCUITRY To avoid high current conditions caused by floating inputs to CMOS devices, and to eliminate the need for pull-up/down resistors, “bus-hold” circuitry has been used on MSM80C88A-10 pins 2-16, 26-32, and 34-39 (Figures 6a, 6b). These circuits will maintain the last valid logic state if no driving source is present (i.e. an unconnected pin or a driving source which goes to a high impedance state). To overdrive the “bus hold” circuits, an external driver must be capable of supplying approximately 400 mA minimum sink or source current at valid input voltage levels. Since this “bus hold” circuitry is active and not a “resistive” type element, the associated power supply current is negligible and power dissipation is significantly reduced when compared to the use of passive pull-up resistors. "Pull-Up/Pull-Down" Bond Pad Output Driver External Pin Input Protection Circuitry Input Buffer Input Buffer exists only on I/O pins Figure 6a. Bus Hold Circuitry Pin 2-16, 35-39 "Pull-Up" Bond Pad Output Driver PCC Input Buffer External Pin P Input Protection Circuitry Input Buffer exists only on I/O pins Figure 6b. Bus Hold Circuit Pin 26-32, 34 25/37 7 1 1 1 1 1 1 1 6 0 1 0 0 0 0 0 5 0 0 1 1 1 0 0 4 0 0 1 0 0 0 0 3 1 0 w 0 0 1 1 2 0 1 0 w w 7 6 mod mod w w 0 0 mod mod 4 3 reg 0 0 0 data addr-low addr-low 0 reg 0 reg PUSH = Push: Register/memory Register Segment register 1 0 0 1 1 0 1 1 1 0 1 0 0 reg 1 1 1 reg 1 1 0 mod 1 1 0 r/m POP = Pop: Register/memory Register Segment register 1 0 0 0 1 0 0 0 1 0 1 1 0 reg 1 1 1 reg 1 1 1 mod 0 0 0 r/m XCHG = Exchange: Register/memory with register Register with accumulator 1 1 0 0 0 0 0 1 0 0 1 mod IN = Input from: Fixed port Variable port 1 1 1 1 1 1 0 0 0 1 1 1 0 0 w w port OUT = Output to: Fixed port Variable port XLAT = Translate byte to AL LEA = Load EA to register LDS = Load pointer to DS LES = Load pointer to ES LAHF = Load AH with flags SAHF = Store AH into flags PUSHF = Push flags POPF = Pop flags 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 w w 1 1 1 0 1 0 0 1 port 0 0 1 1 1 d 1 reg 0 1 1 0 1 w reg mod mod mod 5 reg reg reg reg 2 1 0 r/m r/m r/m r/m 7 6 5 4 3 2 1 data data if w = 1 addr-high addr-high 0 7 6 5 4 3 2 data if w = 1 1 0 r/m r/m r/m r/m 26/37 MSM80C88A-10RS/GS/JS MOV = Move: Register/memory to/from register Immediate to register/memory Immediatye to register Memory to accumulator Accumulator to memory Register/memory to segment register Segment register to register/memory ¡ Semiconductor DATA TRANSFER 0 1 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 ADD = Add: Reg./memory with register to either Immediate to register/memory Immediate to accumulator ADC = Add with carry: Reg./memory with register to either Immediate to register/memory Immediate to accumulator INC = Increment: Register/memory Register AAA = ASCII adjust for add DAA = Decimal adjust for add SUB = Subtract: Reg./memory with register to either Immediate from register/memory Immediate from accumulator SBB = Subtract with borrow: Reg./memory and register to either Immediate from register/memory Immediate from accumulator DEC = Decrement: Register/memory Register NEG = Change sign CMP = Compare: Register/memory and register Immediate with register/memory Immediate from accumulator AAS = ASCII adjust for subtract ARITHMETHIC 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 1 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 d s 0 d s 0 w w w w w w d s 0 d s 0 w w w w w w 0 0 1 1 d s 0 1 w w w 1 1 w reg 1 1 w 1 0 0 1 0 0 1 1 w reg 1 1 1 1 1 1 1 0 0 1 0 0 1 1 0 mod mod mod 0 0 1 0 0 0 mod mod mod mod mod mod mod mod mod mod 0 1 1 reg 1 1 data 1 0 reg 1 1 data reg 0 1 data 0 reg 1 0 data reg 0 0 data r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m data data if w = 1 data data if w = 1 data data if w = 1 data data if w = 1 data data if w = 1 data if s:w = 01 data if s:w = 01 data if s:w = 01 data if s:w = 01 data if s:w = 01 ¡ Semiconductor MSM80C88A-10RS/GS/JS 27/37 DAS = Decimal adjust for subtract MUL = Multiply (unsigned) IMUL = Integer multiply (signed) AAM = ASCII adjust for multiply DIV = Divide (unsigned) IDIV = Integer divide (signed) AAD = ASCII adjust for divide CBW = Convert byte to word CWD = Convert word to double word 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 0 0 0 1 w w 0 w w 1 0 1 mod mod 0 0 mod mod 0 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1 r/m r/m 0 1 0 r/m r/m 0 1 0 ¡ Semiconductor MSM80C88A-10RS/GS/JS 28/37 1 1 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 0 1 0 NOT = Invert SHL/SAL = Shift logical/arithmetic left SHR = Shift logical right SAR = Shift arithmetic right ROL = Rotate left ROR = Rotate right RCL = Rotate left through carry RCR = Rotate right through carry AND = And: Reg./memory with register to either Immediate to register/memory Immediate to accumulator TEST = And function to flags, no result: Register/memory and register Immediate data and register/memory Immediate data and accumulator OR = Or: Reg./memory and register to either Immediate to register/memory Immediate to accumulator XOR = Exclusive or: Reg./memory and register to either Immediate to register/memory Immediate to accumulator LOGIC 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 d 0 0 d 0 0 0 1 0 d 0 0 1 v v v v v v v w w w w w w w w w w w w w w w w w w w w mod mod mod mod mod mod mod mod mod mod mod mod mod mod mod mod 1 0 0 1 0 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 reg 1 0 data reg 0 1 data reg 0 0 data reg 0 0 data 1 0 0 1 0 0 1 1 r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m r/m data data if w = 1 data data if w = 1 data data if w = 1 data data if w = 1 data if w = 1 data if w = 1 data if w = 1 data if w = 1 ¡ Semiconductor MSM80C88A-10RS/GS/JS 29/37 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 0 1 1 0 1 z w w w w w CJMP = Conditional JMP JE/JZ = Jump on equal/zero JZ/JNGE = Jump on less/not greater or equal JLE/JNG = Jump on less or equal/not greater JB/JNAE = Jump on below/not above or equal JBE/JNA = Jump on below or equal/not above JP/JPE = Jump on parity/parity even JO = Jump on over flow JS = Jump on sign JNE/JNZ = Jump on not equal/not zero JNL/JGE = Jump on not less/greater or equal JNLE/JG = Jump on not less or equal/greater JNB/JAE = Jump on not below/above or equal JNBE/JA = Jump on not below or equal/above JNP/JPO = Jump on not parity/parity odd JNO = Jump on not overflow JNS = Jump on not sigh LOOP = Loop CX times LOOPZ/LOOPE = Loop while zero/equal LOOPNZ/LOOPNE = Loop while not zero equal JCXZ = Jump on CX zero 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp INT = Interrupt Type specified Type 3 INTO = Interrupt on overflow IRET = Interrupt return 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 type 30/37 MSM80C88A-10RS/GS/JS REP = Repeat MOVS = Move byte/word CMPS = Compare byte/word SCAS = Scan byte/word LODS = Load byte/word to AL/AX STOS = Store byte/word from AL/AX ¡ Semiconductor STRING MANIPULATION ¡ Semiconductor PROCESSOR CONTROL CLC = Clear carry CMC = Complementary carry STC = Set carry CLD = Clear direction STD = Set direction CLI = Clear interrupt STI = Set interrupt HLT = Halt WAIT = Wait ESC = Escape ( to external device) LOCK = Bus lock prefix 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 0 0 1 0 x 0 0 0 0 0 0 1 1 0 1 x 0 0 1 1 0 1 0 1 0 1 x 0 CALL = Call: Direct within segment Indirect within segment Direct intersegment 7 1 1 1 6 1 1 0 5 1 1 0 4 0 1 1 3 1 1 1 2 0 1 0 1 0 1 1 0 0 1 0 Indirect intersegment 1 1 1 1 1 1 1 1 JMP = Unconditional Jump: Direct within segment Direct within segment-short Indirect within segment Direct intersegment 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 Indirect intersegment 1 1 1 1 1 1 1 0 RET = Return from CALL: Within segment Within seg. adding immediate to SP Intersegment Intersegment adding immediate to SP 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 mod x x x r/m CONTROL TRANSFER 7 mod mod mod 5 4 3 2 1 0 disp-low 0 1 0 r/m offset-low seg-low 0 1 1 r/m disp-low disp 1 0 0 offset-low seg-low 1 0 1 7 6 5 4 3 disp-high 2 1 0 7 6 5 4 3 2 1 0 offset-high seg-high disp-high r/m offset-high seg-high r/m data-low data-high data-low dat-high 31/37 MSM80C88A-10RS/GS/JS mod 6 ¡ Semiconductor MSM80C88A-10RS/GS/JS Notes: AL = 8-bit accumulator AX = 18-bit accumulator CX = Count register DS = Data segment EX = Extra segment Above/below refers to unsigned value Greater=more positive Less=less positive (more negative) signed value If d=1 then “to” reg: If d=0 then “from” reg. If w=1 then word instruction: If w=0 then byte instruction If mod=11 then r/m is treated as a REG field If mod=00 then DISP=0*, disp-low and disp-high are absent If mod=01 then DISP=disp-low sign-extended to 16 bits, disp-high is absent If mod=10 then DISP=disp-high: disp-low If r/m=000 then EA=(BX)+(SI)+DISP If r/m=001 then EA=(BX)+(DI)+DISP If r/m=010 then EA=(BP)+(SI)+DISP If r/m=011 then EA=(BP)+(DI)+DISP If r/m=100 then EA=(SI)+DISP If r/m=101 then EA=(DI)+DISP If r/m=110 then EA=(BP)+DISP* If r/m=111 then EA=(BX)+DISP DISP follows 2nd byte of instruction (before data if required) * except if mod=00 and r/m=110 then EA-disp-high: disp-low If s:w=01 then 16 bits of immediate data form the operand If s:w=11 then an immediate data byte is sign extended to form the 16-bit operand If v=0 then “count”=1:if v=1 then “count” in (CL) x=don’ t care z is used for string primitives for comparison with ZF FLAG SEGMENT OVERRIDE PREFIX 001 reg 110 REG is assigned according to the following table: 16-Bit (w=1) 8-Bit (w=0) 000 AX 000 AL 001 CX 001 CL 010 DX 010 DL 011 BX 011 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH Segment 00 01 10 11 ES CS SS DS Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file: FLAGS=x:x:x:x:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF) 32/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Remarks M80C85AH Low-speed device (Old) M80C85A/M80C85A-2 M80C86A-10 M80C86A/M80C86A-2 16bit MPU M80C88A-10 M80C88A/M80C88A-2 8bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M82C37B-5 M81C55 M82C37A/M82C37A-5 RAM.I/O, timer DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C55A-2 M82C53-5 M82C55A-5 Timer PPI 8bit MPU 33/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS Differences between MSM80C88A-10 and MSM80C88A-2, MSM80C88A 1) Manufacturing Process All devices use a 1.5 m Si-CMOS process technology. 2) Design Although circuit timings of these devices are a little different, these devices have the same chip size and logics. 3) Electrical Characteristics Oki's '96 Data Book for MICROCONTROLLER describes that the MSM80C88A-10 satisfies the electrical characteristics of the MSM80C88A-2 and MSM80C88A. 4) Other notices 1) The noise characteristics of the high-speed MSM80C88A-10 (for 10 MHz) are a little different from those of the MSM80C88A-2 and MSM80C88A. Therefore when devices are replaced for upgrading, it is recommended to perform noise evaluation. 2) The characteristics of the MSM80C88A-10 basically satisfy those of the MSM80C88A-2 and MSM80C88A but their timings are a little different. When critical timing is required in designing it is recommended to evaluate operating margins at various temperatures and voltages. 34/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS PACKAGE DIMENSIONS (Unit : mm) DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 35/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS (Unit : mm) QFJ44-P-S650-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 36/37 ¡ Semiconductor MSM80C88A-10RS/GS/JS (Unit : mm) QFP56-P-1519-1.00-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.46 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 37/37