OKI MSM80C51F

E2E1037-19-41
This
version: Mar. 1995
MSM80C31F/80C51F
¡ Semiconductor
MSM80C31F/MSM80C51F
¡ Semiconductor
CMOS 8-Bit Microcontroller
GENERAL DESCRIPTION
The OKI MSM80C31F/MSM80C51F microcontroller is a low-power, 8-bit device implemented
in OKI's silicon-gate complementary metal-oxide semiconductor process technology. The
device includes 4K bytes of mask programmable ROM (MSM80C51F only), 128 bytes of
data RAM, 32 I/O lines, two 16-bit timer/counters, a five-source two-level interrupt
structure, a full duplex serial port, and an oscillator and clock circuitry. In addition, the device
has two software selectable modes for further power reduction — Idle and Power Down. Idle
mode freezes the CPU's in-struction execution while maintaining RAM and allowing the timers,
serial port and interrupt system to continue functions. Power Down mode saves the RAM
contents but freezes the oscillator causing all other device functions to be inoperative.
FEATURES
• Low power consumption by 2 mm silicon gate CMOS process technology
• Fully static circuit
• Internal program memory
: 4K bytes (MSM80C51F)
• External program memory space
: 64K bytes
• Internal data memory (RAM)
: 128 bytes
• External data memory (RAM) space
: 64K bytes
• I/O ports
: 8-bit ¥ 4 ports
• Two 16-bit timer/counters
• Multifunctional serial port (UART)
• Five interrupt sources (Priority can be set)
• Four sets of working registers (R0-7 ¥ 4)
• Stack
: Internal data memory (RAM)
128-byte area can be used arbitrarily (by SP specified)
• Two CPU power-down modes
(1) Idle mode
: CPU stopped while oscillation continued.
(Software setting)
(2) PD mode
: CPU and oscillation all stopped.
(Software setting)
(Setting I/O ports to floating status possible)
• Operating temperature
: –40 to +85°C (@ 12 MHz, VCC = 5 V ±20%)
–20 to +70°C (@ 16 MHz, VCC = 5 V ±5%)
• 2-byte 1-machine cycle instructions
: 1 msec. @ 12 MHz
0.75 msec. @ 16 MHz
• Multiplication/division instructions
: 4 msec. @ 12 MHz
3 msec. @ 16 MHz
• Instruction code addressing method
Byte specification
: Data addressing (direct)
Bit specification
: Bit addressing
1/38
¡ Semiconductor
• Package options
40-pin plastic DIP (DIP40-P-600-2.54)
:
44-pin plastic QFP (QFP44-P-910-0.80-2K)
:
44-pin plastic QFJ (PLCC) (QFJ44-P-S650-1.27) :
MSM80C31F/80C51F
(MSM80C31F-¥¥¥RS) (MSM80C51F-¥¥¥RS)
(MSM80C31F-¥¥¥GS) (MSM80C51F-¥¥¥GS)
(MSM80C31F-¥¥¥JS) (MSM80C51F-¥¥¥JS)
¥¥¥ indicates the code number.
DIFFERENCES BETWEEN MSM80C31F/MSM80C51F AND MSM80C31/MSM80C51
• Operating frequency
0.5 to 16 MHz ..................... MSM80C31F-1/MSM80C51F-1
0.5 to 12 MHz ..................... MSM80C31/MSM80C51/MSM80C31F/MSM80C51F
• External clock input terminal
XTAL1 ................................. MSM80C31F(-1)/MSM80C51F(-1)
XTAL2 ................................. MSM80C31/MSM80C51
• Emulation mode
Output impedance of ALE and PSEN pins becomes about 20 kW while CPU is being reset in
MSM80C31F/MSM80C51F.
Any other functions and electrical characteristics of MSM80C31F/MSM80C51F except for
above three differences are the same as those of MSM80C31/MSM80C51.
2/38
PORT 0
P0.0 to P0.7
PCLL
PCH
PCL
ROM
R/W
SPECIAL
FUNCTION
REGISTER
ADDRESS
DECODER
PLA
4096 WORDS
¥ 8 BITS
IR
SENSE AMP
AIR
XTAL1
C-ROM
ALE
PSEN
DPH
DPL
RESET
R/W AMP
128 WORDS
¥ 8 BITS
SP
ACC
TR1
TR2
RAMDP
BR
PSW
ALU
TL1
TH0
PORT 3
TIMER/COUNTER
TL0
TMOD
TCON
IE
INTERRUPT
IP
SBUF(T)
SBUF(R)
SERIAL IO
SCON
3/38
MSM80C31F/80C51F
PORT 1
TH1
P3.0 to P3.7
ADDRESS DECODER
EA
PCON
OSC AND TIMING
XTAL2
P1.0 to P1.7
SIGNALS
¡ Semiconductor
PCHL
ADDRESS DECODER
PORT 2
P2.0 to P2.7
SIGNALS
BLOCK DIAGRAM
CONTROL
XTAL1
S2
S3
S4
S5
S6
S1
S2
S3
M2
S4
S5
S6
S1
S2
S3
M1
S4
S5
S6
S1
S2
S3
S4
S5
S6
1
0
1
ALE
PSEN
RD/WR
0
¡ Semiconductor
S1
STEP
M1
CLOCK WAVEFORMS
M1
Basic Timing Chart
CYCLE
1
0
1
0
DPL&Rr
PORT-0
PCL
PCL
1
PCH
PCH
PCL
PCL
PCL
PCH
PCH
DPH & PORT DATA
PCH
PCH
,,,
,
,,,
,
,,
,,,
,,,
,,,
,,,
,,,
,
Instruction decoding
Instruction execution
PC+1
Instruction execution
PC+1
PC+1
TM+1
Instruction execution
execution
Port output/input
Instruction execution
4/38
MSM80C31F/80C51F
TM+1
TM+1
External data memory instruction
Port output/input
,,,
,
,,,
,,
,,,
,,,
,,,
,,,
,,
,,
,,,
,,,
,,,
,,,
,,,
,,,
,,
,,,
,,
,,
,
,,,
,,,
,,
,
,,,
TM+1
,,,
PC+1
PORT NEW DATA
Instruction decoding
Instruction execution
PC+1
,,,
Instruction decoding
,,,
,,
,
,,,
PORT OLD DATA
0
,,
1
,,,
,,,
,,,
,,,
,,
,,
,,,
,,
,,
0
,,,
,
,,,
1
PCH
DATA STABLE
,,,
DATA STABLE
,,,
PORT¨CPU
ACC & RAM
,,,
0
CPU¨PORT
PCL
0
,,,
,,
PORT-2
1
¡ Semiconductor
MSM80C31F/80C51F
PIN CONFIGURATION (TOP VIEW)
P1.0
1
40
VCC
P1.1
2
39
P0.0
P1.2
3
38
P0.1
P1.3
4
37
P0.2
P1.4
5
36
P0.3
P1.5
6
35
P0.4
P1.6
7
34
P0.5
P1.7
8
33
P0.6
RESET
9
32
P0.7
RXD/P3.0 10
TXD/P3.1 11
31
30
EA
ALE
INT0/P3.2 12
29
PSEN
INT1/P3.3 13
28
P2.7
T0/P3.4 14
27
P2.6
T1/P3.5 15
26
P2.5
WR/P3.6 16
25
P2.4
RD/P3.7 17
XTAL2 18
24
23
P2.3
XTAL1 19
22
P2.1
20
21
P2.0
VSS
P2.2
40-Pin Plastic DIP
5/38
¡ Semiconductor
,
MSM80C31F/80C51F
P1.5
P1.6
P1.7
RESET
P3.0/RXD
NC
P3.1/TXD
P3.2/INT0
34 P0.3
35 P0.2
36 P0.1
37 P0.0
38 VCC
39 NC
40 P1.0
41 P1.1
42 P1.2
43 P1.3
44 P1.4
PIN CONFIGURATION (TOP VIEW) (continued)
1
33 P0.4
2
32 P0.5
3
31 P0.6
4
30 P0.7
5
29 EA
6
28 NC
7
27 ALE
8
26 PSEN
P2.4 22
P2.3 21
P2.2 20
P2.1 19
P2.0 18
VSS 17
VSS 16
23 P2.5
XTAL1 15
P3.5/T1/HPDI 11
XTAL2 14
24 P2.6
P3.7/RD 13
25 P2.7
P3.6/WR 12
9
P3.4/T0 10
P3.3/INT1
44-Pin Plastic QFP
6/38
¡ Semiconductor
MSM80C31F/80C51F
29 P2.5
30 P2.6
31 P2.7
32 PSEN
33 ALE
34 NC
35 EA
36 P0.7
37 P0.6
25 P2.1
24 P2.0
23 NC
22 VSS
21 XTAL1
20 XTAL2
19 P3.7/RD
18 P3.6/WR
P3.4/T0 16
P1.4 6
26 P2.2
P3.5/T1 17
P1.3 5
27 P2.3
P3.3/INT1 15
P1.2 4
28 P2.4
P3.2/INT0 14
P1.1 3
NC 12
P1.0 2
P3.1/TXD 13
NC 1
RESET 10
VCC 44
P3.0/RXD 11
P0.0 43
P1.7 9
P0.1 42
P1.6 8
P0.2 41
P1.5 7
P0.3 40
38 P0.5
39 P0.4
PIN CONFIGURATION (TOP VIEW) (continued)
44-Pin Plastic QFJ (PLCC)
7/38
¡ Semiconductor
MSM80C31F/80C51F
PIN DESCRIPTION
Symbol
Description
VSS
Ground potential
VCC
Supply voltage during Normal, Idle and Power Down operation
Port 0.0
- 0.7
Port 1.0
- 1.7
Port 0 is an 8-bit open-drain bidirectional I/O port. It is also the mutiplexed low-order address
and data bus during accesses to external memory.
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. It can drive CMOS inputs without
external pull-ups.
Port 2.0
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. It outputs the high-order address
- 2.7
byte during accesses to external memory. It can drive CMOS inputs without external pull-ups.
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. It also provides various special
features, as shown below:
Alternate Function
Port Pin
(serial input port)
RXD
P3.0
(serial output port)
TXD
P3.1
(external interrupt)
INT0
P3.2
(external interrupt)
INT1
P3.3
(Timer 0 external input)
T0
P3.4
(Timer 1 external input)
T1
P3.5
(external data memory write strobe)
WR
P3.6
(external data memory read strobe)
RD
P3.7
Port 3 can drive CMOS inputs without external pull-ups.
Port 3.0
- 3.7
RESET
ALE
Reset input pin. A reset is accomplished by holding the RESET pin high for at least 1ms.
even if the oscillator has been stopped. The CPU responds by executing an internal reset. An
internal pull-down resistor permits Power-On reset using only a capacitor connected to VCC.
This pin does not receive the power down voltage since the function has been transferred to the
VCC pin.
Address Latch Enable. This output latches for latching the low byte of the address during
accesses to external memory. For this purpose, ALE is activated twice every machine cycle or
at a constant rate of 1/6th the oscillator frequency, except during an external memory access at
which time one ALE pulse is skipped. ALE can drive CMOS inputs without an external pull-up.
PSEN
EA
Program Store Enable output. This output is the read strobe to external program memory.
For this purpose, PSEN is activated twice every machine cycle. (However, when executing out
of external program memory, two activations of PSEN are skipped during each access to
external data memory.) PSEN is not activated during fetches from internal program memory.
It can drive CMOS inputs without an external pull-up.
External Access input pin. When EA is held high, the CPU executes out of internal program
memory (unless the program counter exceeds 0FFFH).
When EA is held low, the CPU executes only out of external program memory.
EA must not be floated.
XTAL1
Crystal 1 pin. It is an input to the inverting amplifier which forms the internal oscillator.
XTAL2
Crystal 2 pin. It is an output of the inverting amplifier that forms the internal oscillator.
8/38
¡ Semiconductor
MSM80C31F/80C51F
SPECIAL FUNCTION REGISTERS
DATA MEMORY AND SPECIAL FUNCTION REGISTER LAYOUT DIAGRAM
0F0H
0E0H
0D0H
0B8H
0B0H
0A8H
0A0H
99H
98H
90H
8DH
8CH
8BH
8AH
89H
88H
87H
83H
82H
81H
80H
B
ACC
PSW
IP
P3
IE
P2
SBUF
SCON
P1
TH1
TH0
TL1
TL0
TMOD
TCON
PCON
DPH
DPL
SP
P0
7F
USER RAM
80W ¥ 8 bits
DATA RAM
30
2F
20
1F
18
17
10
0F
08
07
00
7F
78
BIT ADDRESSABLE
RAM
7
0
R7
BANK 3
R0
R7
BANK 2
R0
R7
BANK 1
R0
R7
BANK 0
R0
BIT ADDRESSING
DATA ADDRESSING
9/38
¡ Semiconductor
MSM80C31F/80C51F
DETAILED DIAGRAM OF DATA MEMORY (RAM)
7FH
127
USER DATA RAM
7F
7E
7D
7C
7B
7A
79
78
47
2EH
77
76
75
74
73
72
71
70
46
2DH
6F
6E
6D
6C
6B
6A
69
68
45
2CH
67
66
65
64
63
62
61
60
44
2BH
5F
5E
5D
5C
5B
5A
59
58
43
2AH
57
56
55
54
53
52
51
50
42
29H
4F
4E
4D
4C
4B
4A
49
48
41
28H
47
46
45
44
43
42
41
40
40
27H
3F
3E
3D
3C
3B
3A
39
38
39
26H
37
36
35
34
33
32
31
30
38
25H
2F
2E
2D
2C
2B
2A
29
28
37
24H
27
26
25
24
23
22
21
20
36
23H
1F
1E
1D
1C
1B
1A
19
18
35
22H
17
16
15
14
13
12
11
10
34
21H
0F
0E
0D
0C
0B
0A
09
08
33
20H
07
06
05
04
03
02
01
00
32
INDIRECT ADDRESSING
2FH
DATA ADDRESSING
48
BIT ADDRESSING
30H
31
1FH
24
18H
23
17H
Bank 2
10H
16
0FH
15
Bank 1
08H
8
07H
7
REGISTER ADDRESSING
Bank 3
Bank 0
00H
0
10/38
¡ Semiconductor
MSM80C31F/80C51F
DETAILED DIAGRAM OF SPECIAL FUNCITON REGISTERS
Data
Address
(MSB)
Special
Function
Register
(LSB) Symbol
Bit Address
0F0H
F7
F6
F5
F4
F3
F2
F1
F0
0E0H
0D0H
E7
CY
D7
E6
AC
D6
E5
F0
D5
0B8H
—
—
—
E4
RS1
D4
PS
BC
E3
RS0
D3
PT1
BB
E2
OV
D2
PX1
BA
E1
F1
D1
PT0
B9
E0
P
D0
PX0
B8
0B0H
B6
B5
—
—
B4
ES
AC
B3
ET1
AB
B2
EX1
AA
B1
ET0
A9
B0
EX0
A8
P3
0A8H
B7
EA
AF
0A0H
A7
A6
A5
A4
A3
A2
A1
A0
P2
98H
SM0
9F
SM1
9E
TI
99
RI
98
SCON
90H
97
96
91
90
P1
99H
Not Bit Addressable
SM2 REN
TB8
RB8
9D
9C
9B
9A
95
94
93
92
B
ACC
PSW
IP
IE
SBUF
8DH
Not Bit Addressable
TH1
8CH
Not Bit Addressable
TH0
8BH
Not Bit Addressable
TL1
8AH
Not Bit Addressable
TL0
89H
Not Bit Addressable
TF0
TR0
IE1
IT1
8D
8C
8B
8A
88H
TF1
8F
TR1
8E
TMOD
IE0
89
IT0
88
TCON
87H
Not Bit Addressable
PCON
83H
Not Bit Addressable
DPH
82H
Not Bit Addressable
DPL
Not Bit Addressable
81H
80H
87
86
85
84
83
SP
82
81
80
P0
11/38
¡ Semiconductor
MSM80C31F/80C51F
INSTRUCTION LIST
List of Instruction Symbols
A
:
AB
:
AC
:
B
:
C
:
DPTR
:
PC
:
Rr
:
SP
:
AND
:
OR
:
XOR
:
+
:
–
:
X
:
/
:
(X)
:
((X))
:
#
:
@
:
=
:
⫽
:
¨
:
Æ
:
—
:
<
:
>
:
bit address
:
code address :
data
:
relative offset :
direct address :
Accumulator
Register pair
Auxiliary carry flag
Arithmetic operation register
Carry flag
Data pointer
Program counter
Register indicator (r = 0 to 7)
Stack pointer
Logical product
Logical sum
Exclusive-OR
Addition
Subtraction
Multiplication
Division
Denotes the contents of X
Denotes the contents of address determined by the contents of X
Denotes the immediate data
Denotes the indirect address
Equality
Non-equality
Substitution
Substitution
Negation
Smaller than
Larger than
RAM and the special function register bit specifier address (b0 to b7)
Absolute address (A0 to A15)
Immediate data (I0 to I7)
Relative jump address offset value (R0 to R7)
RAM and the special function register byte specifier address (a0 to a7)
12/38
¡ Semiconductor
MSM80C31F/80C51F
MSM80C31F/MSM80C51F Instruction Codes
L
H
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
0
0000
1
0001
AJMP
address 11
(Page 0)
ACALL
JBC bit,
address 11
rel
(Page 0)
AJMP
JB bit,
address 11
rel
(Page 1)
ACALL
JNB bit,
address 11
rel
(Page 1)
AJMP
JC
address 11
rel
(Page 2)
ACALL
JNC rel
address 11
(Page 2)
AJMP
JZ rel
address 11
(Page 3)
ACALL
JNZ rel
address 11
(Page 3)
AJMP
SJMP rel address 11
(Page 4)
ACALL
MOV DPTR, address 11
#data 16
(Page 4)
AJMP
ORL C, /bit address 11
(Page 5)
ACALL
ANL C, /bit address 11
(Page 5)
AJMP
PUSH
address 11
direct
(Page 6)
ACALL
POP
address 11
direct
(Page 6)
AJMP
MOVX A, address 11
@DPTR
(Page 7)
ACALL
MOVX
address 11
@DPTR, A
(Page 7)
NOP
2BYTES
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
LJMP
address 16
RR A
INC A
INC
direct
INC @R0
INC @R1
LCALL
adress 16
RRC A
DEC A
DEC
direct
DEC @R0
DEC @R1
RET
RL A
ADD A,
#data
ADD A,
direct
ADD A,
@R0
ADD A,
@R1
RETI
RLC A
ADDC A,
#data
ADDC A,
direct
ADDC A,
@R0
ADDC A,
@R1
ORL A,
#data
ORL A,
direct
ORL A,
@R0
ORL A,
@R1
ANL A,
#data
ANL A,
direct
ANL A,
@R0
ANL A,
@R1
XRL A,
#data
XRL A,
direct
XRL A,
@R0
XRL A,
@R1
XRL
direct, A
ORL
direct,
#data
ANL
direct,
#data
XRL
direct,
#data
ORL C,
bit
JMP
@A+DPTR
MOV A,
#data
ANL C,
bit
MOVC A,
@A+PC
DIV AB
MOV bit,
C
MOVC A,
@A+DPTR
SUBB A,
#data
MOV C,
bit
INC DPTR
MUL AB
CPL bit
CPL C
CJNE A,
#data
rel
CJNE A,
direct,
rel
CLR bit
CLR C
SWAP A
XCH A,
direct
XCH A,
@R0
XCH A,
@R1
SETB bit
SETB C
DA A
DJNZ
direct,
rel
XCHD A,
@R0
XCHD A,
@R1
MOVX A,
@R0
MOVX A,
@R1
CLR A
MOV A,
direct
MOV A,
@R0
MOV A,
@R1
MOVX
@R0, A
MOVX
@R1, A
CPL A
MOV
direct, A
MOV
@R0, A
MOV
@R1, A
ORL
direct, A
ANL
direct, A
MOV
direct
#data
MOV
direct1,
direct2
SUBB A,
direct
MOV @R0, MOV @R1,
#data
#data
MOV
direct,
@R0
MOV
direct,
@R1
SUBB A,
@R0
SUBB A,
direct
MOV @R0, MOV @R1,
direct
direct
CJNE @R0
CJNE @R1,
#data,
#data, rel
rel
3BYTES
MNEMONIC
2CYCLES
4CYCLES
13/38
¡ Semiconductor
MSM80C31F/80C51F
MSM80C31F/MSM80C51F Instruction Codes (continued)
L
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
0
0000
INC R0
INC R1
INC R2
INC R3
INC R4
INC R5
INC R6
INC R7
1
0001
DEC R0
DEC R1
DEC R2
DEC R3
DEC R4
DEC R5
DEC R6
DEC R7
H
2
0010
ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7
3
0011
ADDC A, R0 ADDC A, R1 ADDC A, R2 ADDC A, R3 ADDC A, R4 ADDC A, R5 ADDC A, R6 ADDC A, R7
4
0100
ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4 ORL A, R5 ORL A, R6 ORL A, R7
5
0101
ANL A, R0
ANL A, R1
ANL A, R2
ANL A, R3
ANL A, R4
ANL A, R5
ANL A, R6
ANL A, R7
6
0110
XRL A, R0
XRL A, R1
XRL A, R2
XRL A, R3
XRL A, R4
XRL A, R5
XRL A, R6
XRL A, R7
7
0111
MOV R0,
#data
MOV R1,
#data
MOV R2,
#data
MOV R3,
#data
MOV R4,
#data
MOV R5,
#data
MOV R6,
#data
MOV R7,
#data
8
1000
MOV
direct,
R0
MOV
direct,
R1
MOV
direct,
R2
MOV
direct,
R3
MOV
direct,
R4
MOV
direct,
R5
MOV
direct,
R6
MOV
direct,
R7
9
1001
SUBB A,
R0
SUBB A,
R1
SUBB A,
R2
SUBB A,
R3
SUBB A,
R4
SUBB A,
R5
SUBB A,
R6
SUBB A,
R7
A
1010
MOV R0,
direct
MOV R1,
direct
MOV R2,
direct
MOV R3,
direct
MOV R4,
direct
MOV R5,
direct
MOV R6,
direct
MOV R7,
direct
B
1011
CJNE R0,
#data
rel
CJNE R1,
#data
rel
CJNE R2,
#data
rel
CJNE R3,
#data
rel
CJNE R4,
#data
rel
CJNE R5,
#data
rel
CJNE R6,
#data
rel
CJNE R7,
#data
rel
C
1100
XCH A,
R0
XCH A,
R1
XCH A,
R2
XCH A,
R3
XCH A,
R4
XCH A,
R5
XCH A,
R6
XCH A,
R7
D
1101
DJNZ R0,
rel
DJNZ R1,
rel
DJNZ R2,
rel
DJNZ R3,
rel
DJNZ R4,
rel
DJNE R5,
rel
DJNE R6,
rel
DJNE R7,
rel
E
1110
MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7
F
1111
MOV R0, A MOV R1, A MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6, A MOV R7, A
14/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details
Type
Mnemonic
ADD A, Rr
ADD A, direct
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
1
1
0
0
1
r1
0
r0
1
1
(AC), (0V), (C), (A) ¨ (A)+(Rr)
1
2
1
(AC), (0V), (C), (A) ¨ (A)+(direct
address)
a7 a6 a5 a4
a3 a2 a1 a0
0
0
1
0
0
1
1
r0
1
1
(AC), (0V), (C), (A) ¨ (A)+((Rr))
ADD A, #data
0
0
1
0
0
1
0
0
2
1
(AC), (0V), (C), (A) ¨ (A)+#data
I7
I6
I5
I4
I3
I2
I1
I0
0
0
1
1
1
r2
r1
r0
1
1
(AC), (0V), (C), (A) ¨ (A)+(C)+(Rr)
0
0
1
1
0
1
0
1
2
1
(AC), (0V), (C), (A) ¨ (A)+(C)+
(direct address)
ADDC A, direct
a7 a6 a5 a4
Airthmetic operation instructions
0
r2
ADD A, @Rr
ADDC A, Rr
Accumulation operation
instructions
1
Description
Bytes Cycles
a3 a2 a1 a0
ADDC A, @Rr
0
0
1
1
0
1
1
r0
1
1
(AC), (0V), (C), (A) ¨ (A)+(C)+((Rr))
ADDC A, #data
0
0
1
1
0
1
0
0
2
1
(AC), (0V), (C), (A) ¨ (A)+(C)+#data
I7
I6
I5
I4
I3
I2
I1
I0
SUBB A, Rr
1
0
0
1
1
r2
r1
r0
1
1
(AC), (0V), (C), (A) ¨ (A)–((C))+((Rr))
SUBB A, direct
1
0
0
1
0
1
0
1
2
1
(AC), (0V), (C), (A) ¨ (A)–((C)+
(direct address))
r0
1
1
(AC), (0V), (C), (A) ¨ (A)–((C)+((Rr))
2
1
(AC), (0V), (C), (A) ¨ (A)–((C)+
#data)
SUBB A, @Rr
SUBB A, #data
a7 a6 a5 a4
a3 a2 a1 a0
1
0
0
0
1
1
1
1
0
0
1
0
1
0
0
I7
I6
I5
I4
I3
I2
I1
I0
MUL AB
1
0
1
0
0
1
0
0
1
4
(AB) ¨ (A) x (B)
DIV AB
1
0
0
0
0
1
0
0
1
4
(A)quotient,
(B) remainder
DA A
1
1
0
1
0
1
0
0
1
1
When the contents of accumulator bits
0 thru 3 are greater than 9, or when
auxiliary carry (AC) is 1, 6 is added to
bits 0 thru 3. Bits 4 thru 7 are then
examined, and when bits 4thru 7
follwoing compensation of lower bits 0
thru 3 is greater than 9, or when carry
(C) is 1, 6 is added to bits 4 thru 7. As
a result, the cary flag can be set, but
cannot be cleared.
CLR A
1
1
1
0
0
1
0
0
1
1
(A) ¨ 0
CPL A
1
1
1
1
0
1
0
0
1
1
(A) ¨ (A)
PL A
0
0
1
0
0
0
1
1
1
1
C
PL C
0
0
1
1
0
0
1
1
1
1
C
¨ (A)/(B)
Accumulator
¨¨¨¨¨¨¨¨
7
0
Accumulator
¨¨¨¨¨¨¨¨
7
0
15/38
¡ Semiconductor
MSM80C31F/80C51F
Mnemonic
RR A
Increment/decrement
Type
Accumulation operation
instructions
Instruction Set Details (continued)
0
0
0
0
0
0
1
1
Bytes Cycles
1
Description
1
C
RRC A
0
0
0
1
0
0
1
1
1
1
C
1
(A4 -7) ´ (A0 -3)
0
0
1
1
(A) ¨ (A)+1
r1
r0
1
1
(Rr) ¨ (Rr)+1
1
2
1
(direct address) ¨ (direct address)+1
1
0
0
0
INC A
0
0
0
0
0
1
INC Rr
0
0
0
0
1
r2
0
0
0
0
0
1
0
INC direct
a7 a6 a5 a4
Accumulator
ÆÆÆÆÆÆÆÆ
7
0
1
1
1
Accumulator
ÆÆÆÆÆÆÆÆ
7
0
0
SWAP A
0
a3 a2 a1 a0
INC @Rr
0
0
0
0
0
1
1
r0
1
1
((Rr)) ¨ ((Rr))+1
INC DPTR
1
0
1
0
0
0
1
1
1
2
(DPTR) ¨ (DPTR)+1
DEC A
0
0
0
1
0
1
0
0
1
1
(A) ¨ (A)–1
1
(Rr) ¨ (Rr)–1
DEC Rr
0
0
0
1
1
r2
r1
r0
1
DEC direct
0
0
0
1
0
1
0
1
2
1
(direct address) ¨ (direct address)–1
a7 a6 a5 a4
a3 a2 a1 a0
DEC @Rr
0
0
0
1
0
1
1
r0
1
1
((Rr)) ¨ ((Rr))–1
ANL A, Rr
0
1
0
1
1
r2
r1
r0
1
1
(A) ¨ (A) AND (Rr)
ANL A, direct
0
1
0
1
0
1
0
1
2
1
(A) ¨ (A) AND (direct address)
r0
1
1
(A) ¨ (A) AND ((Rr))
2
1
(A) ¨ (A) AND #data
2
1
(direct address) ¨ (direct address)
AND (A)
3
2
(direct address) ¨ (direct address)
AND #data
ANL A, @Rr
ANL A, #data
Logical operation instructions
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
ANL direct, A
ANL direct,
#data
a7 a6 a5 a4
a3 a2 a1 a0
0
0
1
0
1
1
1
0
1
0
1
0
1
0
0
I7
I6
I5
I4
I3
I2
I1
I0
0
1
0
1
0
0
1
0
a7 a6 a5 a4
a3 a2 a1 a0
0
0
1
0
1
0
1
1
a7 a6 a5 a4
a3 a2 a1 a0
I7
I6
I5
I4
I3
I2
I1
I0
ORL A, Rr
0
1
0
0
1
r2
r1
r0
1
1
(A) ¨ (A) OR (Rr)
ORL A, direct
0
1
0
0
0
1
0
1
2
1
(A) ¨ (A) OR (direct address)
r0
1
1
(A) ¨ (A) OR ((Rr))
2
1
(A) ¨ (A) OR #data
2
1
(direct address) ¨ (direct address)
OR (A)
ORL A, @Rr
ORL A, #data
ORL direct, A
a7 a6 a5 a4
a3 a2 a1 a0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
0
I7
I6
I5
I4
I3
I2
I1
I0
0
1
0
0
0
0
1
0
a7 a6 a5 a4
a3 a2 a1 a0
16/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type
Mnemonic
Logical operation instructions
ORL direct,
#data
1
0
0
0
0
1
1
3
2
Description
(direct address) ¨ (direct address)
OR #data
a3 a2 a1 a0
I7
I6
I5
I4
I3
I2
I1
I0
XRL A, Rr
0
1
1
0
1
r2
r1
r0
1
1
(A) ¨ (A) XOR (Rr)
XRL A, direct
0
1
1
0
0
1
0
1
2
1
(A) ¨ (A) XOR (direct address)
a7 a6 a5 a4
a3 a2 a1 a0
XRL A, @Rr
0
1
1
0
0
1
1
r0
1
1
(A) ¨ (A) XOR ((Rr))
XRL A, #data
0
1
1
0
0
1
0
0
2
1
(A) ¨ (A) XOR #data
I7
I6
I5
I4
I3
I2
I1
I0
0
1
1
0
0
0
1
0
2
1
(direct address) ¨ (direct address)
XOR (A)
3
2
(direct address) ¨ (direct address)
XOR #data
2
1
(A) ¨ #data
2
1
(Rr) ¨ #data
3
2
(direct address) ¨ #data
2
1
(Rr)) ¨ #data
3
2
(DPTR) ¨ #data 16
XRL direct, A
MOV A, #data
Immediate data setting instructions
0
Bytes Cycles
a7 a6 a5 a4
XRL direct,
#data
Carry flag operation instructions
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
MOV Rr, #data
MOV direct,
#data
MOV @Rr,
#data
MOV DPTR,
#data 16
a7 a6 a5 a4
a3 a2 a1 a0
0
0
1
1
0
0
1
1
a7 a6 a5 a4
a3 a2 a1 a0
I7
I3
I6
I5
I4
I2
I1
I0
0
1
1
1
0
1
0
0
I7
I6
I5
I4
I3
I2
I1
I0
0
1
1
1
1
r2
r1
r0
I7
I6
I5
I4
I3
I2
I1
I0
0
1
1
1
0
1
0
1
a7 a6 a5 a4
a3 a2 a1 a0
I7
I6
I5
I4
I3
I2
I1
I0
0
1
1
1
0
1
1
r0
I7
I6
I5
I4
I3
I2
I1
I0
1
0
0
1
0
0
0
0
I15 I14 I13 I12 I11 I10 I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
CLR C
1
1
0
0
0
0
1
1
1
1
(C) ¨ 0
SETB C
1
1
0
1
0
0
1
1
1
1
(C) ¨ 1
CPL C
1
0
1
1
0
0
1
1
1
1
(C) ¨ (C)
1
0
0
0
0
0
1
0
2
2
(C) ¨ (C) AND (bit address)
2
2
(C) ¨ (C) AND (bit address)
2
2
(C) ¨ (C) OR (bit address)
2
2
(C) ¨ (C) OR (bit address)
ANL C, bit
b7 b6 b5 b4 b3 b2 b1 b0
ANL C,/bit
1
0
1
1
0
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
ORL C, bit
0
1
1
1
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
ORL C,/bit
1
0
1
0
0
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
17/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Carry flag
operation
instructions
Type
Mnemonic
MOV C, bit
1
0
1
0
0
0
1
0
Bytes Cycles
Description
2
1
(C) ¨ (bit address)
2
2
(bit address) ¨ (C)
2
1
(bit address) ¨ 1
2
1
(bit address) ¨ 0
2
1
(bit address) ¨ (bit address)
b7 b6 b5 b4 b3 b2 b1 b0
MOV bit, C
1
0
0
1
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
SETB bit
Bit operation
instructions
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
1
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
CLR bit
1
1
0
0
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
CPL bit
1
0
1
1
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
MOV A, Rr
MOV A, direct
Data transfer instructions
MOV A, @Rr
1
0
1
1
1
0
1
r2
r1
r0
1
1
(A) ¨ (Rr)
0
1
0
1
2
1
(A) ¨ (direct address)
r0
1
1
(A) ¨ ((Rr))
1
(Rr) ¨ (A)
a7 a6 a5 a4
a3 a2 a1 a0
1
0
1
1
0
1
1
1
1
1
1
1
r2
r1
r0
1
MOV Rr,
direct
1
0
1
0
1
r2
r1
r0
2
2
(Rr) ¨ (direct address)
2
1
(direct address) ¨ (A)
2
2
(direct address) ¨ (Rr)
3
2
(direct address 1) ¨ (direct address 2)
MOV direct, A
MOV direct,
Rr
MOV direct 1,
direct 2
MOV @Rr,
direct
Constant code
instructions
1
MOV Rr, A
MOV @Rr, A
Data exchange
instructions
1
a7 a6 a5 a4
a3 a2 a1 a0
1
0
1
1
1
1
0
1
a7 a6 a5 a4
a3 a2 a1 a0
1
1
0
0
0
r2
r1
r0
a7 a6 a5 a4
a3 a2 a1 a0
1
0
0
0
0
1
1
r0
2
a7
1
a7
2
a6
1
a6
2
a5
1
a5
2
a4
1
a4
2
a3
1
a3
2
a2
1
a2
2
a1
1
a1
2
a0
1
a0
1
1
1
1
0
1
1
r0
1
1
((Rr)) ¨ (A)
r0
2
2
((Rr)) ¨ (direct address)
1
0
1
0
0
1
1
a7 a6 a5 a4
a3 a2 a1 a0
MOVC A,
@A+DPTR
1
0
0
1
0
0
1
1
1
2
(A) ¨ ((A)+(DPTR))
MOVC A,
@A+PC
1
0
0
0
0
0
1
1
1
2
(PC) ¨ (PC+1)
(A) ¨ ((A)+(PC))
XCH A, Rr
1
1
0
0
1
r2
r1
r0
1
1
(A) ´ (Rr)
XCH A, direct
1
1
0
0
0
1
0
1
2
2
(A) ´ (direct address)
a7 a6 a5 a4
a3 a2 a1 a0
XCH A, @Rr
1
1
0
0
0
1
1
r0
1
1
(A) ´ ((Rr))
XCHD A, @Rr
1
1
0
1
0
1
1
r0
1
1
(A0 - 3) ´ ((Rr0 - 3))
18/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type
Mnemonic
PUSH direct
POP direct
Subroutine instructions
ACALL addr
11
LCALL addr
16
1
1
0
0
0
0
0
0
a7 a6 a5 a4
a3 a2 a1 a0
1
0
1
0
1
0
0
0
a7 a6 a5 a4
a3 a2 a1 a0
A10 A9 A8
0
1
0
0
1
Bytes Cycles
2
(SP) ¨ (SP)+1
((SP)) ¨ (direct address)
2
2
(direct address) ¨ ((SP))
(SP) ¨ (SP)–1
2
2
(PC) ¨ (PC)+2
(SP) ¨ (SP)+1
((SP)) ¨ (PC0 - 7)
(SP) ¨ (SP)+1
((SP)) ¨ (PC8 - 15)
(PC0 - 10) ¨ A0 - 10
3
2
(PC) ¨ (PC)+3
(SP) ¨ (SP)+1
((SP)) ¨ (PC0 - 7)
(SP) ¨ (SP)+1
((SP)) ¨ (PC8 - 15)
(PC0 - 10) ¨ A0 - 10
A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
1
0
0
1
0
Description
2
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
RET
0
0
1
0
0
0
1
0
1
2
(PC8 - 15) ¨ ((SP))
(SP) ¨ (SP)–1
(PC0 - 7) ¨ ((SP))
(SP) ¨ (SP)–1
RETI
0
0
1
1
0
0
1
0
1
2
(PC8 - 15) ¨ ((SP))
(SP) ¨ (SP)–1
(PC0 - 7) ¨ ((SP))
(SP) ¨ (SP)–1
A10 A9 A8
0
0
0
0
1
2
2
(PC) ¨ (PC)+2
(PC0 - 10) ¨ A0 - 10
3
2
(PC0 - 15) ¨ A0 - 15
2
2
(PC) ¨ (PC)+3
(SP) ¨ (SP)+1
1
2
(PC) ¨ (A)+(DPTR)
AJMP addr 11
Jump instructions
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
A7 A6 A5 A4 A3 A2 A1 A0
LJMP addr 16
0
0
0
0
0
0
1
0
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
SJMP rel
1
0
0
0
0
0
0
0
R7 R6 R5 R4 R3 R2 R1 R0
JMP @A+
DPTR
0
1
1
1
0
0
1
1
19/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type
Mnemonic
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
CJNE A, direct, 1 0 1 1
rel
a7 a6 a5 a4
0
1
0
1
Bytes Cycles
3
2
(PC) ¨ (PC)+3
IF
(A)π(direct address)
THEN
(PC) ¨ (PC)+relative offset
IF
(A)<(direct address)
THEN
(C) ¨ 1
ELSE
(C) ¨ 0
3
2
(PC) ¨ (PC)+3
IF
(A)π #data
THEN
(PC) ¨ (PC)+relative offset
IF
(A)< #data
THEN
(C) ¨ 1
ELSE
(C) ¨ 0
3
2
(PC) ¨ (PC)+3
IF
((Rr))π #data
THEN
(PC) ¨ (PC)+relative offset
IF
(Rr))< #data
THEN
(C) ¨ 1
ELSE
(C) ¨ 0
3
2
(PC) ¨ (PC)+3
IF
((Rr))π #data
THEN
(PC) ¨ (PC)+relative offset
IF
((Rr))< #data
THEN
(C) ¨ 1
ELSE
(C) ¨ 0
2
2
(PC) ¨ (PC)+2
(Rr) ¨ (Rr)–1
IF
(Rr)< 0
THEN
(PC) ¨ (PC)+relative offset
3
2
(PC) ¨ (PC)+3
(direct address) ¨ (direct address)–1
IF
(direct address)π 0
THEN
(PC) ¨ (PC)+relative offset
a3 a2 a1 a0
R7 R6 R5 R4 R3 R2 R1 R0
CJNE A, #data,
rel
1
0
1
1
0
1
0
0
I7
I6
I5
I4
I3
I2
I1
I0
Branch instructions
R7 R6 R5 R4 R3 R2 R1 R0
CJNE Rr,
#data, rel
1
0
1
1
1
r2
r1
r0
I7
I6
I5
I4
I3
I2
I1
I0
R7 R6 R5 R4 R3 R2 R1 R0
CJNE @Rr,
#data, rel
1
0
1
1
0
1
1
r0
I7
I6
I5
I4
I3
I2
I1
I0
R7 R6 R5 R4 R3 R2 R1 R0
DJNZ Rr, rel
1
1
0
1
1
r2
r1
r0
R7 R6 R5 R4 R3 R2 R1 R0
DJNZ direct,
rel
1
1
0
1
a7 a6 a5 a4
0
1
0
1
a3 a2 a1 a0
R7 R6 R5 R4 R3 R2 R1 R0
Description
20/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type
Mnemonic
JZ rel
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
0
0
0
0
0
Bytes Cycles
2
2
(PC) ¨ (PC)+2
IF
(A) = 0
THEN
(PC) ¨ (PC)+relative offset
2
2
(PC) ¨ (PC)+2
IF
(A) π 0
THEN
(PC) ¨ (PC)+relative offset
2
2
(PC) ¨ (PC)+2
IF
(C) = 1
THEN
(PC) ¨ (PC)+relative offset
2
2
(PC) ¨ (PC)+2
IF
(C) = 0
THEN
(PC) ¨ (PC)+relative offset
3
2
(PC) ¨ (PC)+3
IF
(bit address) = 1
THEN
(PC) ¨ (PC)+relative offset
3
2
(PC) ¨ (PC)+3
IF
(bit address) = 0
THEN
(PC) ¨ (PC)+relative offset
3
2
(PC) ¨ (PC)+3
IF
(bit address) = 1
THEN
(bit address) ¨ 0
(PC) ¨ (PC)+relative offset
R7 R6 R5 R4 R3 R2 R1 R0
JNZ rel
0
1
1
1
0
0
0
0
R7 R6 R5 R4 R3 R2 R1 R0
JC rel
0
1
0
0
0
0
0
0
Branch instructions
R7 R6 R5 R4 R3 R2 R1 R0
JNC rel
0
1
0
1
0
0
0
0
R7 R6 R5 R4 R3 R2 R1 R0
JB bit, rel
0
0
1
0
0
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
R7 R6 R5 R4 R3 R2 R1 R0
JNB bit, rel
0
0
1
1
0
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
R7 R6 R5 R4 R3 R2 R1 R0
JBC bit, rel
0
0
0
1
0
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
External
memory
instructions
R7 R6 R5 R4 R3 R2 R1 R0
Other
instructions
Description
MOVX A, @Rr
1
1
1
0
0
0
0
r0
1
2
(A) ¨ ((Rr)) EXTERNAL RAM
MOVX A,
@DPTR
1
1
1
0
0
0
0
0
1
2
(A) ¨ ((DPTR)) EXTERNAL RAM
MOVX @Rr, A
1
1
1
1
0
0
1
r0
1
2
(Rr) ¨ (A) EXTERNAL RAM
MOVX
@DPTR, A
1
1
1
1
0
0
0
0
1
2
((DPTP)) ¨ (A) EXTERNAL RAM
NOP
0
0
0
0
0
0
0
0
1
1
(PC) ¨ (PC)+1
21/38
¡ Semiconductor
MSM80C31F/80C51F
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Voltage from Any Pin to VSS
Storage Temperature
Symbol
Condition
Rating
Unit
VCC
Ta = 25°C
–0.5 to +7.0
V
VI
Ta = 25°C
–0.5 to VCC +7.0
V
TSTG
—
–55 to +150
°C
Symbol
Condition
Range
Unit
OPERATING RANGE
Parameter
Supply Voltage
VCC
See figure below
2.5 to 6
Memory Retention Voltage
VCC
fOSC = Oscillation stop
2 to 6
Oscillation Frequency
fOSC
Ambient Temperature
Ta
See figure below
DC to 16
MSM80C31F/51F
–40 to +85
MSM80C31F-1
–20 to +70
*1
V
V
*2
MHz
°C
*1 DC & AC characteristics in the range of 2.5 V £ VCC < 4 V will be specified by DC & AC
Characteristics 2.
*2 Specify MSM80C31F-1 when using MSM80C31F at 12 MHz to 16 MHz.
GUARANTEED OPERATING RANGE
Ta = –40 to +85°C (MSM80C31F/80C51F)
Ta = –20 to +70°C (MSM80C31F-1)
[ms]
10
5
3
Cycle Time (tcy)
4
Operating Range
3
6
2
MSM80C31/51
MSM80C31F/51F
1
12
0.75
Oscillation Frequency (fOSC)
1.2
16
MSM80C31F-1
2
3
4
5
6
[V]
Supply Voltage (VCC)
22/38
¡ Semiconductor
MSM80C31F/80C51F
ELECTRICAL CHARACTERISTICS
DC Characteristics 1
Parameter
MSM80C31F/51F
VCC = 5 V ±20%, VSS = 0 V, Ta = –40°C to +85°C
MSM80C31F-1/51F-1 VCC = 5 V ±5%, VSS = 0 V, Ta = –20°C to +70°C
MeasSymbol
Condition
Min.
Typ.
Max.
Unit uring
circuit
Low Input Voltage
VIL
High Input Voltage
VIH
High Input Voltage
VIH1
Low Output Voltage
(Port 1, 2 and 3)
Low Output Voltage
(Port 0, ALE and PSEN)
—
–0.5
—
0.2 VCC – 0.1
V
0.2 VCC + 0.9
—
VCC + 0.5
V
XTAL1, RESET and EA
0.7 VCC
—
VCC + 0.5
V
VOL
IOL = 1.6 mA
—
—
0.45
V
VOL1
IOL = 3.2 mA
—
—
0.45
V
2.4
—
—
V
IOH = –30 mA
0.75 VCC
—
—
V
IOH = –10 mA
0.9 VCC
—
—
V
2.4
—
—
V
IOH = –150 mA
0.75 VCC
—
—
V
IOH = –40 mA
0.9 VCC
—
—
V
–10
—
–200
mA
Except XTAL1, RESET
and EA
IOH = –60 mA
High Output Voltage
(Port 1, 2 and 3)
VOH
VCC = 5 V ±10%
IOH = –400 mA
High Output Voltage
(Port 0, ALE and PSEN)
Output Current at Low Input/
High Output Power Supply
Output Current (Port 1, 2
and 3) at transition from
H to L
Input Leakage Current
(Floating Port 0 and EA)
RESET Pull-down Resistor
VOH1
IIL / IOH
VCC = 5 V ±10%
VI = 0.45 V
VO = 0.45 V
1
2
ITL
VIL = 2.0 V
—
—
–500
mA
ILI
VSS < VI < VCC
—
—
±10
mA
3
RRST
—
20
40
125
kW
2
—
—
10
pF
—
—
1
50
mA
4
Input Pin Capacitor
CIO
Power Down Current
IPD
Ta = 25°C, f = 1 MHz
5 V (except XTAL1)
VCC = 2 V
23/38
¡ Semiconductor
MSM80C31F/80C51F
DC Characteristics 2
Parameter
Symbol
Condition
Low Input Voltage
VIL
—
High Input Voltage
VIH
High Input Voltage
VIH1
Low Output Voltage
(Port 1, 2 and 3)
Low Output Voltage
(Port 0, ALE and PSEN)
High Output Voltage
(Port 1, 2 and 3)
High Output Voltage
(Port 0, ALE and PSEN)
Output Current at Low Input/
High Output Power Supply
Output Current (Port 1, 2
and 3) at transition from
H to L
Input Leakage Current
(Floating Port 0 and EA)
RESET Pull-down Resistor
Except XTAL1, RESET
and EA
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –40 to +85°C)
MeasMin.
Typ.
Max.
Unit uring
circuit
–0.5
— 0.25VCC – 0.1
0.25VCC + 0.9 —
XTAL1, RESET and EA 0.6VCC + 0.6
V
VCC + 0.5
V
—
VCC + 0.5
V
0.1
V
VOL
IOL = 10 mA
—
—
VOL1
IOL = 20 mA
—
—
0.1
V
VOH
IOH = –5 mA
0.75 VCC
—
—
V
VOH1
IOH = –20 mA
0.75 VCC
—
—
V
—
—
–100
mA
1
IIL / IOH
VI = 0.1 V
VO = 0.1 V
2
ITL
VIL = 1.9 V
—
—
–300
mA
ILI
VSS < VI < VCC
—
—
±10
mA
3
RRST
—
20
40
125
kW
2
—
—
10
pF
—
—
1
10
mA
4
Input Pin Capacitor
CIO
Power Down Current
IPD
Ta = 25°C, f = 1 MHz
5 V (except XTAL1)
—
24/38
¡ Semiconductor
MSM80C31F/80C51F
Maximum operating power supply ICC [mA]
VCC
2.5 V
3.0 V
4.0 V
0.5 MHz
0.7
0.9
1.6
3.0 MHz
1.9
2.4
4.3
8 MHz
—
—
8.3
12 MHz
—
—
12.0
Freq
Maximum IDLE power supply ICC [mA]
VCC
2.5 V
3.0 V
4.0 V
0.5 MHz
0.3
0.4
0.6
3.0 MHz
0.6
0.8
1.2
8 MHz
—
—
2.2
12 MHz
—
—
3.1
Freq
25/38
¡ Semiconductor
MSM80C31F/80C51F
Measuring Circuit
1
2
A IO
VCC
OUTPUT
V
(*1)
INPUT
VIL
INPUT
(*3)
(*2)
OUTPUT
VCC
VIH
V A
VSS
VSS
3
4
A
VIH
V
VSS
A
(*3)
VIL
OUTPUT
VIL
VCC
INPUT
(*3)
INPUT
VIH
(*2)
OUTPUT
VCC
VSS
*1 Repeated for specified input pin.
*2 Repeated for specified output pin.
*3 Logic input for specified condition.
26/38
¡ Semiconductor
MSM80C31F/80C51F
External Program Memory Access AC Characteristics 1
(VCC = 5 V ±20%, VSS = 0 V, Ta = –40°C to +85°C; Load Capacitance for Port 0, ALE, and PSEN =
100 pF ; Load Capacitance for all other outputs = 80 pF)
Variable Clock
Parameter
Symbol
12 MHz Clock
Min.
Max.
See Guaranteed
Operating Range
Min.
Unit
Max.
XTAL1, XTAL2 Oscillation Cycle
tCLCL
—
—
83.3
—
ns
ALE Signal Width
tLHLL
126
—
2tCLCL – 40
—
ns
Adderss Setup Time
tAVLL
43
—
1tCLCL – 40
—
ns
tLLAX
48
—
1tCLCL – 35
—
ns
tLLIV
—
233
—
4tCLCL – 100
ns
tLLPL
58
—
1tCLCL – 25
—
ns
PSEN Signal Width
tPLPH
215
—
3tCLCL – 35
—
ns
Instruction Data Read Time
tPLIV
—
145
—
3tCLCL – 105
ns
tPXIX
0
—
0
—
ns
tPXIZ
—
63
—
1tCLCL – 20
ns
tPXAV
75
—
1tCLCL – 8
—
ns
tAVIV
—
312
—
5tCLCL – 105
ns
tPLAZ
—
0
—
0
ns
(to ALE Falling Edge)
Adderss Hold Time
(from ALE Falling Edge)
Instruction Data Read Time
(from ALE Falling Edge)
From ALE Falling Edge to
PSEN Falling Edge
(from PSEN Falling Edge)
Instruction Data Hold Time
(from PSEN Rising Edge)
Bus Floating Time after Instruction
Data Read (from PSEN Rising Edge)
Address Output Time from
PSEN Rising Edge
Instruction Data Read Time
(from Address Output)
Bus Floating Time (Address
Float from PSEN Falling Edge)
27/38
¡ Semiconductor
MSM80C31F/80C51F
External Program Memory Access AC Characteristics 2
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –40°C to +85°C; Load Capacitance for Port 0, ALE, and PSEN
= 100 pF ; Load Capacitance for all other outputs = 80 pF)
Variable Clock
12 MHz Clock
See Guaranteed
Operating Range
Parameter
Symbol
Unit
Min.
Max.
Min.
Max.
XTAL1, XTAL2 Oscillation Cycle
tCLCL
—
—
83.3
—
ns
ALE Signal Width
tLHLL
126
—
2tCLCL – 40
—
ns
Adderss Setup Time
tAVLL
43
—
1tCLCL – 40
—
ns
tLLAX
48
—
1tCLCL – 35
—
ns
tLLIV
—
233
—
4tCLCL – 100
ns
tLLPL
58
—
1tCLCL – 25
—
ns
PSEN Signal Width
tPLPH
215
—
3tCLCL – 35
—
ns
Instruction Data Read Time
tPLIV
—
145
—
3tCLCL – 105
ns
tPXIX
0
—
0
—
ns
tPXIZ
—
63
—
1tCLCL – 20
ns
tPXAV
75
—
1tCLCL – 8
—
ns
tAVIV
—
312
—
5tCLCL – 105
ns
tPLAZ
—
0
—
0
ns
(to ALE Falling Edge)
Adderss Hold Time
(from ALE Falling Edge)
Instruction Data Read Time
(from ALE Falling Edge)
From ALE Falling Edge to
PSEN Falling Edge
(from PSEN Falling Edge)
Instruction Data Hold Time
(from PSEN Rising Edge)
Bus Floating Time after Instruction
Data Read (from PSEN Rising Edge)
Address Output Time from
PSEN Rising Edge
Instruction Data Read Time
(from Address Output)
Bus Floating Time (Address
Float from PSEN Falling Edge)
28/38
¡ Semiconductor
MSM80C31F/80C51F
External Program Memory Read Cycle
tLHLL
ALE
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN
tPXAV
tPXIZ
tLLAX
PORT0
tPLAZ
tPXIX
INSTR
IN
A0~A7
A0~A7
tAVIV
PORT2
A8~A15
A8~A15
A8~A15
29/38
¡ Semiconductor
MSM80C31F/80C51F
External Data Memory Access AC Characteristics 1
(VCC = 5 V ±20%, VSS = 0 V, Ta = –40°C to +85°C; load capacitance for Port 0, ALE, and PSEN =
100 pF ; load capacitance for all other outputs = 80 pF)
Variable Clock
Parameter
Symbol
12 MHz Clock
Min.
Max.
See Guaranteed
Operating Range
Min.
Unit
Max.
XTAL1, XTAL2 Oscillation Cycle
tCLCL
—
—
62.5
—
ns
ALE Single Width
tLHLL
126
—
2tCLCL – 40
—
ns
Adderss Setup Time
tAVLL
43
—
1tCLCL – 40
—
ns
tLLAX
48
—
1tCLCL – 35
—
ns
RD Single Width
tRLRH
400
—
6tCLCL – 100
—
ns
WR Single Width
tWLWH
400
—
6tCLCL – 100
—
ns
RAM Data Read Time
tRLDV
—
251
—
5tCLCL – 165
ns
tRHDX
0
—
0
—
ns
tRHDZ
—
96
—
2tCLCL – 70
ns
tLLDV
—
516
—
8tCLCL – 150
ns
tAVDV
—
585
—
9tCLCL – 165
ns
tLLWL
200
300
3tCLCL – 50
3tCLCL + 50
ns
tAVWL
203
—
4tCLCL – 130
—
ns
RD Output Time from Data Output
tQVWX
23
—
1tCLCL – 60
—
ns
Time from Data Output to
tQVWH
433
—
7tCLCL – 150
—
ns
Data Hold Time (WR Rising Edge)
tWHQX
33
—
1tCLCL – 50
—
ns
Time from RD Output to
tRLAZ
—
0
—
0
ns
tWHLH
43
133
1tCLCL – 40
1tCLCL + 50
ns
(to ALE Falling Edge)
Adderss Hold Time
(from ALE Falling Edge)
(from RD Single Falling Edge)
RAM Data Read Hold Time
(from RD Single Rising Edge)
Data Bus Floating Time
(from RD Single Rising Edge)
RAM Data Read Time
(from ALE Single Falling Edge)
RAM Data Read Time
(from Address Output)
RD/WR Output Time from
ALE Falling Edge
RD/WR Output Time from
Address Output
WR Rising Edge
Address Float
Time from RD/WR Rising
Edge to ALE Rising Edge
30/38
¡ Semiconductor
MSM80C31F/80C51F
External Data Memory Access AC Characteristics 2
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –40°C to +85°C; load capacitance for Port 0, ALE, and PSEN =
100 pF ; load capacitance for all other outputs = 80 pF)
Variable Clock
12 MHz Clock
See Guaranteed
Operating Range
Parameter
Symbol
Unit
Min.
Max.
Min.
Max.
XTAL1, XTAL2 Oscillation Cycle
tCLCL
—
—
62.5
—
ns
ALE Single Width
tLHLL
126
—
2tCLCL – 40
—
ns
Adderss Setup Time
tAVLL
43
—
1tCLCL – 40
—
ns
tLLAX
48
—
1tCLCL – 35
—
ns
RD Single Width
tRLRH
400
—
6tCLCL – 100
—
ns
WR Single Width
tWLWH
400
—
6tCLCL – 100
—
ns
RAM Data Read Time
tRLDV
—
251
—
5tCLCL – 165
ns
tRHDX
0
—
0
—
ns
tRHDZ
—
96
—
2tCLCL – 70
ns
tLLDV
—
516
—
8tCLCL – 150
ns
tAVDV
—
585
—
9tCLCL – 165
ns
tLLWL
150
300
3tCLCL – 100
3tCLCL + 50
ns
tAVWL
203
—
4tCLCL – 130
—
ns
RD Output Time from Data Output
tQVWX
23
—
1tCLCL – 60
—
ns
Time from Data Output to
tQVWH
433
—
7tCLCL – 150
—
ns
Data Hold Time (WR Rising Edge)
tWHQX
33
—
1tCLCL – 50
—
ns
Time from RD Output to
tRLAZ
—
0
—
0
ns
tWHLH
43
183
1tCLCL – 40
1tCLCL + 100
ns
(to ALE Falling Edge)
Adderss Hold Time
(from ALE Falling Edge)
(from RD Single Falling Edge)
RAM Data Read Hold Time
(from RD Single Rising Edge)
Data Bus Floating Time
(from RD Single Rising Edge)
RAM Data Read Time
(from ALE Single Falling Edge)
RAM Data Read Time
(from Address Output)
RD/WR Output Time from
ALE Falling Edge
RD/WR Output Time from
Address Output
WR Rising Edge
Address Float
Time from RD/WR Rising
Edge to ALE Rising Edge
31/38
¡ Semiconductor
MSM80C31F/80C51F
External Data Memory Read Cycle
tWHLH
tLHLL
ALE
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL t t
LLAX RLAZ
PORT 0
INSTR
IN
A0~A7
PCL
PCH
tRHDX
A0~A7
Rr or DPL
tAVWL
PORT 2
tRHDZ
tRLDV
A8~A15 PCH
A0~A7
PCL
tAVDV
P2.0~P2.7 DATA or A8~A15 DPH
A8~A15 PCH
External Data Memory Write Cycle
tWHLH
tLHLL
ALE
PSEN
tLLWL
tWLWH
WR
tQVWH
tAVLL
tWHQX
tLLAX tQVWX
PORT 0
INSTR
IN
A0~A7
PCL
A0~A7
Rr or DPL
DATA (ACC)
A0~A7
PCL
tAVWL
PORT 2
A8~A15
PCH
A8~A15 PCH
P2.0~P2.7 DATA or A8~A15 DPH
A8~A15 PCH
32/38
¡ Semiconductor
MSM80C31F/80C51F
Serial Port Timing (I/O Expansion Mode) AC Characteristics 1
(Ta = –40°C to +85°C ; VCC = 5 V ±20% ; VSS = 0 V)
Symbol
Min.
Max.
Unit
Serial port clock cycle time
tXLXL
12tCLCL
—
ns
Output data setup to clock rising edge
tQVXH
10tCLCL – 133
—
ns
Output data hold after clock rising edge
tXHQX
2tCLCL – 117
—
ns
Input data hold after clock rising edge
tXHDX
0
—
ns
Clock rising edge to input data valid
tXHDV
—
10tCLCL – 133
ns
Parameter
MACHINE
CYCLE
0
1
2
3
4
5
6
7
8
ALE
tXLXL
SHIFT
CLOCK
tQVXH
OUTPUT
DATA
tXHQX
0
1
2
tXHDV
INPUT
DATA
VALID
3
4
5
6
7
tXHDX
VALID
VALID
VALID
VALID
VALID
VALID
VALID
33/38
¡ Semiconductor
MSM80C31F/80C51F
Serial Port Timing (I/O Expansion Mode) AC Characteristics 2
(Ta = –40°C to +85°C ; VC C =2.5 to 4.0 V ; VSS = 0 V)
Symbol
Min.
Max.
Unit
Serial port clock cycle time
tXLXL
12tCLCL
—
ns
Output data setup to clock rising edge
tQVXH
10tCLCL – 133
—
ns
Output data hold after clock rising edge
tXHQX
2tCLCL – 117
—
ns
Input data hold after clock rising edge
tXHDX
0
—
ns
Clock rising edge to input data valid
tXHDV
—
10tCLCL – 133
ns
Parameter
MACHINE
CYCLE
0
1
2
3
4
5
6
7
8
ALE
tXLXL
SHIFT
CLOCK
tQVXH
OUTPUT
DATA
tXHQX
0
1
2
tXHDV
INPUT
DATA
VALID
3
4
5
6
7
tXHDX
VALID
VALID
VALID
VALID
VALID
VALID
VALID
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¡ Semiconductor
MSM80C31F/80C51F
AC Characteristics Measuring Conditions
Input/output signal
VOH
VIH
VOH
VIH
TEST POINT
VIL
VOL
*
VIL
VOL
The input signals in AC test mode are either VOH (logic "1") or VOL (logic "0") input signals
where logic "1" corresponds to a CPU output signal waveform measuring point in excess of
VIH, and logic "0" to a point below VIL.
Floating
Floating
VOH
VOL
*
VIH
VIH
VIL
VIL
VOH
VOL
The port 0 floating interval is measured from the time the port 0 pin voltage drops below VIH
after sinking to GND at 2.4 mA when switching to floating status from a "1" output, and from
the time the port 0 pin voltage exceeds VIL after connecting to a 400 mA source when
switching to floating status from a "0" output.
XTAL1 External Clock Input Waveform Conditions
Variable Clock
Parameter
Symbol
Min.
Max.
Unit
External Clock Frequency
1/tCLCL
DC
16
MHz
See Guaranteed Operating Range
High Time
tCHCX
20
—
ns
Low Time
tCLCX
20
—
ns
Rise Time
tCLCH
—
20
ns
Fall Time
tCHCL
—
20
ns
External clock waveform
VCC – 0.5
0.45 V
0.7VCC
0.2VCC – 0.1
tCHCX
tCHCL
tCLCX
tCLCH
tCLCL
35/38
¡ Semiconductor
MSM80C31F/80C51F
PACKAGE DIMENSIONS
(Unit : mm)
DIP40-P-600-2.54
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
6.10 TYP.
36/38
¡ Semiconductor
MSM80C31F/80C51F
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
0.41 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
37/38
¡ Semiconductor
MSM80C31F/80C51F
(Unit : mm)
QFJ44-P-S650-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
2.00 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
38/38
E2Y0002-29-11
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1995 Oki Electric Industry Co., Ltd.
Printed in Japan